| commit | 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a | |
| author | Andy Fleming <afleming@freescale.com> | |
| Mon, 13 Aug 2007 19:49:59 +0000 (13 14:49 -0500) | ||
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | |
| Tue, 14 Aug 2007 06:44:55 +0000 (14 01:44 -0500) | ||
| tree | 2cbe4098e743b3e178ddb3bc97ca8ef9ec7107cd | treesnapshot (tar.gz zip) |
| parent | 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 | commitdiff |
MPC85xx BA bits not set for 3-bit bank address DIMM
The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).
Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).
Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
| cpu/mpc85xx/spd_sdram.c | diffblobblamehistory |