riscv: Use GAS syntax for loads/stores:
commit8cbbd2b88ac39815c79918610313984cc58db2bf
authorEkaitz Zarraga <ekaitz@elenq.tech>
Tue, 19 Mar 2024 10:11:25 +0000 (19 11:11 +0100)
committerEkaitz Zarraga <ekaitz@elenq.tech>
Tue, 19 Mar 2024 11:38:21 +0000 (19 12:38 +0100)
tree1813d0a9959eef443c808a89dd982b8012c178d6
parent019d10fc12c56657245d3cdf4f7a88175d85d700
riscv: Use GAS syntax for loads/stores:

Before:
    ld rd, rs, imm
    sd rs1, rs2, imm

Now:
    ld rd, imm(rs)
    sd rs2, imm(rs1)

NOTES: Just as in GAS:
    - In stores the register order is swapped
    - imm is optional
    - when imm is not included parenthesis can be removed
riscv64-asm.c