From 92fcdb3f4bae47d16fa9b2631856a135f26f8268 Mon Sep 17 00:00:00 2001 From: yajin Date: Mon, 19 Jan 2009 15:50:02 +0800 Subject: [PATCH] change TARGET_PHYS_ADDR_BITS t0 64 bits(same as qemu) --- hw/mips_jz.c | 10 +++++----- hw/mips_jz.h | 2 +- hw/mips_jz_glue.h | 21 +++------------------ target-mips/mips-defs.h | 6 ------ 4 files changed, 9 insertions(+), 30 deletions(-) diff --git a/hw/mips_jz.c b/hw/mips_jz.c index 913a06df12..ae3a432b87 100755 --- a/hw/mips_jz.c +++ b/hw/mips_jz.c @@ -2275,7 +2275,7 @@ static inline void jz4740_dma_transfer(struct jz4740_dma_s *s, pd_src = cpu_get_physical_page_desc(src); if ((pd_src & ~TARGET_PAGE_MASK) != IO_MEM_RAM) /* TODO */ - cpu_abort(cpu_single_env, "%s: DMA source address %x outside RAM!\n", + cpu_abort(cpu_single_env, "%s: DMA source address "JZ_FMT_plx" outside RAM!\n", __FUNCTION__, src); else sr = phys_ram_base + @@ -2285,7 +2285,7 @@ static inline void jz4740_dma_transfer(struct jz4740_dma_s *s, if ((pd_dest & ~TARGET_PAGE_MASK) != IO_MEM_RAM) /* TODO */ cpu_abort(cpu_single_env, - "%s: DMA destination address %x outside RAM!\n", + "%s: DMA destination address "JZ_FMT_plx" outside RAM!\n", __FUNCTION__, dest); else de = phys_ram_base + @@ -2362,8 +2362,8 @@ static inline void jz4740_dma_drun(struct jz4740_dma_s *s, int channel) if (!desc) cpu_abort(cpu_single_env, - "%s: DMA descriptor " JZ_FMT_plx " is NULL!\n", __FUNCTION__, - (uint32_t) desc); + "%s: DMA descriptor %x is NULL!\n", __FUNCTION__, + (uint32_t)desc); while (1) { @@ -2398,7 +2398,7 @@ static inline void jz4740_dma_drun(struct jz4740_dma_s *s, int channel) pd = cpu_get_physical_page_desc(desc_phy); if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) cpu_abort(cpu_single_env, - "%s: DMA descriptor address %x outside RAM!\n", + "%s: DMA descriptor address "JZ_FMT_plx" outside RAM!\n", __FUNCTION__, desc_phy); else desc = (struct jz4740_desc_s *) (phys_ram_base + diff --git a/hw/mips_jz.h b/hw/mips_jz.h index ad66da2646..b05256e1a3 100755 --- a/hw/mips_jz.h +++ b/hw/mips_jz.h @@ -102,7 +102,7 @@ -#define JZ_FMT_plx "%#16x" +#define JZ_FMT_plx "%#16llx" uint32_t jz4740_badwidth_read8(void *opaque, target_phys_addr_t addr); uint32_t jz4740_badwidth_read16(void *opaque, target_phys_addr_t addr); diff --git a/hw/mips_jz_glue.h b/hw/mips_jz_glue.h index 858bd129d0..c974e6344e 100755 --- a/hw/mips_jz_glue.h +++ b/hw/mips_jz_glue.h @@ -110,24 +110,17 @@ static inline void glue(jz4740_tcu_start_full, debug_out(DEBUG_TCU, "s->tsr %d s->ter %d s->freq[TCU_INDEX] %d \n", s->tsr , s->ter ,s->freq[TCU_INDEX]); -//printf("s->tsr %d s->ter %d s->freq[TCU_INDEX] %d \n", - // s->tsr , s->ter ,s->freq[TCU_INDEX]); if ((!(s->tsr & (1 << TCU_INDEX))) && (s->ter & (1 << TCU_INDEX)) && (s->freq[TCU_INDEX] != 0)) { glue(jz4740_tcu_time_sync, TCU_INDEX) (s); - //printf("tdfr %x \n",s->tdfr[TCU_INDEX] ); /*calculate next fire time */ count = (s->tdfr[TCU_INDEX] - s->tcnt[TCU_INDEX]) * s->prescale[TCU_INDEX]; - //printf("tdfr11 %x count %lld\n",s->tdfr[TCU_INDEX],count ); next += muldiv64(count, ticks_per_sec, s->freq[TCU_INDEX]); qemu_mod_timer(s->full_timer[TCU_INDEX], next); debug_out(DEBUG_TCU, "s->tdfr[TCU_INDEX] %d s->tcnt[TCU_INDEX] %d next %lld \n", s->tdfr[TCU_INDEX] , s->tcnt[TCU_INDEX] ,next); - //printf("s->tdfr[TCU_INDEX]22 %x s->tcnt[TCU_INDEX] %x next %lld \n", - // s->tdfr[TCU_INDEX] , s->tcnt[TCU_INDEX] ,next); - } else qemu_del_timer(s->full_timer[TCU_INDEX]); @@ -170,10 +163,8 @@ static void glue(jz4740_tcu_full_cb, TCU_INDEX) (void *opaque) if ((!(s->tsr & (1 << TCU_INDEX))) && (s->ter & (1 << TCU_INDEX)) && (s->freq[TCU_INDEX] != 0)) { - //printf("s->tdfr[TCU_INDEX] %x s->prescale[TCU_INDEX] %x \n",s->tdfr[TCU_INDEX] ,s->prescale[TCU_INDEX] ); count = s->tdfr[TCU_INDEX] * s->prescale[TCU_INDEX]; next += muldiv64(count, ticks_per_sec, s->freq[TCU_INDEX]); - //printf("count %lld next %lld \n",count,next); qemu_mod_timer(s->full_timer[TCU_INDEX], next); s->tfr |= 1 << TCU_INDEX; jz4740_tcu_update_interrupt(s); @@ -200,14 +191,12 @@ static uint32_t glue(jz4740_tcu_read, TCU_INDEX) (void *opaque, return s->tdhr[TCU_INDEX]; case 0x8: glue(jz4740_tcu_time_sync, TCU_INDEX) (s); - //debug_out(DEBUG_TCU, "s->tcnt %x\n", s->tcnt[TCU_INDEX]); - //printf("s->tcnt %x\n", s->tcnt[TCU_INDEX]); return s->tcnt[TCU_INDEX]; case 0xc: return s->tcsr[TCU_INDEX]; default: cpu_abort(s->soc->env, - "jz4740_tcu_read undefined addr %x timer %x \n", addr, + "jz4740_tcu_read undefined addr "JZ_FMT_plx" timer %x \n", addr, TCU_INDEX); } return (0); @@ -219,19 +208,15 @@ static void glue(jz4740_tcu_write, TCU_INDEX) (void *opaque, { struct jz4740_tcu_s *s = (struct jz4740_tcu_s *) opaque; - debug_out(DEBUG_TCU, "jz4740_tcu_write%x addr %x value %x \n", TCU_INDEX, + debug_out(DEBUG_TCU, "jz4740_tcu_write%x addr "JZ_FMT_plx" value %x \n", TCU_INDEX, addr, value); -//printf( "jz4740_tcu_write%x addr %x value %x \n", TCU_INDEX, -// addr, value); addr -= 0x40 + TCU_INDEX * 0x10; switch (addr) { case 0x0: /*TDFR*/ - s->tdfr[TCU_INDEX] = value & 0xffff; - //printf("s->tdfr[TCU_INDEX] %x \n",s->tdfr[TCU_INDEX] ); glue(jz4740_tcu_start_full, TCU_INDEX) (s); break; case 0x4: @@ -268,7 +253,7 @@ static void glue(jz4740_tcu_write, TCU_INDEX) (void *opaque, break; default: cpu_abort(s->soc->env, - "jz4740_tcu_write undefined addr %x timer %x \n", addr, + "jz4740_tcu_write undefined addr "JZ_FMT_plx" timer %x \n", addr, TCU_INDEX); } diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index d5d1a4cbaf..551aa7b06f 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -15,13 +15,7 @@ #endif /* Even MIPS32 can have 36 bits physical address space. */ -//#define TARGET_PHYS_ADDR_BITS 64 -/*Set TARGET_PHYS_ADDR_BITS will confuse the TARGET_FMT_plx macro */ -#if defined(TARGET_MIPS64) #define TARGET_PHYS_ADDR_BITS 64 -#else -#define TARGET_PHYS_ADDR_BITS 32 -#endif /* Masks used to mark instructions to indicate which ISA level they -- 2.11.4.GIT