target-mips/translate_init.c

   1 /*
   2  *  MIPS emulation for qemu: CPU initialisation routines.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *  Copyright (c) 2007 Herve Poussineau
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  20  */
  21
  22 /* CPU / CPU family specific config register values. */
  23
  24 /* Have config1, uncached coherency */
  25 #define MIPS_CONFIG0                                              \
  26   ((1 << CP0C0_M) | (0x2 << CP0C0_K0))
  27
  28 /* Have config2, no coprocessor2 attached, no MDMX support attached,
  29    no performance counters, watch registers present,
  30    no code compression, EJTAG present, no FPU */
  31 #define MIPS_CONFIG1                                              \
  32 ((1 << CP0C1_M) |                                                 \
  33  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
  34  (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
  35  (0 << CP0C1_FP))
  36
  37 /* Have config3, no tertiary/secondary caches implemented */
  38 #define MIPS_CONFIG2                                              \
  39 ((1 << CP0C2_M))
  40
  41 /* No config4, no DSP ASE, no large physaddr (PABITS),
  42    no external interrupt controller, no vectored interupts,
  43    no 1kb pages, no SmartMIPS ASE, no trace logic */
  44 #define MIPS_CONFIG3                                              \
  45 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  46  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  47  (0 << CP0C3_SM) | (0 << CP0C3_TL))
  48
  49 /* Define a implementation number of 1.
  50    Define a major version 1, minor version 0. */
  51 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
  52
  53 /* MMU types, the first four entries have the same layout as the
  54    CP0C0_MT field.  */
  55 enum mips_mmu_types {
  56     MMU_TYPE_NONE,
  57     MMU_TYPE_R4000,
  58     MMU_TYPE_RESERVED,
  59     MMU_TYPE_FMT,
  60     MMU_TYPE_R3000,
  61     MMU_TYPE_R6000,
  62     MMU_TYPE_R8000
  63 };
  64
  65 struct mips_def_t {
  66     const char *name;
  67     int32_t CP0_PRid;
  68     int32_t CP0_Config0;
  69     int32_t CP0_Config1;
  70     int32_t CP0_Config2;
  71     int32_t CP0_Config3;
  72     int32_t CP0_Config6;
  73     int32_t CP0_Config7;
  74     int32_t SYNCI_Step;
  75     int32_t CCRes;
  76     int32_t CP0_Status_rw_bitmask;
  77     int32_t CP0_TCStatus_rw_bitmask;
  78     int32_t CP0_SRSCtl;
  79     int32_t CP1_fcr0;
  80     int32_t SEGBITS;
  81     int32_t PABITS;
  82     int32_t CP0_SRSConf0_rw_bitmask;
  83     int32_t CP0_SRSConf0;
  84     int32_t CP0_SRSConf1_rw_bitmask;
  85     int32_t CP0_SRSConf1;
  86     int32_t CP0_SRSConf2_rw_bitmask;
  87     int32_t CP0_SRSConf2;
  88     int32_t CP0_SRSConf3_rw_bitmask;
  89     int32_t CP0_SRSConf3;
  90     int32_t CP0_SRSConf4_rw_bitmask;
  91     int32_t CP0_SRSConf4;
  92     int insn_flags;
  93     enum mips_mmu_types mmu_type;
  94 };
  95
  96 /*****************************************************************************/
  97 /* MIPS CPU definitions */
  98 static const mips_def_t mips_defs[] =
  99 {
 100     {
 101         .name = "4Kc",
 102         .CP0_PRid = 0x00018000,
 103         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
 104         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 105                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 106                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 107         .CP0_Config2 = MIPS_CONFIG2,
 108         .CP0_Config3 = MIPS_CONFIG3,
 109         .SYNCI_Step = 32,
 110         .CCRes = 2,
 111         .CP0_Status_rw_bitmask = 0x1278FF17,
 112         .SEGBITS = 32,
 113         .PABITS = 32,
 114         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 115         .mmu_type = MMU_TYPE_R4000,
 116     },
 117     {
 118         .name = "4Km",
 119         .CP0_PRid = 0x00018300,
 120         /* Config1 implemented, fixed mapping MMU,
 121            no virtual icache, uncached coherency. */
 122         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
 123         .CP0_Config1 = MIPS_CONFIG1 |
 124                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 125                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 126         .CP0_Config2 = MIPS_CONFIG2,
 127         .CP0_Config3 = MIPS_CONFIG3,
 128         .SYNCI_Step = 32,
 129         .CCRes = 2,
 130         .CP0_Status_rw_bitmask = 0x1258FF17,
 131         .SEGBITS = 32,
 132         .PABITS = 32,
 133         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 134         .mmu_type = MMU_TYPE_FMT,
 135     },
 136     {
 137         .name = "4KEcR1",
 138         .CP0_PRid = 0x00018400,
 139         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
 140         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 141                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 142                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 143         .CP0_Config2 = MIPS_CONFIG2,
 144         .CP0_Config3 = MIPS_CONFIG3,
 145         .SYNCI_Step = 32,
 146         .CCRes = 2,
 147         .CP0_Status_rw_bitmask = 0x1278FF17,
 148         .SEGBITS = 32,
 149         .PABITS = 32,
 150         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 151         .mmu_type = MMU_TYPE_R4000,
 152     },
 153     {
 154         .name = "4KEmR1",
 155         .CP0_PRid = 0x00018500,
 156         .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
 157         .CP0_Config1 = MIPS_CONFIG1 |
 158                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 159                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 160         .CP0_Config2 = MIPS_CONFIG2,
 161         .CP0_Config3 = MIPS_CONFIG3,
 162         .SYNCI_Step = 32,
 163         .CCRes = 2,
 164         .CP0_Status_rw_bitmask = 0x1258FF17,
 165         .SEGBITS = 32,
 166         .PABITS = 32,
 167         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 168         .mmu_type = MMU_TYPE_FMT,
 169     },
 170     {
 171         .name = "4KEc",
 172         .CP0_PRid = 0x00019000,
 173         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 174                     (MMU_TYPE_R4000 << CP0C0_MT),
 175         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 176                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 177                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 178         .CP0_Config2 = MIPS_CONFIG2,
 179         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 180         .SYNCI_Step = 32,
 181         .CCRes = 2,
 182         .CP0_Status_rw_bitmask = 0x1278FF17,
 183         .SEGBITS = 32,
 184         .PABITS = 32,
 185         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 186         .mmu_type = MMU_TYPE_R4000,
 187     },
 188     {
 189         .name = "jz4740",
 190         .CP0_PRid = 0x0ad0024f,
 191         .CP0_Config0 = 0x80000082,
 192         .CP0_Config1 = 0x3E613080,
 193         .CP0_Config7 = 0,
 194         .SYNCI_Step = 32,
 195         .CCRes = 2,
 196         .CP0_Status_rw_bitmask = 0x1278FF17,
 197         .SEGBITS = 32,
 198         .PABITS = 32,
 199         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 200         .mmu_type = MMU_TYPE_R4000,
 201     },
 202     {
 203         .name = "4KEm",
 204         .CP0_PRid = 0x00019100,
 205         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 206                     (MMU_TYPE_FMT << CP0C0_MT),
 207         .CP0_Config1 = MIPS_CONFIG1 |
 208                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 209                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 210         .CP0_Config2 = MIPS_CONFIG2,
 211         .CP0_Config3 = MIPS_CONFIG3,
 212         .SYNCI_Step = 32,
 213         .CCRes = 2,
 214         .CP0_Status_rw_bitmask = 0x1258FF17,
 215         .SEGBITS = 32,
 216         .PABITS = 32,
 217         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 218         .mmu_type = MMU_TYPE_FMT,
 219     },
 220     {
 221         .name = "24Kc",
 222         .CP0_PRid = 0x00019300,
 223         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 224                     (MMU_TYPE_R4000 << CP0C0_MT),
 225         .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 226                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 227                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 228         .CP0_Config2 = MIPS_CONFIG2,
 229         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 230         .SYNCI_Step = 32,
 231         .CCRes = 2,
 232         /* No DSP implemented. */
 233         .CP0_Status_rw_bitmask = 0x1278FF1F,
 234         .SEGBITS = 32,
 235         .PABITS = 32,
 236         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 237         .mmu_type = MMU_TYPE_R4000,
 238     },
 239     {
 240         .name = "24Kf",
 241         .CP0_PRid = 0x00019300,
 242         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 243                     (MMU_TYPE_R4000 << CP0C0_MT),
 244         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 245                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 246                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 247         .CP0_Config2 = MIPS_CONFIG2,
 248         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 249         .SYNCI_Step = 32,
 250         .CCRes = 2,
 251         /* No DSP implemented. */
 252         .CP0_Status_rw_bitmask = 0x3678FF1F,
 253         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 254                     (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 255         .SEGBITS = 32,
 256         .PABITS = 32,
 257         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 258         .mmu_type = MMU_TYPE_R4000,
 259     },
 260     {
 261         .name = "34Kf",
 262         .CP0_PRid = 0x00019500,
 263         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 264                     (MMU_TYPE_R4000 << CP0C0_MT),
 265         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 266                     (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 267                     (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 268         .CP0_Config2 = MIPS_CONFIG2,
 269         .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),
 270         .SYNCI_Step = 32,
 271         .CCRes = 2,
 272         /* No DSP implemented. */
 273         .CP0_Status_rw_bitmask = 0x3678FF1F,
 274         /* No DSP implemented. */
 275         .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
 276                     (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
 277                     (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
 278                     (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
 279                     (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
 280                     (0xff << CP0TCSt_TASID),
 281         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 282                     (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
 283         .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 284         .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
 285         .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
 286                     (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
 287         .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
 288         .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
 289                     (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
 290         .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
 291         .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
 292                     (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
 293         .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
 294         .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
 295                     (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
 296         .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
 297         .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
 298                     (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
 299         .SEGBITS = 32,
 300         .PABITS = 32,
 301         .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
 302         .mmu_type = MMU_TYPE_R4000,
 303     },
 304 #if defined(TARGET_MIPS64)
 305     {
 306         .name = "R4000",
 307         .CP0_PRid = 0x00000400,
 308         /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
 309         .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
 310         /* Note: Config1 is only used internally, the R4000 has only Config0. */
 311         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 312         .SYNCI_Step = 16,
 313         .CCRes = 2,
 314         .CP0_Status_rw_bitmask = 0x3678FFFF,
 315         /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
 316         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
 317         .SEGBITS = 40,
 318         .PABITS = 36,
 319         .insn_flags = CPU_MIPS3,
 320         .mmu_type = MMU_TYPE_R4000,
 321     },
 322     {
 323         .name = "VR5432",
 324         .CP0_PRid = 0x00005400,
 325         /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
 326         .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
 327         .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 328         .SYNCI_Step = 16,
 329         .CCRes = 2,
 330         .CP0_Status_rw_bitmask = 0x3678FFFF,
 331         /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
 332         .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
 333         .SEGBITS = 40,
 334         .PABITS = 32,
 335         .insn_flags = CPU_VR54XX,
 336         .mmu_type = MMU_TYPE_R4000,
 337     },
 338     {
 339         .name = "5Kc",
 340         .CP0_PRid = 0x00018100,
 341         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 342                     (MMU_TYPE_R4000 << CP0C0_MT),
 343         .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
 344                     (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 345                     (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 346                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 347         .CP0_Config2 = MIPS_CONFIG2,
 348         .CP0_Config3 = MIPS_CONFIG3,
 349         .SYNCI_Step = 32,
 350         .CCRes = 2,
 351         .CP0_Status_rw_bitmask = 0x32F8FFFF,
 352         .SEGBITS = 42,
 353         .PABITS = 36,
 354         .insn_flags = CPU_MIPS64,
 355         .mmu_type = MMU_TYPE_R4000,
 356     },
 357     {
 358         .name = "5Kf",
 359         .CP0_PRid = 0x00018100,
 360         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 361                     (MMU_TYPE_R4000 << CP0C0_MT),
 362         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 363                     (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 364                     (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 365                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 366         .CP0_Config2 = MIPS_CONFIG2,
 367         .CP0_Config3 = MIPS_CONFIG3,
 368         .SYNCI_Step = 32,
 369         .CCRes = 2,
 370         .CP0_Status_rw_bitmask = 0x36F8FFFF,
 371         /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 372         .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 373                     (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
 374         .SEGBITS = 42,
 375         .PABITS = 36,
 376         .insn_flags = CPU_MIPS64,
 377         .mmu_type = MMU_TYPE_R4000,
 378     },
 379     {
 380         .name = "20Kc",
 381         /* We emulate a later version of the 20Kc, earlier ones had a broken
 382            WAIT instruction. */
 383         .CP0_PRid = 0x000182a0,
 384         .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 385                     (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
 386         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
 387                     (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 388                     (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 389                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 390         .CP0_Config2 = MIPS_CONFIG2,
 391         .CP0_Config3 = MIPS_CONFIG3,
 392         .SYNCI_Step = 32,
 393         .CCRes = 1,
 394         .CP0_Status_rw_bitmask = 0x36FBFFFF,
 395         /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
 396         .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 397                     (1 << FCR0_D) | (1 << FCR0_S) |
 398                     (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
 399         .SEGBITS = 40,
 400         .PABITS = 36,
 401         .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
 402         .mmu_type = MMU_TYPE_R4000,
 403     },
 404     {
 405         /* A generic CPU providing MIPS64 Release 2 features.
 406            FIXME: Eventually this should be replaced by a real CPU model. */
 407         .name = "MIPS64R2-generic",
 408         .CP0_PRid = 0x00010000,
 409         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 410                     (MMU_TYPE_R4000 << CP0C0_MT),
 411         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 412                     (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 413                     (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 414                     (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 415         .CP0_Config2 = MIPS_CONFIG2,
 416         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
 417         .SYNCI_Step = 32,
 418         .CCRes = 2,
 419         .CP0_Status_rw_bitmask = 0x36FBFFFF,
 420         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
 421                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 422                     (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 423         .SEGBITS = 42,
 424         /* The architectural limit is 59, but we have hardcoded 36 bit
 425            in some places...
 426         .PABITS = 59, */ /* the architectural limit */
 427         .PABITS = 36,
 428         .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
 429         .mmu_type = MMU_TYPE_R4000,
 430     },
 431 #endif
 432 };
 433
 434 static const mips_def_t *cpu_mips_find_by_name (const char *name)
 435 {
 436     int i;
 437
 438     for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
 439         if (strcasecmp(name, mips_defs[i].name) == 0) {
 440             return &mips_defs[i];
 441         }
 442     }
 443     return NULL;
 444 }
 445
 446 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 447 {
 448     int i;
 449
 450     for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
 451         (*cpu_fprintf)(f, "MIPS '%s'\n",
 452                        mips_defs[i].name);
 453     }
 454 }
 455
 456 #ifndef CONFIG_USER_ONLY
 457 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 458 {
 459     env->tlb->nb_tlb = 1;
 460     env->tlb->map_address = &no_mmu_map_address;
 461 }
 462
 463 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 464 {
 465     env->tlb->nb_tlb = 1;
 466     env->tlb->map_address = &fixed_mmu_map_address;
 467 }
 468
 469 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 470 {
 471     env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
 472     env->tlb->map_address = &r4k_map_address;
 473     env->tlb->do_tlbwi = r4k_do_tlbwi;
 474     env->tlb->do_tlbwr = r4k_do_tlbwr;
 475     env->tlb->do_tlbp = r4k_do_tlbp;
 476     env->tlb->do_tlbr = r4k_do_tlbr;
 477 }
 478
 479 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
 480 {
 481     env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
 482
 483     switch (def->mmu_type) {
 484         case MMU_TYPE_NONE:
 485             no_mmu_init(env, def);
 486             break;
 487         case MMU_TYPE_R4000:
 488             r4k_mmu_init(env, def);
 489             break;
 490         case MMU_TYPE_FMT:
 491             fixed_mmu_init(env, def);
 492             break;
 493         case MMU_TYPE_R3000:
 494         case MMU_TYPE_R6000:
 495         case MMU_TYPE_R8000:
 496         default:
 497             cpu_abort(env, "MMU type not supported\n");
 498     }
 499     env->CP0_Random = env->tlb->nb_tlb - 1;
 500     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 501 }
 502 #endif /* CONFIG_USER_ONLY */
 503
 504 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 505 {
 506     int i;
 507
 508     for (i = 0; i < MIPS_FPU_MAX; i++)
 509         env->fpus[i].fcr0 = def->CP1_fcr0;
 510
 511     memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
 512 #if defined(CONFIG_USER_ONLY)
 513     if (env->CP0_Config1 & (1 << CP0C1_FP))
 514         env->hflags |= MIPS_HFLAG_FPU;
 515 #ifdef TARGET_MIPS64
 516     if (env->active_fpu.fcr0 & (1 << FCR0_F64))
 517         env->hflags |= MIPS_HFLAG_F64;
 518 #endif
 519 #endif
 520 }
 521
 522 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
 523 {
 524     env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
 525
 526     /* MVPConf1 implemented, TLB sharable, no gating storage support,
 527        programmable cache partitioning implemented, number of allocatable
 528        and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
 529        implemented, 5 TCs implemented. */
 530     env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
 531                              (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
 532 // TODO: actually do 2 VPEs.
 533 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
 534 //                             (0x04 << CP0MVPC0_PTC);
 535                              (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
 536                              (0x04 << CP0MVPC0_PTC);
 537 #if !defined(CONFIG_USER_ONLY)
 538     /* Usermode has no TLB support */
 539     env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
 540 #endif
 541
 542     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
 543        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
 544     env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
 545                              (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
 546                              (0x1 << CP0MVPC1_PCP1);
 547 }
 548
 549 static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
 550 {
 551     env->CP0_PRid = def->CP0_PRid;
 552     env->CP0_Config0 = def->CP0_Config0;
 553 #ifdef TARGET_WORDS_BIGENDIAN
 554     env->CP0_Config0 |= (1 << CP0C0_BE);
 555 #endif
 556     env->CP0_Config1 = def->CP0_Config1;
 557     env->CP0_Config2 = def->CP0_Config2;
 558     env->CP0_Config3 = def->CP0_Config3;
 559     env->CP0_Config6 = def->CP0_Config6;
 560     env->CP0_Config7 = def->CP0_Config7;
 561     env->SYNCI_Step = def->SYNCI_Step;
 562     env->CCRes = def->CCRes;
 563     env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
 564     env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
 565     env->CP0_SRSCtl = def->CP0_SRSCtl;
 566     env->current_tc = 0;
 567     env->SEGBITS = def->SEGBITS;
 568     env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1);
 569 #if defined(TARGET_MIPS64)
 570     if (def->insn_flags & ISA_MIPS3) {
 571         env->hflags |= MIPS_HFLAG_64;
 572         env->SEGMask |= 3ULL << 62;
 573     }
 574 #endif
 575     env->PABITS = def->PABITS;
 576     env->PAMask = (target_ulong)((1ULL << def->PABITS) - 1);
 577     env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask;
 578     env->CP0_SRSConf0 = def->CP0_SRSConf0;
 579     env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask;
 580     env->CP0_SRSConf1 = def->CP0_SRSConf1;
 581     env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask;
 582     env->CP0_SRSConf2 = def->CP0_SRSConf2;
 583     env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask;
 584     env->CP0_SRSConf3 = def->CP0_SRSConf3;
 585     env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask;
 586     env->CP0_SRSConf4 = def->CP0_SRSConf4;
 587     env->insn_flags = def->insn_flags;
 588
 589 #ifndef CONFIG_USER_ONLY
 590     mmu_init(env, def);
 591 #endif
 592     fpu_init(env, def);
 593     mvp_init(env, def);
 594     return 0;
 595 }