From d42f183c0452a9c769b91e3911566566724983ff Mon Sep 17 00:00:00 2001 From: aurel32 Date: Mon, 9 Mar 2009 18:50:53 +0000 Subject: [PATCH] Implement TCG rotation ops for x86-64 Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162 --- tcg/tcg-op.h | 28 ++++++++++++++++++++++++++++ tcg/tcg-opc.h | 8 ++++++-- tcg/x86_64/tcg-target.c | 22 ++++++++++++++++++++-- tcg/x86_64/tcg-target.h | 2 ++ 4 files changed, 56 insertions(+), 4 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 970c590ae5..4c1c5bddb0 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1573,6 +1573,9 @@ static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_rot_i32 + tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2); +#else TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); @@ -1583,10 +1586,14 @@ static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) tcg_gen_or_i32(ret, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); +#endif } static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_rot_i64 + tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2); +#else TCGv_i64 t0, t1; t0 = tcg_temp_new_i64(); @@ -1597,6 +1604,7 @@ static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) tcg_gen_or_i64(ret, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); +#endif } static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) @@ -1605,6 +1613,11 @@ static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { +#ifdef TCG_TARGET_HAS_rot_i32 + TCGv_i32 t0 = tcg_const_i32(arg2); + tcg_gen_rotl_i32(ret, arg1, t0); + tcg_temp_free_i32(t0); +#else TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32(); @@ -1613,6 +1626,7 @@ static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) tcg_gen_or_i32(ret, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); +#endif } } @@ -1622,6 +1636,11 @@ static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) if (arg2 == 0) { tcg_gen_mov_i64(ret, arg1); } else { +#ifdef TCG_TARGET_HAS_rot_i64 + TCGv_i64 t0 = tcg_const_i64(arg2); + tcg_gen_rotl_i64(ret, arg1, t0); + tcg_temp_free_i64(t0); +#else TCGv_i64 t0, t1; t0 = tcg_temp_new_i64(); t1 = tcg_temp_new_i64(); @@ -1630,11 +1649,15 @@ static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) tcg_gen_or_i64(ret, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); +#endif } } static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_rot_i32 + tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2); +#else TCGv_i32 t0, t1; t0 = tcg_temp_new_i32(); @@ -1645,10 +1668,14 @@ static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) tcg_gen_or_i32(ret, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); +#endif } static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_rot_i64 + tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2); +#else TCGv_i64 t0, t1; t0 = tcg_temp_new_i64(); @@ -1659,6 +1686,7 @@ static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) tcg_gen_or_i64(ret, t0, t1); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); +#endif } static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 17c4bfba83..9b7b863c06 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -67,10 +67,12 @@ DEF2(divu2_i32, 2, 3, 0, 0) DEF2(and_i32, 1, 2, 0, 0) DEF2(or_i32, 1, 2, 0, 0) DEF2(xor_i32, 1, 2, 0, 0) -/* shifts */ +/* shifts/rotates */ DEF2(shl_i32, 1, 2, 0, 0) DEF2(shr_i32, 1, 2, 0, 0) DEF2(sar_i32, 1, 2, 0, 0) +DEF2(rotl_i32, 1, 2, 0, 0) +DEF2(rotr_i32, 1, 2, 0, 0) DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) #if TCG_TARGET_REG_BITS == 32 @@ -120,10 +122,12 @@ DEF2(divu2_i64, 2, 3, 0, 0) DEF2(and_i64, 1, 2, 0, 0) DEF2(or_i64, 1, 2, 0, 0) DEF2(xor_i64, 1, 2, 0, 0) -/* shifts */ +/* shifts/rotates */ DEF2(shl_i64, 1, 2, 0, 0) DEF2(shr_i64, 1, 2, 0, 0) DEF2(sar_i64, 1, 2, 0, 0) +DEF2(rotl_i64, 1, 2, 0, 0) +DEF2(rotr_i64, 1, 2, 0, 0) DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) #ifdef TCG_TARGET_HAS_ext8s_i64 diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c index 33327d1d11..60968327b3 100644 --- a/tcg/x86_64/tcg-target.c +++ b/tcg/x86_64/tcg-target.c @@ -194,6 +194,8 @@ static inline int tcg_target_const_match(tcg_target_long val, #define ARITH_XOR 6 #define ARITH_CMP 7 +#define SHIFT_ROL 0 +#define SHIFT_ROR 1 #define SHIFT_SHL 4 #define SHIFT_SHR 5 #define SHIFT_SAR 7 @@ -1049,7 +1051,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, case INDEX_op_sar_i32: c = SHIFT_SAR; goto gen_shift32; - + case INDEX_op_rotl_i32: + c = SHIFT_ROL; + goto gen_shift32; + case INDEX_op_rotr_i32: + c = SHIFT_ROR; + goto gen_shift32; + case INDEX_op_shl_i64: c = SHIFT_SHL; gen_shift64: @@ -1070,7 +1078,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, case INDEX_op_sar_i64: c = SHIFT_SAR; goto gen_shift64; - + case INDEX_op_rotl_i64: + c = SHIFT_ROL; + goto gen_shift64; + case INDEX_op_rotr_i64: + c = SHIFT_ROR; + goto gen_shift64; + case INDEX_op_brcond_i32: tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3], 0); @@ -1230,6 +1244,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = { { INDEX_op_shl_i32, { "r", "0", "ci" } }, { INDEX_op_shr_i32, { "r", "0", "ci" } }, { INDEX_op_sar_i32, { "r", "0", "ci" } }, + { INDEX_op_rotl_i32, { "r", "0", "ci" } }, + { INDEX_op_rotr_i32, { "r", "0", "ci" } }, { INDEX_op_brcond_i32, { "r", "ri" } }, @@ -1259,6 +1275,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = { { INDEX_op_shl_i64, { "r", "0", "ci" } }, { INDEX_op_shr_i64, { "r", "0", "ci" } }, { INDEX_op_sar_i64, { "r", "0", "ci" } }, + { INDEX_op_rotl_i64, { "r", "0", "ci" } }, + { INDEX_op_rotr_i64, { "r", "0", "ci" } }, { INDEX_op_brcond_i64, { "r", "re" } }, diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 77d0709d6b..1eadf422f1 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -65,6 +65,8 @@ enum { #define TCG_TARGET_HAS_ext8s_i64 #define TCG_TARGET_HAS_ext16s_i64 #define TCG_TARGET_HAS_ext32s_i64 +#define TCG_TARGET_HAS_rot_i32 +#define TCG_TARGET_HAS_rot_i64 /* Note: must be synced with dyngen-exec.h */ #define TCG_AREG0 TCG_REG_R14 -- 2.11.4.GIT