From c42410681dccbe88b13c30fd5661c47be2cc2ef3 Mon Sep 17 00:00:00 2001 From: Michel Date: Mon, 23 Feb 2009 14:15:11 +0000 Subject: [PATCH] [S3C] Make s3c aware of 2440s Introduced a cpu_id field to handle S3C2440, at least for the general ourpose register for chip id. --- hw/s3c.h | 8 ++++++-- hw/s3c2410.c | 8 +++++--- hw/s3c24xx_gpio.c | 10 ++++++---- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/hw/s3c.h b/hw/s3c.h index 29bc1a98c1..84874b7590 100644 --- a/hw/s3c.h +++ b/hw/s3c.h @@ -13,6 +13,9 @@ # include "flash.h" # include "sd.h" +#define S3C_CPU_2410 0x32410002 +#define S3C_CPU_2440 0x32440001 + /* Interrupt numbers */ # define S3C_PIC_EINT0 0 # define S3C_PIC_EINT1 1 @@ -143,7 +146,7 @@ struct s3c_wdt_state_s *s3c_wdt_init(target_phys_addr_t base, qemu_irq irq); /* s3c24xx_gpio.c */ struct s3c_gpio_state_s; -struct s3c_gpio_state_s *s3c_gpio_init(target_phys_addr_t base, qemu_irq *pic); +struct s3c_gpio_state_s *s3c_gpio_init(target_phys_addr_t base, qemu_irq *pic, uint32_t cpu_id); qemu_irq *s3c_gpio_in_get(struct s3c_gpio_state_s *s); void s3c_gpio_out_set(struct s3c_gpio_state_s *s, int line, qemu_irq handler); void s3c_gpio_setpwrstat(struct s3c_gpio_state_s *s, int stat); @@ -183,6 +186,7 @@ void s3c_spi_attach(struct s3c_spi_state_s *s, int ch, struct s3c_state_s { CPUState *env; + uint32_t cpu_id; qemu_irq *irq; qemu_irq *drq; struct s3c_pic_state_s *pic; @@ -219,7 +223,7 @@ struct s3c_state_s { }; /* s3c2410.c */ -struct s3c_state_s *s3c2410_init(unsigned int sdram_size, DisplayState *ds, +struct s3c_state_s *s3c24xx_init(uint32_t cpu_id, unsigned int sdram_size, DisplayState *ds, SDState *mmc); void s3c_nand_register(struct s3c_state_s *s, struct nand_flash_s *chip); void s3c_nand_setwp(struct s3c_state_s *s, int wp); diff --git a/hw/s3c2410.c b/hw/s3c2410.c index 10e47c29e4..355b246dab 100644 --- a/hw/s3c2410.c +++ b/hw/s3c2410.c @@ -2838,15 +2838,17 @@ static void s3c2410_reset(void *opaque) } /* Initialise an S3C2410A microprocessor. */ -struct s3c_state_s *s3c2410_init(unsigned int sdram_size, DisplayState *ds, +struct s3c_state_s *s3c24xx_init(uint32_t cpu_id, unsigned int sdram_size, DisplayState *ds, SDState *mmc) { struct s3c_state_s *s; int iomemtype, i; s = (struct s3c_state_s *) qemu_mallocz(sizeof(struct s3c_state_s)); + s->cpu_id = cpu_id; + s->env = cpu_init("arm920t"); - register_savevm("s3c2410", 0, 0, + register_savevm("s3c24xx", 0, 0, cpu_save, cpu_load, s->env); cpu_register_physical_memory(S3C_RAM_BASE, sdram_size, @@ -2903,7 +2905,7 @@ struct s3c_state_s *s3c2410_init(unsigned int sdram_size, DisplayState *ds, s->i2s = s3c_i2s_init(0x55000000, s->drq); - s->io = s3c_gpio_init(0x56000000, s->irq); + s->io = s3c_gpio_init(0x56000000, s->irq, s->cpu_id); s->rtc = s3c_rtc_init(0x57000000, s->irq[S3C_PIC_RTC]); diff --git a/hw/s3c24xx_gpio.c b/hw/s3c24xx_gpio.c index c0f17d3fa0..c7aa67e5be 100644 --- a/hw/s3c24xx_gpio.c +++ b/hw/s3c24xx_gpio.c @@ -13,6 +13,7 @@ #define S3C_IO_BANKS 8 struct s3c_gpio_state_s { /* Modelled as an interrupt controller */ + uint32_t cpu_id; target_phys_addr_t base; qemu_irq *pic; qemu_irq *in; @@ -184,7 +185,7 @@ static uint32_t s3c_gpio_read(void *opaque, target_phys_addr_t addr) case S3C_GSTATUS0: return 0x0; case S3C_GSTATUS1: - return 0x32410002; + return s->cpu_id; case S3C_GSTATUS2: return s->pwrstat; case S3C_GSTATUS3: @@ -217,7 +218,7 @@ static uint32_t s3c_gpio_read(void *opaque, target_phys_addr_t addr) case S3C_GPUP: return s->bank[bank].up; default: - printf("%s: Bad register 0x%lx\n", __FUNCTION__, addr); + printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr); break; } return 0; @@ -299,7 +300,7 @@ static void s3c_gpio_write(void *opaque, target_phys_addr_t addr, s->bank[bank].up = value; break; default: - printf("%s: Bad register 0x%lx\n", __FUNCTION__, addr); + printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr); } } @@ -367,12 +368,13 @@ static int s3c_gpio_load(QEMUFile *f, void *opaque, int version_id) return 0; } -struct s3c_gpio_state_s *s3c_gpio_init(target_phys_addr_t base, qemu_irq *pic) +struct s3c_gpio_state_s *s3c_gpio_init(target_phys_addr_t base, qemu_irq *pic, uint32_t cpu_id) { int iomemtype; struct s3c_gpio_state_s *s = (struct s3c_gpio_state_s *) qemu_mallocz(sizeof(struct s3c_gpio_state_s)); + s->cpu_id = cpu_id; s->base = base; s->pic = pic; s->in = qemu_allocate_irqs(s3c_gpio_set, s, S3C_GP_MAX); -- 2.11.4.GIT