From 105f198c21dd8b2cb553768d468d8714e6a56c15 Mon Sep 17 00:00:00 2001
From: Michel Pollet <buserror@gmail.com>
Date: Mon, 23 Feb 2009 23:11:48 +0000
Subject: [PATCH] [S3C] S3C2440 compatibility changes

Supports a few different registers to accomodate S3C2440
---
 hw/s3c.h          |  2 +-
 hw/s3c2410.c      | 15 ++++++++++++++-
 hw/s3c24xx_gpio.c |  2 ++
 hw/s3c24xx_mmci.c |  3 +++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/hw/s3c.h b/hw/s3c.h
index ae1acaa91f..ef25f77320 100644
--- a/hw/s3c.h
+++ b/hw/s3c.h
@@ -222,7 +222,7 @@ struct s3c_state_s {
 
     /* Clock & power management */
     target_phys_addr_t clkpwr_base;
-    uint32_t clkpwr_regs[6];
+    uint32_t clkpwr_regs[6 + 1];	// 6 2410. 1 2440
 };
 
 /* s3c2410.c */
diff --git a/hw/s3c2410.c b/hw/s3c2410.c
index 833fee9477..7c14d93fa8 100644
--- a/hw/s3c2410.c
+++ b/hw/s3c2410.c
@@ -447,6 +447,8 @@ static int s3c_mc_load(QEMUFile *f, void *opaque, int version_id)
 #define S3C_CLKSLOW	0x10	/* Slow Clock Control register */
 #define S3C_CLKDIVN	0x14	/* Clock Divider Control register */
 
+#define S3C2440_CAMDIVN	0x18	/* Camera Clock Divider register */
+
 static void s3c_clkpwr_reset(struct s3c_state_s *s)
 {
     s->clkpwr_regs[S3C_LOCKTIME >> 2] = 0x00ffffff;
@@ -455,6 +457,7 @@ static void s3c_clkpwr_reset(struct s3c_state_s *s)
     s->clkpwr_regs[S3C_CLKCON >> 2] = 0x0007fff0;
     s->clkpwr_regs[S3C_CLKSLOW >> 2] = 0x00000004;
     s->clkpwr_regs[S3C_CLKDIVN >> 2] = 0x00000000;
+    s->clkpwr_regs[S3C2440_CAMDIVN >> 2] = 0x00000000;
 }
 
 static uint32_t s3c_clkpwr_read(void *opaque, target_phys_addr_t addr)
@@ -464,6 +467,9 @@ static uint32_t s3c_clkpwr_read(void *opaque, target_phys_addr_t addr)
     switch (addr) {
     case S3C_LOCKTIME ... S3C_CLKDIVN:
         return s->clkpwr_regs[addr >> 2];
+    case S3C2440_CAMDIVN:
+    	if (s->cpu_id == S3C_CPU_2440)
+    		return s->clkpwr_regs[addr >> 2];
     default:
         printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
         break;
@@ -506,8 +512,13 @@ static void s3c_clkpwr_write(void *opaque, target_phys_addr_t addr,
                             (value & (1 << 4)) ? "on" : "off");
         s->clkpwr_regs[addr >> 2] = value;
         break;
+    case S3C2440_CAMDIVN:
+    	if (s->cpu_id == S3C_CPU_2440) {
+    		s->clkpwr_regs[addr >> 2] = value;
+    		break;
+    	}
     default:
-        printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
+        printf("%s: Bad register 0x%lx (cpu %08x)\n", __FUNCTION__, /*(unsigned long)*/addr, s->cpu_id);
     }
 }
 
@@ -1340,6 +1351,8 @@ static uint32_t s3c_uart_read(void *opaque, target_phys_addr_t addr)
     case S3C_UMSTAT:
         s3c_uart_update(s);
         return 0x11;
+    case S3C_UTXH:	/* why this is called by u-boot is not clear */
+    	return 0;
     case S3C_URXH:
         s3c_uart_update(s);
         if (s->rxlen) {
diff --git a/hw/s3c24xx_gpio.c b/hw/s3c24xx_gpio.c
index 33337c8f59..0c67dba8f4 100644
--- a/hw/s3c24xx_gpio.c
+++ b/hw/s3c24xx_gpio.c
@@ -10,6 +10,8 @@
 #include "s3c.h"
 #include "hw.h"
 
+/* S3C2410 : A B C D E F G H  = 8 
+ * S3C2440 : J = 1 */
 #define S3C_IO_BANKS	8
 
 struct s3c_gpio_state_s {	/* Modelled as an interrupt controller */
diff --git a/hw/s3c24xx_mmci.c b/hw/s3c24xx_mmci.c
index 2b9fc63eed..d846afc092 100644
--- a/hw/s3c24xx_mmci.c
+++ b/hw/s3c24xx_mmci.c
@@ -347,6 +347,9 @@ static void s3c_mmci_writew(void *opaque, target_phys_addr_t addr,
     case S3C_SDIDSTA:
         s->dstatus &= ~(value & 0x3f8);
         break;
+    case S3C_SDIFSTA:
+    	/* write is tolerated on the s3c2440 */
+    	break;
     case S3C_SDIDAT:
         s->fifo[(s->fifostart + s->fifolen ++) & 63] = (value >> 0) & 0xff;
         s->fifo[(s->fifostart + s->fifolen ++) & 63] = (value >> 8) & 0xff;
-- 
2.11.4.GIT