hw/spitz.c

   1 /*
   2  * PXA270-based Clamshell PDA platforms.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GNU GPL v2.
   8  */
   9
  10 #include "hw.h"
  11 #include "pxa.h"
  12 #include "arm-misc.h"
  13 #include "sysemu.h"
  14 #include "pcmcia.h"
  15 #include "i2c.h"
  16 #include "ssi.h"
  17 #include "flash.h"
  18 #include "qemu-timer.h"
  19 #include "devices.h"
  20 #include "sharpsl.h"
  21 #include "console.h"
  22 #include "block.h"
  23 #include "audio/audio.h"
  24 #include "boards.h"
  25
  26 #undef REG_FMT
  27 #if TARGET_PHYS_ADDR_BITS == 32
  28 #define REG_FMT                 "0x%02x"
  29 #else
  30 #define REG_FMT                 "0x%02lx"
  31 #endif
  32
  33 /* Spitz Flash */
  34 #define FLASH_BASE              0x0c000000
  35 #define FLASH_ECCLPLB           0x00    /* Line parity 7 - 0 bit */
  36 #define FLASH_ECCLPUB           0x04    /* Line parity 15 - 8 bit */
  37 #define FLASH_ECCCP             0x08    /* Column parity 5 - 0 bit */
  38 #define FLASH_ECCCNTR           0x0c    /* ECC byte counter */
  39 #define FLASH_ECCCLRR           0x10    /* Clear ECC */
  40 #define FLASH_FLASHIO           0x14    /* Flash I/O */
  41 #define FLASH_FLASHCTL          0x18    /* Flash Control */
  42
  43 #define FLASHCTL_CE0            (1 << 0)
  44 #define FLASHCTL_CLE            (1 << 1)
  45 #define FLASHCTL_ALE            (1 << 2)
  46 #define FLASHCTL_WP             (1 << 3)
  47 #define FLASHCTL_CE1            (1 << 4)
  48 #define FLASHCTL_RYBY           (1 << 5)
  49 #define FLASHCTL_NCE            (FLASHCTL_CE0 | FLASHCTL_CE1)
  50
  51 typedef struct {
  52     NANDFlashState *nand;
  53     uint8_t ctl;
  54     ECCState ecc;
  55 } SLNANDState;
  56
  57 static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
  58 {
  59     SLNANDState *s = (SLNANDState *) opaque;
  60     int ryby;
  61
  62     switch (addr) {
  63 #define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
  64     case FLASH_ECCLPLB:
  65         return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
  66                 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
  67
  68 #define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
  69     case FLASH_ECCLPUB:
  70         return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
  71                 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
  72
  73     case FLASH_ECCCP:
  74         return s->ecc.cp;
  75
  76     case FLASH_ECCCNTR:
  77         return s->ecc.count & 0xff;
  78
  79     case FLASH_FLASHCTL:
  80         nand_getpins(s->nand, &ryby);
  81         if (ryby)
  82             return s->ctl | FLASHCTL_RYBY;
  83         else
  84             return s->ctl;
  85
  86     case FLASH_FLASHIO:
  87         return ecc_digest(&s->ecc, nand_getio(s->nand));
  88
  89     default:
  90         zaurus_printf("Bad register offset " REG_FMT "\n", addr);
  91     }
  92     return 0;
  93 }
  94
  95 static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
  96 {
  97     SLNANDState *s = (SLNANDState *) opaque;
  98
  99     if (addr == FLASH_FLASHIO)
 100         return ecc_digest(&s->ecc, nand_getio(s->nand)) |
 101                 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
 102
 103     return sl_readb(opaque, addr);
 104 }
 105
 106 static void sl_writeb(void *opaque, target_phys_addr_t addr,
 107                 uint32_t value)
 108 {
 109     SLNANDState *s = (SLNANDState *) opaque;
 110
 111     switch (addr) {
 112     case FLASH_ECCCLRR:
 113         /* Value is ignored.  */
 114         ecc_reset(&s->ecc);
 115         break;
 116
 117     case FLASH_FLASHCTL:
 118         s->ctl = value & 0xff & ~FLASHCTL_RYBY;
 119         nand_setpins(s->nand,
 120                         s->ctl & FLASHCTL_CLE,
 121                         s->ctl & FLASHCTL_ALE,
 122                         s->ctl & FLASHCTL_NCE,
 123                         s->ctl & FLASHCTL_WP,
 124                         0);
 125         break;
 126
 127     case FLASH_FLASHIO:
 128         nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
 129         break;
 130
 131     default:
 132         zaurus_printf("Bad register offset " REG_FMT "\n", addr);
 133     }
 134 }
 135
 136 static void sl_save(QEMUFile *f, void *opaque)
 137 {
 138     SLNANDState *s = (SLNANDState *) opaque;
 139
 140     qemu_put_8s(f, &s->ctl);
 141     ecc_put(f, &s->ecc);
 142 }
 143
 144 static int sl_load(QEMUFile *f, void *opaque, int version_id)
 145 {
 146     SLNANDState *s = (SLNANDState *) opaque;
 147
 148     qemu_get_8s(f, &s->ctl);
 149     ecc_get(f, &s->ecc);
 150
 151     return 0;
 152 }
 153
 154 enum {
 155     FLASH_128M,
 156     FLASH_1024M,
 157 };
 158
 159 static void sl_flash_register(PXA2xxState *cpu, int size)
 160 {
 161     int iomemtype;
 162     SLNANDState *s;
 163     CPUReadMemoryFunc *sl_readfn[] = {
 164         sl_readb,
 165         sl_readb,
 166         sl_readl,
 167     };
 168     CPUWriteMemoryFunc *sl_writefn[] = {
 169         sl_writeb,
 170         sl_writeb,
 171         sl_writeb,
 172     };
 173
 174     s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState));
 175     s->ctl = 0;
 176     if (size == FLASH_128M)
 177         s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73);
 178     else if (size == FLASH_1024M)
 179         s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1);
 180
 181     iomemtype = cpu_register_io_memory(0, sl_readfn,
 182                     sl_writefn, s);
 183     cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype);
 184
 185     register_savevm("sl_flash", 0, 0, sl_save, sl_load, s);
 186 }
 187
 188 /* Spitz Keyboard */
 189
 190 #define SPITZ_KEY_STROBE_NUM    11
 191 #define SPITZ_KEY_SENSE_NUM     7
 192
 193 static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
 194     12, 17, 91, 34, 36, 38, 39
 195 };
 196
 197 static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
 198     88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
 199 };
 200
 201 /* Eighth additional row maps the special keys */
 202 static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
 203     { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
 204     {  -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
 205     { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25,  -1 ,  -1 ,  -1  },
 206     { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26,  -1 , 0x36,  -1  },
 207     { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34,  -1 , 0x1c, 0x2a,  -1  },
 208     { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33,  -1 , 0x48,  -1 ,  -1 , 0x38 },
 209     { 0x37, 0x3d,  -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d,  -1 ,  -1  },
 210     { 0x52, 0x43, 0x01, 0x47, 0x49,  -1 ,  -1 ,  -1 ,  -1 ,  -1 ,  -1  },
 211 };
 212
 213 #define SPITZ_GPIO_AK_INT       13      /* Remote control */
 214 #define SPITZ_GPIO_SYNC         16      /* Sync button */
 215 #define SPITZ_GPIO_ON_KEY       95      /* Power button */
 216 #define SPITZ_GPIO_SWA          97      /* Lid */
 217 #define SPITZ_GPIO_SWB          96      /* Tablet mode */
 218
 219 /* The special buttons are mapped to unused keys */
 220 static const int spitz_gpiomap[5] = {
 221     SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
 222     SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
 223 };
 224 static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, };
 225
 226 typedef struct {
 227     qemu_irq sense[SPITZ_KEY_SENSE_NUM];
 228     qemu_irq *strobe;
 229     qemu_irq gpiomap[5];
 230     int keymap[0x80];
 231     uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
 232     uint16_t strobe_state;
 233     uint16_t sense_state;
 234
 235     uint16_t pre_map[0x100];
 236     uint16_t modifiers;
 237     uint16_t imodifiers;
 238     uint8_t fifo[16];
 239     int fifopos, fifolen;
 240     QEMUTimer *kbdtimer;
 241 } SpitzKeyboardState;
 242
 243 static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
 244 {
 245     int i;
 246     uint16_t strobe, sense = 0;
 247     for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
 248         strobe = s->keyrow[i] & s->strobe_state;
 249         if (strobe) {
 250             sense |= 1 << i;
 251             if (!(s->sense_state & (1 << i)))
 252                 qemu_irq_raise(s->sense[i]);
 253         } else if (s->sense_state & (1 << i))
 254             qemu_irq_lower(s->sense[i]);
 255     }
 256
 257     s->sense_state = sense;
 258 }
 259
 260 static void spitz_keyboard_strobe(void *opaque, int line, int level)
 261 {
 262     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 263
 264     if (level)
 265         s->strobe_state |= 1 << line;
 266     else
 267         s->strobe_state &= ~(1 << line);
 268     spitz_keyboard_sense_update(s);
 269 }
 270
 271 static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
 272 {
 273     int spitz_keycode = s->keymap[keycode & 0x7f];
 274     if (spitz_keycode == -1)
 275         return;
 276
 277     /* Handle the additional keys */
 278     if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
 279         qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^
 280                         spitz_gpio_invert[spitz_keycode & 0xf]);
 281         return;
 282     }
 283
 284     if (keycode & 0x80)
 285         s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
 286     else
 287         s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
 288
 289     spitz_keyboard_sense_update(s);
 290 }
 291
 292 #define SHIFT   (1 << 7)
 293 #define CTRL    (1 << 8)
 294 #define FN      (1 << 9)
 295
 296 #define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
 297
 298 static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode)
 299 {
 300     uint16_t code;
 301     int mapcode;
 302     switch (keycode) {
 303     case 0x2a:  /* Left Shift */
 304         s->modifiers |= 1;
 305         break;
 306     case 0xaa:
 307         s->modifiers &= ~1;
 308         break;
 309     case 0x36:  /* Right Shift */
 310         s->modifiers |= 2;
 311         break;
 312     case 0xb6:
 313         s->modifiers &= ~2;
 314         break;
 315     case 0x1d:  /* Control */
 316         s->modifiers |= 4;
 317         break;
 318     case 0x9d:
 319         s->modifiers &= ~4;
 320         break;
 321     case 0x38:  /* Alt */
 322         s->modifiers |= 8;
 323         break;
 324     case 0xb8:
 325         s->modifiers &= ~8;
 326         break;
 327     }
 328
 329     code = s->pre_map[mapcode = ((s->modifiers & 3) ?
 330             (keycode | SHIFT) :
 331             (keycode & ~SHIFT))];
 332
 333     if (code != mapcode) {
 334 #if 0
 335         if ((code & SHIFT) && !(s->modifiers & 1))
 336             QUEUE_KEY(0x2a | (keycode & 0x80));
 337         if ((code & CTRL ) && !(s->modifiers & 4))
 338             QUEUE_KEY(0x1d | (keycode & 0x80));
 339         if ((code & FN   ) && !(s->modifiers & 8))
 340             QUEUE_KEY(0x38 | (keycode & 0x80));
 341         if ((code & FN   ) && (s->modifiers & 1))
 342             QUEUE_KEY(0x2a | (~keycode & 0x80));
 343         if ((code & FN   ) && (s->modifiers & 2))
 344             QUEUE_KEY(0x36 | (~keycode & 0x80));
 345 #else
 346         if (keycode & 0x80) {
 347             if ((s->imodifiers & 1   ) && !(s->modifiers & 1))
 348                 QUEUE_KEY(0x2a | 0x80);
 349             if ((s->imodifiers & 4   ) && !(s->modifiers & 4))
 350                 QUEUE_KEY(0x1d | 0x80);
 351             if ((s->imodifiers & 8   ) && !(s->modifiers & 8))
 352                 QUEUE_KEY(0x38 | 0x80);
 353             if ((s->imodifiers & 0x10) && (s->modifiers & 1))
 354                 QUEUE_KEY(0x2a);
 355             if ((s->imodifiers & 0x20) && (s->modifiers & 2))
 356                 QUEUE_KEY(0x36);
 357             s->imodifiers = 0;
 358         } else {
 359             if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
 360                 QUEUE_KEY(0x2a);
 361                 s->imodifiers |= 1;
 362             }
 363             if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
 364                 QUEUE_KEY(0x1d);
 365                 s->imodifiers |= 4;
 366             }
 367             if ((code & FN   ) && !((s->modifiers | s->imodifiers) & 8)) {
 368                 QUEUE_KEY(0x38);
 369                 s->imodifiers |= 8;
 370             }
 371             if ((code & FN   ) && (s->modifiers & 1) &&
 372                             !(s->imodifiers & 0x10)) {
 373                 QUEUE_KEY(0x2a | 0x80);
 374                 s->imodifiers |= 0x10;
 375             }
 376             if ((code & FN   ) && (s->modifiers & 2) &&
 377                             !(s->imodifiers & 0x20)) {
 378                 QUEUE_KEY(0x36 | 0x80);
 379                 s->imodifiers |= 0x20;
 380             }
 381         }
 382 #endif
 383     }
 384
 385     QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
 386 }
 387
 388 static void spitz_keyboard_tick(void *opaque)
 389 {
 390     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 391
 392     if (s->fifolen) {
 393         spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
 394         s->fifolen --;
 395         if (s->fifopos >= 16)
 396             s->fifopos = 0;
 397     }
 398
 399     qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + ticks_per_sec / 32);
 400 }
 401
 402 static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
 403 {
 404     int i;
 405     for (i = 0; i < 0x100; i ++)
 406         s->pre_map[i] = i;
 407     s->pre_map[0x02 | SHIFT     ] = 0x02 | SHIFT;       /* exclam */
 408     s->pre_map[0x28 | SHIFT     ] = 0x03 | SHIFT;       /* quotedbl */
 409     s->pre_map[0x04 | SHIFT     ] = 0x04 | SHIFT;       /* numbersign */
 410     s->pre_map[0x05 | SHIFT     ] = 0x05 | SHIFT;       /* dollar */
 411     s->pre_map[0x06 | SHIFT     ] = 0x06 | SHIFT;       /* percent */
 412     s->pre_map[0x08 | SHIFT     ] = 0x07 | SHIFT;       /* ampersand */
 413     s->pre_map[0x28             ] = 0x08 | SHIFT;       /* apostrophe */
 414     s->pre_map[0x0a | SHIFT     ] = 0x09 | SHIFT;       /* parenleft */
 415     s->pre_map[0x0b | SHIFT     ] = 0x0a | SHIFT;       /* parenright */
 416     s->pre_map[0x29 | SHIFT     ] = 0x0b | SHIFT;       /* asciitilde */
 417     s->pre_map[0x03 | SHIFT     ] = 0x0c | SHIFT;       /* at */
 418     s->pre_map[0xd3             ] = 0x0e | FN;          /* Delete */
 419     s->pre_map[0x3a             ] = 0x0f | FN;          /* Caps_Lock */
 420     s->pre_map[0x07 | SHIFT     ] = 0x11 | FN;          /* asciicircum */
 421     s->pre_map[0x0d             ] = 0x12 | FN;          /* equal */
 422     s->pre_map[0x0d | SHIFT     ] = 0x13 | FN;          /* plus */
 423     s->pre_map[0x1a             ] = 0x14 | FN;          /* bracketleft */
 424     s->pre_map[0x1b             ] = 0x15 | FN;          /* bracketright */
 425     s->pre_map[0x1a | SHIFT     ] = 0x16 | FN;          /* braceleft */
 426     s->pre_map[0x1b | SHIFT     ] = 0x17 | FN;          /* braceright */
 427     s->pre_map[0x27             ] = 0x22 | FN;          /* semicolon */
 428     s->pre_map[0x27 | SHIFT     ] = 0x23 | FN;          /* colon */
 429     s->pre_map[0x09 | SHIFT     ] = 0x24 | FN;          /* asterisk */
 430     s->pre_map[0x2b             ] = 0x25 | FN;          /* backslash */
 431     s->pre_map[0x2b | SHIFT     ] = 0x26 | FN;          /* bar */
 432     s->pre_map[0x0c | SHIFT     ] = 0x30 | FN;          /* underscore */
 433     s->pre_map[0x33 | SHIFT     ] = 0x33 | FN;          /* less */
 434     s->pre_map[0x35             ] = 0x33 | SHIFT;       /* slash */
 435     s->pre_map[0x34 | SHIFT     ] = 0x34 | FN;          /* greater */
 436     s->pre_map[0x35 | SHIFT     ] = 0x34 | SHIFT;       /* question */
 437     s->pre_map[0x49             ] = 0x48 | FN;          /* Page_Up */
 438     s->pre_map[0x51             ] = 0x50 | FN;          /* Page_Down */
 439
 440     s->modifiers = 0;
 441     s->imodifiers = 0;
 442     s->fifopos = 0;
 443     s->fifolen = 0;
 444     s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s);
 445     spitz_keyboard_tick(s);
 446 }
 447
 448 #undef SHIFT
 449 #undef CTRL
 450 #undef FN
 451
 452 static void spitz_keyboard_save(QEMUFile *f, void *opaque)
 453 {
 454     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 455     int i;
 456
 457     qemu_put_be16s(f, &s->sense_state);
 458     qemu_put_be16s(f, &s->strobe_state);
 459     for (i = 0; i < 5; i ++)
 460         qemu_put_byte(f, spitz_gpio_invert[i]);
 461 }
 462
 463 static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id)
 464 {
 465     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 466     int i;
 467
 468     qemu_get_be16s(f, &s->sense_state);
 469     qemu_get_be16s(f, &s->strobe_state);
 470     for (i = 0; i < 5; i ++)
 471         spitz_gpio_invert[i] = qemu_get_byte(f);
 472
 473     /* Release all pressed keys */
 474     memset(s->keyrow, 0, sizeof(s->keyrow));
 475     spitz_keyboard_sense_update(s);
 476     s->modifiers = 0;
 477     s->imodifiers = 0;
 478     s->fifopos = 0;
 479     s->fifolen = 0;
 480
 481     return 0;
 482 }
 483
 484 static void spitz_keyboard_register(PXA2xxState *cpu)
 485 {
 486     int i, j;
 487     SpitzKeyboardState *s;
 488
 489     s = (SpitzKeyboardState *)
 490             qemu_mallocz(sizeof(SpitzKeyboardState));
 491     memset(s, 0, sizeof(SpitzKeyboardState));
 492
 493     for (i = 0; i < 0x80; i ++)
 494         s->keymap[i] = -1;
 495     for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
 496         for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
 497             if (spitz_keymap[i][j] != -1)
 498                 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
 499
 500     for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
 501         s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]];
 502
 503     for (i = 0; i < 5; i ++)
 504         s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]];
 505
 506     s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s,
 507                     SPITZ_KEY_STROBE_NUM);
 508     for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
 509         pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]);
 510
 511     spitz_keyboard_pre_map(s);
 512     qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s);
 513
 514     register_savevm("spitz_keyboard", 0, 0,
 515                     spitz_keyboard_save, spitz_keyboard_load, s);
 516 }
 517
 518 /* LCD backlight controller */
 519
 520 #define LCDTG_RESCTL    0x00
 521 #define LCDTG_PHACTRL   0x01
 522 #define LCDTG_DUTYCTRL  0x02
 523 #define LCDTG_POWERREG0 0x03
 524 #define LCDTG_POWERREG1 0x04
 525 #define LCDTG_GPOR3     0x05
 526 #define LCDTG_PICTRL    0x06
 527 #define LCDTG_POLCTRL   0x07
 528
 529 typedef struct {
 530     SSISlave ssidev;
 531     int bl_intensity;
 532     int bl_power;
 533 } SpitzLCDTG;
 534
 535 static void spitz_bl_update(SpitzLCDTG *s)
 536 {
 537     if (s->bl_power && s->bl_intensity)
 538         zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
 539     else
 540         zaurus_printf("LCD Backlight now off\n");
 541 }
 542
 543 /* FIXME: Implement GPIO properly and remove this hack.  */
 544 static SpitzLCDTG *spitz_lcdtg;
 545
 546 static inline void spitz_bl_bit5(void *opaque, int line, int level)
 547 {
 548     SpitzLCDTG *s = spitz_lcdtg;
 549     int prev = s->bl_intensity;
 550
 551     if (level)
 552         s->bl_intensity &= ~0x20;
 553     else
 554         s->bl_intensity |= 0x20;
 555
 556     if (s->bl_power && prev != s->bl_intensity)
 557         spitz_bl_update(s);
 558 }
 559
 560 static inline void spitz_bl_power(void *opaque, int line, int level)
 561 {
 562     SpitzLCDTG *s = spitz_lcdtg;
 563     s->bl_power = !!level;
 564     spitz_bl_update(s);
 565 }
 566
 567 static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
 568 {
 569     SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
 570     int addr;
 571     addr = value >> 5;
 572     value &= 0x1f;
 573
 574     switch (addr) {
 575     case LCDTG_RESCTL:
 576         if (value)
 577             zaurus_printf("LCD in QVGA mode\n");
 578         else
 579             zaurus_printf("LCD in VGA mode\n");
 580         break;
 581
 582     case LCDTG_DUTYCTRL:
 583         s->bl_intensity &= ~0x1f;
 584         s->bl_intensity |= value;
 585         if (s->bl_power)
 586             spitz_bl_update(s);
 587         break;
 588
 589     case LCDTG_POWERREG0:
 590         /* Set common voltage to M62332FP */
 591         break;
 592     }
 593     return 0;
 594 }
 595
 596 static void spitz_lcdtg_save(QEMUFile *f, void *opaque)
 597 {
 598     SpitzLCDTG *s = (SpitzLCDTG *)opaque;
 599     qemu_put_be32(f, s->bl_intensity);
 600     qemu_put_be32(f, s->bl_power);
 601 }
 602
 603 static int spitz_lcdtg_load(QEMUFile *f, void *opaque, int version_id)
 604 {
 605     SpitzLCDTG *s = (SpitzLCDTG *)opaque;
 606     s->bl_intensity = qemu_get_be32(f);
 607     s->bl_power = qemu_get_be32(f);
 608     return 0;
 609 }
 610
 611 static void spitz_lcdtg_init(SSISlave *dev)
 612 {
 613     SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
 614
 615     spitz_lcdtg = s;
 616     s->bl_power = 0;
 617     s->bl_intensity = 0x20;
 618
 619     register_savevm("spitz-lcdtg", -1, 1,
 620                     spitz_lcdtg_save, spitz_lcdtg_load, s);
 621 }
 622
 623 /* SSP devices */
 624
 625 #define CORGI_SSP_PORT          2
 626
 627 #define SPITZ_GPIO_LCDCON_CS    53
 628 #define SPITZ_GPIO_ADS7846_CS   14
 629 #define SPITZ_GPIO_MAX1111_CS   20
 630 #define SPITZ_GPIO_TP_INT       11
 631
 632 static DeviceState *max1111;
 633
 634 /* "Demux" the signal based on current chipselect */
 635 typedef struct {
 636     SSISlave ssidev;
 637     SSIBus *bus[3];
 638     int enable[3];
 639 } CorgiSSPState;
 640
 641 static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
 642 {
 643     CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
 644     int i;
 645
 646     for (i = 0; i < 3; i++) {
 647         if (s->enable[i]) {
 648             return ssi_transfer(s->bus[i], value);
 649         }
 650     }
 651     return 0;
 652 }
 653
 654 static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
 655 {
 656     CorgiSSPState *s = (CorgiSSPState *)opaque;
 657     assert(line >= 0 && line < 3);
 658     s->enable[line] = !level;
 659 }
 660
 661 #define MAX1111_BATT_VOLT       1
 662 #define MAX1111_BATT_TEMP       2
 663 #define MAX1111_ACIN_VOLT       3
 664
 665 #define SPITZ_BATTERY_TEMP      0xe0    /* About 2.9V */
 666 #define SPITZ_BATTERY_VOLT      0xd0    /* About 4.0V */
 667 #define SPITZ_CHARGEON_ACIN     0x80    /* About 5.0V */
 668
 669 static void spitz_adc_temp_on(void *opaque, int line, int level)
 670 {
 671     if (!max1111)
 672         return;
 673
 674     if (level)
 675         max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
 676     else
 677         max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
 678 }
 679
 680 static void spitz_ssp_save(QEMUFile *f, void *opaque)
 681 {
 682     CorgiSSPState *s = (CorgiSSPState *)opaque;
 683     int i;
 684
 685     for (i = 0; i < 3; i++) {
 686         qemu_put_be32(f, s->enable[i]);
 687     }
 688 }
 689
 690 static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id)
 691 {
 692     CorgiSSPState *s = (CorgiSSPState *)opaque;
 693     int i;
 694
 695     if (version_id != 1) {
 696         return -EINVAL;
 697     }
 698     for (i = 0; i < 3; i++) {
 699         s->enable[i] = qemu_get_be32(f);
 700     }
 701     return 0;
 702 }
 703
 704 static void corgi_ssp_init(SSISlave *dev)
 705 {
 706     CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
 707
 708     qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
 709     s->bus[0] = ssi_create_bus();
 710     qdev_attach_child_bus(&dev->qdev, "ssi0", s->bus[0]);
 711     s->bus[1] = ssi_create_bus();
 712     qdev_attach_child_bus(&dev->qdev, "ssi1", s->bus[1]);
 713     s->bus[2] = ssi_create_bus();
 714     qdev_attach_child_bus(&dev->qdev, "ssi2", s->bus[2]);
 715
 716     register_savevm("spitz_ssp", -1, 1, spitz_ssp_save, spitz_ssp_load, s);
 717 }
 718
 719 static void spitz_ssp_attach(PXA2xxState *cpu)
 720 {
 721     DeviceState *mux;
 722     DeviceState *dev;
 723     void *bus;
 724
 725     mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
 726
 727     bus = qdev_get_child_bus(mux, "ssi0");
 728     dev = ssi_create_slave(bus, "spitz-lcdtg");
 729
 730     bus = qdev_get_child_bus(mux, "ssi1");
 731     dev = ssi_create_slave(bus, "ads7846");
 732     qdev_connect_gpio_out(dev, 0,
 733                           pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]);
 734
 735     bus = qdev_get_child_bus(mux, "ssi2");
 736     max1111 = ssi_create_slave(bus, "max1111");
 737     max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
 738     max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
 739     max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
 740
 741     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
 742                         qdev_get_gpio_in(mux, 0));
 743     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
 744                         qdev_get_gpio_in(mux, 1));
 745     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
 746                         qdev_get_gpio_in(mux, 2));
 747 }
 748
 749 /* CF Microdrive */
 750
 751 static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
 752 {
 753     PCMCIACardState *md;
 754     int index;
 755     BlockDriverState *bs;
 756
 757     index = drive_get_index(IF_IDE, 0, 0);
 758     if (index == -1)
 759         return;
 760     bs = drives_table[index].bdrv;
 761     if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
 762         md = dscm1xxxx_init(bs);
 763         pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
 764     }
 765 }
 766
 767 /* Wm8750 and Max7310 on I2C */
 768
 769 #define AKITA_MAX_ADDR  0x18
 770 #define SPITZ_WM_ADDRL  0x1b
 771 #define SPITZ_WM_ADDRH  0x1a
 772
 773 #define SPITZ_GPIO_WM   5
 774
 775 #ifdef HAS_AUDIO
 776 static void spitz_wm8750_addr(void *opaque, int line, int level)
 777 {
 778     i2c_slave *wm = (i2c_slave *) opaque;
 779     if (level)
 780         i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
 781     else
 782         i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
 783 }
 784 #endif
 785
 786 static void spitz_i2c_setup(PXA2xxState *cpu)
 787 {
 788     /* Attach the CPU on one end of our I2C bus.  */
 789     i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
 790
 791 #ifdef HAS_AUDIO
 792     DeviceState *wm;
 793
 794     /* Attach a WM8750 to the bus */
 795     wm = i2c_create_slave(bus, "wm8750", 0);
 796
 797     spitz_wm8750_addr(wm, 0, 0);
 798     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
 799                     qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
 800     /* .. and to the sound interface.  */
 801     cpu->i2s->opaque = wm;
 802     cpu->i2s->codec_out = wm8750_dac_dat;
 803     cpu->i2s->codec_in = wm8750_adc_dat;
 804     wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
 805 #endif
 806 }
 807
 808 static void spitz_akita_i2c_setup(PXA2xxState *cpu)
 809 {
 810     /* Attach a Max7310 to Akita I2C bus.  */
 811     i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
 812                      AKITA_MAX_ADDR);
 813 }
 814
 815 /* Other peripherals */
 816
 817 static void spitz_out_switch(void *opaque, int line, int level)
 818 {
 819     switch (line) {
 820     case 0:
 821         zaurus_printf("Charging %s.\n", level ? "off" : "on");
 822         break;
 823     case 1:
 824         zaurus_printf("Discharging %s.\n", level ? "on" : "off");
 825         break;
 826     case 2:
 827         zaurus_printf("Green LED %s.\n", level ? "on" : "off");
 828         break;
 829     case 3:
 830         zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
 831         break;
 832     case 4:
 833         spitz_bl_bit5(opaque, line, level);
 834         break;
 835     case 5:
 836         spitz_bl_power(opaque, line, level);
 837         break;
 838     case 6:
 839         spitz_adc_temp_on(opaque, line, level);
 840         break;
 841     }
 842 }
 843
 844 #define SPITZ_SCP_LED_GREEN             1
 845 #define SPITZ_SCP_JK_B                  2
 846 #define SPITZ_SCP_CHRG_ON               3
 847 #define SPITZ_SCP_MUTE_L                4
 848 #define SPITZ_SCP_MUTE_R                5
 849 #define SPITZ_SCP_CF_POWER              6
 850 #define SPITZ_SCP_LED_ORANGE            7
 851 #define SPITZ_SCP_JK_A                  8
 852 #define SPITZ_SCP_ADC_TEMP_ON           9
 853 #define SPITZ_SCP2_IR_ON                1
 854 #define SPITZ_SCP2_AKIN_PULLUP          2
 855 #define SPITZ_SCP2_BACKLIGHT_CONT       7
 856 #define SPITZ_SCP2_BACKLIGHT_ON         8
 857 #define SPITZ_SCP2_MIC_BIAS             9
 858
 859 static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
 860                 ScoopInfo *scp0, ScoopInfo *scp1)
 861 {
 862     qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
 863
 864     scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
 865     scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]);
 866     scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
 867     scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
 868
 869     if (scp1) {
 870         scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
 871         scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
 872     }
 873
 874     scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
 875 }
 876
 877 #define SPITZ_GPIO_HSYNC                22
 878 #define SPITZ_GPIO_SD_DETECT            9
 879 #define SPITZ_GPIO_SD_WP                81
 880 #define SPITZ_GPIO_ON_RESET             89
 881 #define SPITZ_GPIO_BAT_COVER            90
 882 #define SPITZ_GPIO_CF1_IRQ              105
 883 #define SPITZ_GPIO_CF1_CD               94
 884 #define SPITZ_GPIO_CF2_IRQ              106
 885 #define SPITZ_GPIO_CF2_CD               93
 886
 887 static int spitz_hsync;
 888
 889 static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
 890 {
 891     PXA2xxState *cpu = (PXA2xxState *) opaque;
 892     qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
 893     spitz_hsync ^= 1;
 894 }
 895
 896 static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
 897 {
 898     qemu_irq lcd_hsync;
 899     /*
 900      * Bad hack: We toggle the LCD hsync GPIO on every GPIO status
 901      * read to satisfy broken guests that poll-wait for hsync.
 902      * Simulating a real hsync event would be less practical and
 903      * wouldn't guarantee that a guest ever exits the loop.
 904      */
 905     spitz_hsync = 0;
 906     lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
 907     pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
 908     pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
 909
 910     /* MMC/SD host */
 911     pxa2xx_mmci_handlers(cpu->mmc,
 912                     pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP],
 913                     pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]);
 914
 915     /* Battery lock always closed */
 916     qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]);
 917
 918     /* Handle reset */
 919     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
 920
 921     /* PCMCIA signals: card's IRQ and Card-Detect */
 922     if (slots >= 1)
 923         pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
 924                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ],
 925                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]);
 926     if (slots >= 2)
 927         pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
 928                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ],
 929                         pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]);
 930
 931     /* Initialise the screen rotation related signals */
 932     spitz_gpio_invert[3] = 0;   /* Always open */
 933     if (graphic_rotate) {       /* Tablet mode */
 934         spitz_gpio_invert[4] = 0;
 935     } else {                    /* Portrait mode */
 936         spitz_gpio_invert[4] = 1;
 937     }
 938     qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA],
 939                     spitz_gpio_invert[3]);
 940     qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB],
 941                     spitz_gpio_invert[4]);
 942 }
 943
 944 /* Board init.  */
 945 enum spitz_model_e { spitz, akita, borzoi, terrier };
 946
 947 #define SPITZ_RAM       0x04000000
 948 #define SPITZ_ROM       0x00800000
 949
 950 static struct arm_boot_info spitz_binfo = {
 951     .loader_start = PXA2XX_SDRAM_BASE,
 952     .ram_size = 0x04000000,
 953 };
 954
 955 static void spitz_common_init(ram_addr_t ram_size,
 956                 const char *kernel_filename,
 957                 const char *kernel_cmdline, const char *initrd_filename,
 958                 const char *cpu_model, enum spitz_model_e model, int arm_id)
 959 {
 960     PXA2xxState *cpu;
 961     ScoopInfo *scp0, *scp1 = NULL;
 962
 963     if (!cpu_model)
 964         cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
 965
 966     /* Setup CPU & memory */
 967     cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
 968
 969     sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
 970
 971     cpu_register_physical_memory(0, SPITZ_ROM,
 972                     qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM);
 973
 974     /* Setup peripherals */
 975     spitz_keyboard_register(cpu);
 976
 977     spitz_ssp_attach(cpu);
 978
 979     scp0 = scoop_init(cpu, 0, 0x10800000);
 980     if (model != akita) {
 981             scp1 = scoop_init(cpu, 1, 0x08800040);
 982     }
 983
 984     spitz_scoop_gpio_setup(cpu, scp0, scp1);
 985
 986     spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
 987
 988     spitz_i2c_setup(cpu);
 989
 990     if (model == akita)
 991         spitz_akita_i2c_setup(cpu);
 992
 993     if (model == terrier)
 994         /* A 6.0 GB microdrive is permanently sitting in CF slot 1.  */
 995         spitz_microdrive_attach(cpu, 1);
 996     else if (model != akita)
 997         /* A 4.0 GB microdrive is permanently sitting in CF slot 0.  */
 998         spitz_microdrive_attach(cpu, 0);
 999
1000     /* Setup initial (reset) machine state */
1001     cpu->env->regs[15] = spitz_binfo.loader_start;
1002
1003     spitz_binfo.kernel_filename = kernel_filename;
1004     spitz_binfo.kernel_cmdline = kernel_cmdline;
1005     spitz_binfo.initrd_filename = initrd_filename;
1006     spitz_binfo.board_id = arm_id;
1007     arm_load_kernel(cpu->env, &spitz_binfo);
1008     sl_bootparam_write(SL_PXA_PARAM_BASE);
1009 }
1010
1011 static void spitz_init(ram_addr_t ram_size,
1012                 const char *boot_device,
1013                 const char *kernel_filename, const char *kernel_cmdline,
1014                 const char *initrd_filename, const char *cpu_model)
1015 {
1016     spitz_common_init(ram_size, kernel_filename,
1017                 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
1018 }
1019
1020 static void borzoi_init(ram_addr_t ram_size,
1021                 const char *boot_device,
1022                 const char *kernel_filename, const char *kernel_cmdline,
1023                 const char *initrd_filename, const char *cpu_model)
1024 {
1025     spitz_common_init(ram_size, kernel_filename,
1026                 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
1027 }
1028
1029 static void akita_init(ram_addr_t ram_size,
1030                 const char *boot_device,
1031                 const char *kernel_filename, const char *kernel_cmdline,
1032                 const char *initrd_filename, const char *cpu_model)
1033 {
1034     spitz_common_init(ram_size, kernel_filename,
1035                 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
1036 }
1037
1038 static void terrier_init(ram_addr_t ram_size,
1039                 const char *boot_device,
1040                 const char *kernel_filename, const char *kernel_cmdline,
1041                 const char *initrd_filename, const char *cpu_model)
1042 {
1043     spitz_common_init(ram_size, kernel_filename,
1044                 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
1045 }
1046
1047 QEMUMachine akitapda_machine = {
1048     .name = "akita",
1049     .desc = "Akita PDA (PXA270)",
1050     .init = akita_init,
1051 };
1052
1053 QEMUMachine spitzpda_machine = {
1054     .name = "spitz",
1055     .desc = "Spitz PDA (PXA270)",
1056     .init = spitz_init,
1057 };
1058
1059 QEMUMachine borzoipda_machine = {
1060     .name = "borzoi",
1061     .desc = "Borzoi PDA (PXA270)",
1062     .init = borzoi_init,
1063 };
1064
1065 QEMUMachine terrierpda_machine = {
1066     .name = "terrier",
1067     .desc = "Terrier PDA (PXA270)",
1068     .init = terrier_init,
1069 };
1070
1071 static SSISlaveInfo corgi_ssp_info = {
1072     .init = corgi_ssp_init,
1073     .transfer = corgi_ssp_transfer
1074 };
1075
1076 static SSISlaveInfo spitz_lcdtg_info = {
1077     .init = spitz_lcdtg_init,
1078     .transfer = spitz_lcdtg_transfer
1079 };
1080
1081 static void spitz_register_devices(void)
1082 {
1083     ssi_register_slave("corgi-ssp", sizeof(CorgiSSPState), &corgi_ssp_info);
1084     ssi_register_slave("spitz-lcdtg", sizeof(SpitzLCDTG), &spitz_lcdtg_info);
1085 }
1086
1087 device_init(spitz_register_devices)