target/arm: Convert the VSEL instructions to decodetree
commitb3ff4b87b4ae08120a51fe12592725e1dca8a085
authorPeter Maydell <peter.maydell@linaro.org>
Tue, 11 Jun 2019 15:39:42 +0000 (11 16:39 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 13 Jun 2019 14:14:03 +0000 (13 15:14 +0100)
tree112b1d7ac27b9deefd12cc160c876ccdef7f724d
parent973751fd798d41402d34f9f705c0c6d1633d0cda
target/arm: Convert the VSEL instructions to decodetree

Convert the VSEL instructions to decodetree.
We leave trans_VSEL() in translate.c for now as this allows
the patch to show just the changes from the old handle_vsel().

In the old code the check for "do D16-D31 exist" was hidden in
the VFP_DREG macro, and assumed that VFPv3 always implied that
D16-D31 exist. In the new code we do the correct ID register test.
This gives identical behaviour for most of our CPUs, and fixes
previously incorrect handling for  Cortex-R5F, Cortex-M4 and
Cortex-M33, which all implement VFPv3 or better with only 16
double-precision registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
target/arm/cpu.h
target/arm/translate-vfp.inc.c
target/arm/translate.c
target/arm/vfp-uncond.decode