target-arm: A64: Create Instruction Syndromes for Data Aborts
commitaaa1f954d4cab243e3d5337a72bc6d104e1c4808
authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Mon, 6 Jun 2016 15:59:28 +0000 (6 16:59 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 6 Jun 2016 15:59:28 +0000 (6 16:59 +0100)
tree809f34f601f6dc8bdfc98c7484717a90c71877f4
parent2a5a9abd4bc45e2f4c62c77e07aebe53608c6915
target-arm: A64: Create Instruction Syndromes for Data Aborts

Add support for generating the ISS (Instruction Specific Syndrome) for
Data Abort exceptions taken from AArch64.
These syndromes are used by hypervisors for example to trap and emulate
memory accesses.

We save the decoded data out-of-band with the TBs at translation time.
When exceptions hit, the extra data attached to the TB is used to
recreate the state needed to encode instruction syndromes.
This avoids the need to emit moves with every load/store.

Based on a suggestion from Peter Maydell.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1462464601-10888-2-git-send-email-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm/cpu.h
target-arm/op_helper.c
target-arm/translate-a64.c
target-arm/translate.c
target-arm/translate.h