target/riscv: Consolidate RV32/64 16-bit instructions
commit6baba30ad0b7fbad035a530cc8d0a16c9cc74dc9
authorAlistair Francis <alistair.francis@wdc.com>
Sat, 24 Apr 2021 03:34:25 +0000 (24 13:34 +1000)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 11 May 2021 10:02:07 +0000 (11 20:02 +1000)
treec4aa021e8137ea987db04f0bc692c2178bb3e95f
parentdaf866b606bdb94bb7c7ac6621353d30958521d8
target/riscv: Consolidate RV32/64 16-bit instructions

This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
target/riscv/insn16-32.decode [deleted file]
target/riscv/insn16-64.decode [deleted file]
target/riscv/insn16.decode
target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/meson.build