| commit | 5cb0e7abe1635cb82e0033260dac2b910d142f8c | |
| author | Xu Lu <luxu.kernel@bytedance.com> | |
| Tue, 26 Dec 2023 04:05:00 +0000 (26 12:05 +0800) | ||
| committer | Michael Tokarev <mjt@tls.msk.ru> | |
| Fri, 5 Jan 2024 19:28:54 +0000 (5 22:28 +0300) | ||
| tree | 1a0a066c7df22d8f3f4163141a84849fc8fcf3fc | treesnapshot (tar.gz zip) |
| parent | 0c1eccd368af8805ec0fb11e6cf25d0684d37328 | commitdiff |
target/riscv: Fix mcycle/minstret increment behavior
The mcycle/minstret counter's stop flag is mistakenly updated on a copy
on stack. Thus the counter increments even when the CY/IR bit in the
mcountinhibit register is set. This commit corrects its behavior.
Fixes: 3780e33732f88 (target/riscv: Support mcycle/minstret write operation)
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
The mcycle/minstret counter's stop flag is mistakenly updated on a copy
on stack. Thus the counter increments even when the CY/IR bit in the
mcountinhibit register is set. This commit corrects its behavior.
Fixes: 3780e33732f88 (target/riscv: Support mcycle/minstret write operation)
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| target/riscv/csr.c | diffblobblamehistory |