| commit | 3a4e56015b897a5502ab6a691cd4e20700e779c1 | |
| author | Michael Tokarev <mjt@tls.msk.ru> | |
| Tue, 14 Nov 2023 16:11:33 +0000 (14 19:11 +0300) | ||
| committer | Michael Tokarev <mjt@tls.msk.ru> | |
| Wed, 15 Nov 2023 09:06:05 +0000 (15 12:06 +0300) | ||
| tree | 92657ea61d7ff7c06eb8132b7dd2eb71618ed6c6 | treesnapshot (tar.gz zip) |
| parent | 801faee4dd15ee395fe1c2fb35241c3c7a0b9af5 | commitdiff |
target/riscv/cpu.h: spelling fix: separatly
Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support."
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support."
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| target/riscv/cpu.h | diffblobblamehistory |