| commit | 0707b34dcb87b5446208362cd6c8ccff75f2e01c | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Fri, 20 Jan 2017 11:15:07 +0000 (20 11:15 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 20 Jan 2017 11:15:07 +0000 (20 11:15 +0000) | ||
| tree | 7f3cd275e7a6642070e1ddf4c862ef968f731506 | treesnapshot (tar.gz zip) |
| parent | f248a9dbd0cfb9f577f7cb6f799497c51690054a | commitdiff |
aspeed/smc: autostrap CE0/1 configuration
On the AST2500 SoC, the FMC controller flash type is fixed to SPI for
CE0 and CE1 and 4BYTE mode is autodetected for CE0.
On the AST2400 SoC, the FMC controller flash type and 4BYTE mode are
strapped with register SCU70. We use the default settings from the
palmetto-bmc machine for now.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1483979087-32663-5-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
On the AST2500 SoC, the FMC controller flash type is fixed to SPI for
CE0 and CE1 and 4BYTE mode is autodetected for CE0.
On the AST2400 SoC, the FMC controller flash type and 4BYTE mode are
strapped with register SCU70. We use the default settings from the
palmetto-bmc machine for now.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1483979087-32663-5-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/ssi/aspeed_smc.c | diffblobblamehistory |