4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/translator.h"
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
33 #include "trace-tcg.h"
36 //#define DEBUG_DISPATCH 1
38 #define DEFO32(name, offset) static TCGv QREG_##name;
39 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
44 static TCGv_i32 cpu_halted
;
45 static TCGv_i32 cpu_exception_index
;
47 static char cpu_reg_names
[2 * 8 * 3 + 5 * 4];
48 static TCGv cpu_dregs
[8];
49 static TCGv cpu_aregs
[8];
50 static TCGv_i64 cpu_macc
[4];
52 #define REG(insn, pos) (((insn) >> (pos)) & 7)
53 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
54 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
55 #define MACREG(acc) cpu_macc[acc]
56 #define QREG_SP get_areg(s, 7)
58 static TCGv NULL_QREG
;
59 #define IS_NULL_QREG(t) (t == NULL_QREG)
60 /* Used to distinguish stores from bad addressing modes. */
61 static TCGv store_dummy
;
63 #include "exec/gen-icount.h"
65 void m68k_tcg_init(void)
70 #define DEFO32(name, offset) \
71 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
72 offsetof(CPUM68KState, offset), #name);
73 #define DEFO64(name, offset) \
74 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
80 cpu_halted
= tcg_global_mem_new_i32(cpu_env
,
81 -offsetof(M68kCPU
, env
) +
82 offsetof(CPUState
, halted
), "HALTED");
83 cpu_exception_index
= tcg_global_mem_new_i32(cpu_env
,
84 -offsetof(M68kCPU
, env
) +
85 offsetof(CPUState
, exception_index
),
89 for (i
= 0; i
< 8; i
++) {
91 cpu_dregs
[i
] = tcg_global_mem_new(cpu_env
,
92 offsetof(CPUM68KState
, dregs
[i
]), p
);
95 cpu_aregs
[i
] = tcg_global_mem_new(cpu_env
,
96 offsetof(CPUM68KState
, aregs
[i
]), p
);
99 for (i
= 0; i
< 4; i
++) {
100 sprintf(p
, "ACC%d", i
);
101 cpu_macc
[i
] = tcg_global_mem_new_i64(cpu_env
,
102 offsetof(CPUM68KState
, macc
[i
]), p
);
106 NULL_QREG
= tcg_global_mem_new(cpu_env
, -4, "NULL");
107 store_dummy
= tcg_global_mem_new(cpu_env
, -8, "NULL");
110 /* internal defines */
111 typedef struct DisasContext
{
113 target_ulong insn_pc
; /* Start of the current instruction. */
116 CCOp cc_op
; /* Current CC operation */
119 struct TranslationBlock
*tb
;
120 int singlestep_enabled
;
127 static TCGv
get_areg(DisasContext
*s
, unsigned regno
)
129 if (s
->writeback_mask
& (1 << regno
)) {
130 return s
->writeback
[regno
];
132 return cpu_aregs
[regno
];
136 static void delay_set_areg(DisasContext
*s
, unsigned regno
,
137 TCGv val
, bool give_temp
)
139 if (s
->writeback_mask
& (1 << regno
)) {
141 tcg_temp_free(s
->writeback
[regno
]);
142 s
->writeback
[regno
] = val
;
144 tcg_gen_mov_i32(s
->writeback
[regno
], val
);
147 s
->writeback_mask
|= 1 << regno
;
149 s
->writeback
[regno
] = val
;
151 TCGv tmp
= tcg_temp_new();
152 s
->writeback
[regno
] = tmp
;
153 tcg_gen_mov_i32(tmp
, val
);
158 static void do_writebacks(DisasContext
*s
)
160 unsigned mask
= s
->writeback_mask
;
162 s
->writeback_mask
= 0;
164 unsigned regno
= ctz32(mask
);
165 tcg_gen_mov_i32(cpu_aregs
[regno
], s
->writeback
[regno
]);
166 tcg_temp_free(s
->writeback
[regno
]);
172 /* is_jmp field values */
173 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
174 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
175 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
176 #define DISAS_JUMP_NEXT DISAS_TARGET_3
178 #if defined(CONFIG_USER_ONLY)
181 #define IS_USER(s) s->user
184 typedef void (*disas_proc
)(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
);
186 #ifdef DEBUG_DISPATCH
187 #define DISAS_INSN(name) \
188 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
190 static void disas_##name(CPUM68KState *env, DisasContext *s, \
193 qemu_log("Dispatch " #name "\n"); \
194 real_disas_##name(env, s, insn); \
196 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
199 #define DISAS_INSN(name) \
200 static void disas_##name(CPUM68KState *env, DisasContext *s, \
204 static const uint8_t cc_op_live
[CC_OP_NB
] = {
205 [CC_OP_DYNAMIC
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
206 [CC_OP_FLAGS
] = CCF_C
| CCF_V
| CCF_Z
| CCF_N
| CCF_X
,
207 [CC_OP_ADDB
... CC_OP_ADDL
] = CCF_X
| CCF_N
| CCF_V
,
208 [CC_OP_SUBB
... CC_OP_SUBL
] = CCF_X
| CCF_N
| CCF_V
,
209 [CC_OP_CMPB
... CC_OP_CMPL
] = CCF_X
| CCF_N
| CCF_V
,
210 [CC_OP_LOGIC
] = CCF_X
| CCF_N
213 static void set_cc_op(DisasContext
*s
, CCOp op
)
215 CCOp old_op
= s
->cc_op
;
224 /* Discard CC computation that will no longer be used.
225 Note that X and N are never dead. */
226 dead
= cc_op_live
[old_op
] & ~cc_op_live
[op
];
228 tcg_gen_discard_i32(QREG_CC_C
);
231 tcg_gen_discard_i32(QREG_CC_Z
);
234 tcg_gen_discard_i32(QREG_CC_V
);
238 /* Update the CPU env CC_OP state. */
239 static void update_cc_op(DisasContext
*s
)
241 if (!s
->cc_op_synced
) {
243 tcg_gen_movi_i32(QREG_CC_OP
, s
->cc_op
);
247 /* Generate a jump to an immediate address. */
248 static void gen_jmp_im(DisasContext
*s
, uint32_t dest
)
251 tcg_gen_movi_i32(QREG_PC
, dest
);
252 s
->is_jmp
= DISAS_JUMP
;
255 /* Generate a jump to the address in qreg DEST. */
256 static void gen_jmp(DisasContext
*s
, TCGv dest
)
259 tcg_gen_mov_i32(QREG_PC
, dest
);
260 s
->is_jmp
= DISAS_JUMP
;
263 static void gen_raise_exception(int nr
)
265 TCGv_i32 tmp
= tcg_const_i32(nr
);
267 gen_helper_raise_exception(cpu_env
, tmp
);
268 tcg_temp_free_i32(tmp
);
271 static void gen_exception(DisasContext
*s
, uint32_t where
, int nr
)
273 gen_jmp_im(s
, where
);
274 gen_raise_exception(nr
);
277 static inline void gen_addr_fault(DisasContext
*s
)
279 gen_exception(s
, s
->insn_pc
, EXCP_ADDRESS
);
282 /* Generate a load from the specified address. Narrow values are
283 sign extended to full register width. */
284 static inline TCGv
gen_load(DisasContext
* s
, int opsize
, TCGv addr
, int sign
)
287 int index
= IS_USER(s
);
288 tmp
= tcg_temp_new_i32();
292 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
294 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
298 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
300 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
303 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
306 g_assert_not_reached();
311 /* Generate a store. */
312 static inline void gen_store(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
)
314 int index
= IS_USER(s
);
317 tcg_gen_qemu_st8(val
, addr
, index
);
320 tcg_gen_qemu_st16(val
, addr
, index
);
323 tcg_gen_qemu_st32(val
, addr
, index
);
326 g_assert_not_reached();
336 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
337 otherwise generate a store. */
338 static TCGv
gen_ldst(DisasContext
*s
, int opsize
, TCGv addr
, TCGv val
,
341 if (what
== EA_STORE
) {
342 gen_store(s
, opsize
, addr
, val
);
345 return gen_load(s
, opsize
, addr
, what
== EA_LOADS
);
349 /* Read a 16-bit immediate constant */
350 static inline uint16_t read_im16(CPUM68KState
*env
, DisasContext
*s
)
353 im
= cpu_lduw_code(env
, s
->pc
);
358 /* Read an 8-bit immediate constant */
359 static inline uint8_t read_im8(CPUM68KState
*env
, DisasContext
*s
)
361 return read_im16(env
, s
);
364 /* Read a 32-bit immediate constant. */
365 static inline uint32_t read_im32(CPUM68KState
*env
, DisasContext
*s
)
368 im
= read_im16(env
, s
) << 16;
369 im
|= 0xffff & read_im16(env
, s
);
373 /* Read a 64-bit immediate constant. */
374 static inline uint64_t read_im64(CPUM68KState
*env
, DisasContext
*s
)
377 im
= (uint64_t)read_im32(env
, s
) << 32;
378 im
|= (uint64_t)read_im32(env
, s
);
382 /* Calculate and address index. */
383 static TCGv
gen_addr_index(DisasContext
*s
, uint16_t ext
, TCGv tmp
)
388 add
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(ext
, 12);
389 if ((ext
& 0x800) == 0) {
390 tcg_gen_ext16s_i32(tmp
, add
);
393 scale
= (ext
>> 9) & 3;
395 tcg_gen_shli_i32(tmp
, add
, scale
);
401 /* Handle a base + index + displacement effective addresss.
402 A NULL_QREG base means pc-relative. */
403 static TCGv
gen_lea_indexed(CPUM68KState
*env
, DisasContext
*s
, TCGv base
)
412 ext
= read_im16(env
, s
);
414 if ((ext
& 0x800) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_WORD_INDEX
))
417 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
) &&
418 !m68k_feature(s
->env
, M68K_FEATURE_SCALED_INDEX
)) {
423 /* full extension word format */
424 if (!m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
))
427 if ((ext
& 0x30) > 0x10) {
428 /* base displacement */
429 if ((ext
& 0x30) == 0x20) {
430 bd
= (int16_t)read_im16(env
, s
);
432 bd
= read_im32(env
, s
);
437 tmp
= tcg_temp_new();
438 if ((ext
& 0x44) == 0) {
440 add
= gen_addr_index(s
, ext
, tmp
);
444 if ((ext
& 0x80) == 0) {
445 /* base not suppressed */
446 if (IS_NULL_QREG(base
)) {
447 base
= tcg_const_i32(offset
+ bd
);
450 if (!IS_NULL_QREG(add
)) {
451 tcg_gen_add_i32(tmp
, add
, base
);
457 if (!IS_NULL_QREG(add
)) {
459 tcg_gen_addi_i32(tmp
, add
, bd
);
463 add
= tcg_const_i32(bd
);
465 if ((ext
& 3) != 0) {
466 /* memory indirect */
467 base
= gen_load(s
, OS_LONG
, add
, 0);
468 if ((ext
& 0x44) == 4) {
469 add
= gen_addr_index(s
, ext
, tmp
);
470 tcg_gen_add_i32(tmp
, add
, base
);
476 /* outer displacement */
477 if ((ext
& 3) == 2) {
478 od
= (int16_t)read_im16(env
, s
);
480 od
= read_im32(env
, s
);
486 tcg_gen_addi_i32(tmp
, add
, od
);
491 /* brief extension word format */
492 tmp
= tcg_temp_new();
493 add
= gen_addr_index(s
, ext
, tmp
);
494 if (!IS_NULL_QREG(base
)) {
495 tcg_gen_add_i32(tmp
, add
, base
);
497 tcg_gen_addi_i32(tmp
, tmp
, (int8_t)ext
);
499 tcg_gen_addi_i32(tmp
, add
, offset
+ (int8_t)ext
);
506 /* Sign or zero extend a value. */
508 static inline void gen_ext(TCGv res
, TCGv val
, int opsize
, int sign
)
513 tcg_gen_ext8s_i32(res
, val
);
515 tcg_gen_ext8u_i32(res
, val
);
520 tcg_gen_ext16s_i32(res
, val
);
522 tcg_gen_ext16u_i32(res
, val
);
526 tcg_gen_mov_i32(res
, val
);
529 g_assert_not_reached();
533 /* Evaluate all the CC flags. */
535 static void gen_flush_flags(DisasContext
*s
)
546 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
547 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
548 /* Compute signed overflow for addition. */
551 tcg_gen_sub_i32(t0
, QREG_CC_N
, QREG_CC_V
);
552 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_ADDB
, 1);
553 tcg_gen_xor_i32(t1
, QREG_CC_N
, QREG_CC_V
);
554 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
556 tcg_gen_andc_i32(QREG_CC_V
, t1
, QREG_CC_V
);
563 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
564 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
565 /* Compute signed overflow for subtraction. */
568 tcg_gen_add_i32(t0
, QREG_CC_N
, QREG_CC_V
);
569 gen_ext(t0
, t0
, s
->cc_op
- CC_OP_SUBB
, 1);
570 tcg_gen_xor_i32(t1
, QREG_CC_N
, t0
);
571 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, t0
);
573 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t1
);
580 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_C
, QREG_CC_N
, QREG_CC_V
);
581 tcg_gen_sub_i32(QREG_CC_Z
, QREG_CC_N
, QREG_CC_V
);
582 gen_ext(QREG_CC_Z
, QREG_CC_Z
, s
->cc_op
- CC_OP_CMPB
, 1);
583 /* Compute signed overflow for subtraction. */
585 tcg_gen_xor_i32(t0
, QREG_CC_Z
, QREG_CC_N
);
586 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_V
, QREG_CC_N
);
587 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, t0
);
589 tcg_gen_mov_i32(QREG_CC_N
, QREG_CC_Z
);
593 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
594 tcg_gen_movi_i32(QREG_CC_C
, 0);
595 tcg_gen_movi_i32(QREG_CC_V
, 0);
599 gen_helper_flush_flags(cpu_env
, QREG_CC_OP
);
604 t0
= tcg_const_i32(s
->cc_op
);
605 gen_helper_flush_flags(cpu_env
, t0
);
611 /* Note that flush_flags also assigned to env->cc_op. */
612 s
->cc_op
= CC_OP_FLAGS
;
615 static inline TCGv
gen_extend(TCGv val
, int opsize
, int sign
)
619 if (opsize
== OS_LONG
) {
622 tmp
= tcg_temp_new();
623 gen_ext(tmp
, val
, opsize
, sign
);
629 static void gen_logic_cc(DisasContext
*s
, TCGv val
, int opsize
)
631 gen_ext(QREG_CC_N
, val
, opsize
, 1);
632 set_cc_op(s
, CC_OP_LOGIC
);
635 static void gen_update_cc_cmp(DisasContext
*s
, TCGv dest
, TCGv src
, int opsize
)
637 tcg_gen_mov_i32(QREG_CC_N
, dest
);
638 tcg_gen_mov_i32(QREG_CC_V
, src
);
639 set_cc_op(s
, CC_OP_CMPB
+ opsize
);
642 static void gen_update_cc_add(TCGv dest
, TCGv src
, int opsize
)
644 gen_ext(QREG_CC_N
, dest
, opsize
, 1);
645 tcg_gen_mov_i32(QREG_CC_V
, src
);
648 static inline int opsize_bytes(int opsize
)
651 case OS_BYTE
: return 1;
652 case OS_WORD
: return 2;
653 case OS_LONG
: return 4;
654 case OS_SINGLE
: return 4;
655 case OS_DOUBLE
: return 8;
656 case OS_EXTENDED
: return 12;
657 case OS_PACKED
: return 12;
659 g_assert_not_reached();
663 static inline int insn_opsize(int insn
)
665 switch ((insn
>> 6) & 3) {
666 case 0: return OS_BYTE
;
667 case 1: return OS_WORD
;
668 case 2: return OS_LONG
;
670 g_assert_not_reached();
672 /* Should never happen. */
676 static inline int ext_opsize(int ext
, int pos
)
678 switch ((ext
>> pos
) & 7) {
679 case 0: return OS_LONG
;
680 case 1: return OS_SINGLE
;
681 case 2: return OS_EXTENDED
;
682 case 3: return OS_PACKED
;
683 case 4: return OS_WORD
;
684 case 5: return OS_DOUBLE
;
685 case 6: return OS_BYTE
;
687 g_assert_not_reached();
691 /* Assign value to a register. If the width is less than the register width
692 only the low part of the register is set. */
693 static void gen_partset_reg(int opsize
, TCGv reg
, TCGv val
)
698 tcg_gen_andi_i32(reg
, reg
, 0xffffff00);
699 tmp
= tcg_temp_new();
700 tcg_gen_ext8u_i32(tmp
, val
);
701 tcg_gen_or_i32(reg
, reg
, tmp
);
705 tcg_gen_andi_i32(reg
, reg
, 0xffff0000);
706 tmp
= tcg_temp_new();
707 tcg_gen_ext16u_i32(tmp
, val
);
708 tcg_gen_or_i32(reg
, reg
, tmp
);
713 tcg_gen_mov_i32(reg
, val
);
716 g_assert_not_reached();
720 /* Generate code for an "effective address". Does not adjust the base
721 register for autoincrement addressing modes. */
722 static TCGv
gen_lea_mode(CPUM68KState
*env
, DisasContext
*s
,
723 int mode
, int reg0
, int opsize
)
731 case 0: /* Data register direct. */
732 case 1: /* Address register direct. */
734 case 3: /* Indirect postincrement. */
735 if (opsize
== OS_UNSIZED
) {
739 case 2: /* Indirect register */
740 return get_areg(s
, reg0
);
741 case 4: /* Indirect predecrememnt. */
742 if (opsize
== OS_UNSIZED
) {
745 reg
= get_areg(s
, reg0
);
746 tmp
= tcg_temp_new();
747 if (reg0
== 7 && opsize
== OS_BYTE
&&
748 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
749 tcg_gen_subi_i32(tmp
, reg
, 2);
751 tcg_gen_subi_i32(tmp
, reg
, opsize_bytes(opsize
));
754 case 5: /* Indirect displacement. */
755 reg
= get_areg(s
, reg0
);
756 tmp
= tcg_temp_new();
757 ext
= read_im16(env
, s
);
758 tcg_gen_addi_i32(tmp
, reg
, (int16_t)ext
);
760 case 6: /* Indirect index + displacement. */
761 reg
= get_areg(s
, reg0
);
762 return gen_lea_indexed(env
, s
, reg
);
765 case 0: /* Absolute short. */
766 offset
= (int16_t)read_im16(env
, s
);
767 return tcg_const_i32(offset
);
768 case 1: /* Absolute long. */
769 offset
= read_im32(env
, s
);
770 return tcg_const_i32(offset
);
771 case 2: /* pc displacement */
773 offset
+= (int16_t)read_im16(env
, s
);
774 return tcg_const_i32(offset
);
775 case 3: /* pc index+displacement. */
776 return gen_lea_indexed(env
, s
, NULL_QREG
);
777 case 4: /* Immediate. */
782 /* Should never happen. */
786 static TCGv
gen_lea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
789 int mode
= extract32(insn
, 3, 3);
790 int reg0
= REG(insn
, 0);
791 return gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
794 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
795 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
796 ADDRP is non-null for readwrite operands. */
797 static TCGv
gen_ea_mode(CPUM68KState
*env
, DisasContext
*s
, int mode
, int reg0
,
798 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
800 TCGv reg
, tmp
, result
;
804 case 0: /* Data register direct. */
805 reg
= cpu_dregs
[reg0
];
806 if (what
== EA_STORE
) {
807 gen_partset_reg(opsize
, reg
, val
);
810 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
812 case 1: /* Address register direct. */
813 reg
= get_areg(s
, reg0
);
814 if (what
== EA_STORE
) {
815 tcg_gen_mov_i32(reg
, val
);
818 return gen_extend(reg
, opsize
, what
== EA_LOADS
);
820 case 2: /* Indirect register */
821 reg
= get_areg(s
, reg0
);
822 return gen_ldst(s
, opsize
, reg
, val
, what
);
823 case 3: /* Indirect postincrement. */
824 reg
= get_areg(s
, reg0
);
825 result
= gen_ldst(s
, opsize
, reg
, val
, what
);
826 if (what
== EA_STORE
|| !addrp
) {
827 TCGv tmp
= tcg_temp_new();
828 if (reg0
== 7 && opsize
== OS_BYTE
&&
829 m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
830 tcg_gen_addi_i32(tmp
, reg
, 2);
832 tcg_gen_addi_i32(tmp
, reg
, opsize_bytes(opsize
));
834 delay_set_areg(s
, reg0
, tmp
, true);
837 case 4: /* Indirect predecrememnt. */
838 if (addrp
&& what
== EA_STORE
) {
841 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
842 if (IS_NULL_QREG(tmp
)) {
849 result
= gen_ldst(s
, opsize
, tmp
, val
, what
);
850 if (what
== EA_STORE
|| !addrp
) {
851 delay_set_areg(s
, reg0
, tmp
, false);
854 case 5: /* Indirect displacement. */
855 case 6: /* Indirect index + displacement. */
857 if (addrp
&& what
== EA_STORE
) {
860 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
861 if (IS_NULL_QREG(tmp
)) {
868 return gen_ldst(s
, opsize
, tmp
, val
, what
);
871 case 0: /* Absolute short. */
872 case 1: /* Absolute long. */
873 case 2: /* pc displacement */
874 case 3: /* pc index+displacement. */
876 case 4: /* Immediate. */
877 /* Sign extend values for consistency. */
880 if (what
== EA_LOADS
) {
881 offset
= (int8_t)read_im8(env
, s
);
883 offset
= read_im8(env
, s
);
887 if (what
== EA_LOADS
) {
888 offset
= (int16_t)read_im16(env
, s
);
890 offset
= read_im16(env
, s
);
894 offset
= read_im32(env
, s
);
897 g_assert_not_reached();
899 return tcg_const_i32(offset
);
904 /* Should never happen. */
908 static TCGv
gen_ea(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
909 int opsize
, TCGv val
, TCGv
*addrp
, ea_what what
)
911 int mode
= extract32(insn
, 3, 3);
912 int reg0
= REG(insn
, 0);
913 return gen_ea_mode(env
, s
, mode
, reg0
, opsize
, val
, addrp
, what
);
916 static TCGv_ptr
gen_fp_ptr(int freg
)
918 TCGv_ptr fp
= tcg_temp_new_ptr();
919 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fregs
[freg
]));
923 static TCGv_ptr
gen_fp_result_ptr(void)
925 TCGv_ptr fp
= tcg_temp_new_ptr();
926 tcg_gen_addi_ptr(fp
, cpu_env
, offsetof(CPUM68KState
, fp_result
));
930 static void gen_fp_move(TCGv_ptr dest
, TCGv_ptr src
)
935 t32
= tcg_temp_new();
936 tcg_gen_ld16u_i32(t32
, src
, offsetof(FPReg
, l
.upper
));
937 tcg_gen_st16_i32(t32
, dest
, offsetof(FPReg
, l
.upper
));
940 t64
= tcg_temp_new_i64();
941 tcg_gen_ld_i64(t64
, src
, offsetof(FPReg
, l
.lower
));
942 tcg_gen_st_i64(t64
, dest
, offsetof(FPReg
, l
.lower
));
943 tcg_temp_free_i64(t64
);
946 static void gen_load_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
)
950 int index
= IS_USER(s
);
952 t64
= tcg_temp_new_i64();
953 tmp
= tcg_temp_new();
956 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
957 gen_helper_exts32(cpu_env
, fp
, tmp
);
960 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
961 gen_helper_exts32(cpu_env
, fp
, tmp
);
964 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
965 gen_helper_exts32(cpu_env
, fp
, tmp
);
968 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
969 gen_helper_extf32(cpu_env
, fp
, tmp
);
972 tcg_gen_qemu_ld64(t64
, addr
, index
);
973 gen_helper_extf64(cpu_env
, fp
, t64
);
974 tcg_temp_free_i64(t64
);
977 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
978 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
981 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
982 tcg_gen_shri_i32(tmp
, tmp
, 16);
983 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
984 tcg_gen_addi_i32(tmp
, addr
, 4);
985 tcg_gen_qemu_ld64(t64
, tmp
, index
);
986 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
989 /* unimplemented data type on 68040/ColdFire
990 * FIXME if needed for another FPU
992 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
995 g_assert_not_reached();
998 tcg_temp_free_i64(t64
);
1001 static void gen_store_fp(DisasContext
*s
, int opsize
, TCGv addr
, TCGv_ptr fp
)
1005 int index
= IS_USER(s
);
1007 t64
= tcg_temp_new_i64();
1008 tmp
= tcg_temp_new();
1011 gen_helper_reds32(tmp
, cpu_env
, fp
);
1012 tcg_gen_qemu_st8(tmp
, addr
, index
);
1015 gen_helper_reds32(tmp
, cpu_env
, fp
);
1016 tcg_gen_qemu_st16(tmp
, addr
, index
);
1019 gen_helper_reds32(tmp
, cpu_env
, fp
);
1020 tcg_gen_qemu_st32(tmp
, addr
, index
);
1023 gen_helper_redf32(tmp
, cpu_env
, fp
);
1024 tcg_gen_qemu_st32(tmp
, addr
, index
);
1027 gen_helper_redf64(t64
, cpu_env
, fp
);
1028 tcg_gen_qemu_st64(t64
, addr
, index
);
1031 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1032 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1035 tcg_gen_ld16u_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1036 tcg_gen_shli_i32(tmp
, tmp
, 16);
1037 tcg_gen_qemu_st32(tmp
, addr
, index
);
1038 tcg_gen_addi_i32(tmp
, addr
, 4);
1039 tcg_gen_ld_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1040 tcg_gen_qemu_st64(t64
, tmp
, index
);
1043 /* unimplemented data type on 68040/ColdFire
1044 * FIXME if needed for another FPU
1046 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1049 g_assert_not_reached();
1052 tcg_temp_free_i64(t64
);
1055 static void gen_ldst_fp(DisasContext
*s
, int opsize
, TCGv addr
,
1056 TCGv_ptr fp
, ea_what what
)
1058 if (what
== EA_STORE
) {
1059 gen_store_fp(s
, opsize
, addr
, fp
);
1061 gen_load_fp(s
, opsize
, addr
, fp
);
1065 static int gen_ea_mode_fp(CPUM68KState
*env
, DisasContext
*s
, int mode
,
1066 int reg0
, int opsize
, TCGv_ptr fp
, ea_what what
)
1068 TCGv reg
, addr
, tmp
;
1072 case 0: /* Data register direct. */
1073 reg
= cpu_dregs
[reg0
];
1074 if (what
== EA_STORE
) {
1079 gen_helper_reds32(reg
, cpu_env
, fp
);
1082 gen_helper_redf32(reg
, cpu_env
, fp
);
1085 g_assert_not_reached();
1088 tmp
= tcg_temp_new();
1091 tcg_gen_ext8s_i32(tmp
, reg
);
1092 gen_helper_exts32(cpu_env
, fp
, tmp
);
1095 tcg_gen_ext16s_i32(tmp
, reg
);
1096 gen_helper_exts32(cpu_env
, fp
, tmp
);
1099 gen_helper_exts32(cpu_env
, fp
, reg
);
1102 gen_helper_extf32(cpu_env
, fp
, reg
);
1105 g_assert_not_reached();
1110 case 1: /* Address register direct. */
1112 case 2: /* Indirect register */
1113 addr
= get_areg(s
, reg0
);
1114 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1116 case 3: /* Indirect postincrement. */
1117 addr
= cpu_aregs
[reg0
];
1118 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1119 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(opsize
));
1121 case 4: /* Indirect predecrememnt. */
1122 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1123 if (IS_NULL_QREG(addr
)) {
1126 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1127 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
1129 case 5: /* Indirect displacement. */
1130 case 6: /* Indirect index + displacement. */
1132 addr
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
1133 if (IS_NULL_QREG(addr
)) {
1136 gen_ldst_fp(s
, opsize
, addr
, fp
, what
);
1140 case 0: /* Absolute short. */
1141 case 1: /* Absolute long. */
1142 case 2: /* pc displacement */
1143 case 3: /* pc index+displacement. */
1145 case 4: /* Immediate. */
1146 if (what
== EA_STORE
) {
1151 tmp
= tcg_const_i32((int8_t)read_im8(env
, s
));
1152 gen_helper_exts32(cpu_env
, fp
, tmp
);
1156 tmp
= tcg_const_i32((int16_t)read_im16(env
, s
));
1157 gen_helper_exts32(cpu_env
, fp
, tmp
);
1161 tmp
= tcg_const_i32(read_im32(env
, s
));
1162 gen_helper_exts32(cpu_env
, fp
, tmp
);
1166 tmp
= tcg_const_i32(read_im32(env
, s
));
1167 gen_helper_extf32(cpu_env
, fp
, tmp
);
1171 t64
= tcg_const_i64(read_im64(env
, s
));
1172 gen_helper_extf64(cpu_env
, fp
, t64
);
1173 tcg_temp_free_i64(t64
);
1176 if (m68k_feature(s
->env
, M68K_FEATURE_CF_FPU
)) {
1177 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1180 tmp
= tcg_const_i32(read_im32(env
, s
) >> 16);
1181 tcg_gen_st16_i32(tmp
, fp
, offsetof(FPReg
, l
.upper
));
1183 t64
= tcg_const_i64(read_im64(env
, s
));
1184 tcg_gen_st_i64(t64
, fp
, offsetof(FPReg
, l
.lower
));
1185 tcg_temp_free_i64(t64
);
1188 /* unimplemented data type on 68040/ColdFire
1189 * FIXME if needed for another FPU
1191 gen_exception(s
, s
->insn_pc
, EXCP_FP_UNIMP
);
1194 g_assert_not_reached();
1204 static int gen_ea_fp(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
1205 int opsize
, TCGv_ptr fp
, ea_what what
)
1207 int mode
= extract32(insn
, 3, 3);
1208 int reg0
= REG(insn
, 0);
1209 return gen_ea_mode_fp(env
, s
, mode
, reg0
, opsize
, fp
, what
);
1220 static void gen_cc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
1226 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1227 if (op
== CC_OP_CMPB
|| op
== CC_OP_CMPW
|| op
== CC_OP_CMPL
) {
1234 tcond
= TCG_COND_LEU
;
1238 tcond
= TCG_COND_LTU
;
1242 tcond
= TCG_COND_EQ
;
1247 c
->v2
= tcg_const_i32(0);
1248 c
->v1
= tmp
= tcg_temp_new();
1249 tcg_gen_sub_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1250 gen_ext(tmp
, tmp
, op
- CC_OP_CMPB
, 1);
1254 tcond
= TCG_COND_LT
;
1258 tcond
= TCG_COND_LE
;
1265 c
->v2
= tcg_const_i32(0);
1271 tcond
= TCG_COND_NEVER
;
1273 case 14: /* GT (!(Z || (N ^ V))) */
1274 case 15: /* LE (Z || (N ^ V)) */
1275 /* Logic operations clear V, which simplifies LE to (Z || N),
1276 and since Z and N are co-located, this becomes a normal
1278 if (op
== CC_OP_LOGIC
) {
1280 tcond
= TCG_COND_LE
;
1284 case 12: /* GE (!(N ^ V)) */
1285 case 13: /* LT (N ^ V) */
1286 /* Logic operations clear V, which simplifies this to N. */
1287 if (op
!= CC_OP_LOGIC
) {
1291 case 10: /* PL (!N) */
1292 case 11: /* MI (N) */
1293 /* Several cases represent N normally. */
1294 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1295 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1296 op
== CC_OP_LOGIC
) {
1298 tcond
= TCG_COND_LT
;
1302 case 6: /* NE (!Z) */
1303 case 7: /* EQ (Z) */
1304 /* Some cases fold Z into N. */
1305 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1306 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
||
1307 op
== CC_OP_LOGIC
) {
1308 tcond
= TCG_COND_EQ
;
1313 case 4: /* CC (!C) */
1314 case 5: /* CS (C) */
1315 /* Some cases fold C into X. */
1316 if (op
== CC_OP_ADDB
|| op
== CC_OP_ADDW
|| op
== CC_OP_ADDL
||
1317 op
== CC_OP_SUBB
|| op
== CC_OP_SUBW
|| op
== CC_OP_SUBL
) {
1318 tcond
= TCG_COND_NE
;
1323 case 8: /* VC (!V) */
1324 case 9: /* VS (V) */
1325 /* Logic operations clear V and C. */
1326 if (op
== CC_OP_LOGIC
) {
1327 tcond
= TCG_COND_NEVER
;
1334 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1341 /* Invalid, or handled above. */
1343 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1344 case 3: /* LS (C || Z) */
1345 c
->v1
= tmp
= tcg_temp_new();
1347 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1348 tcg_gen_or_i32(tmp
, tmp
, QREG_CC_C
);
1349 tcond
= TCG_COND_NE
;
1351 case 4: /* CC (!C) */
1352 case 5: /* CS (C) */
1354 tcond
= TCG_COND_NE
;
1356 case 6: /* NE (!Z) */
1357 case 7: /* EQ (Z) */
1359 tcond
= TCG_COND_EQ
;
1361 case 8: /* VC (!V) */
1362 case 9: /* VS (V) */
1364 tcond
= TCG_COND_LT
;
1366 case 10: /* PL (!N) */
1367 case 11: /* MI (N) */
1369 tcond
= TCG_COND_LT
;
1371 case 12: /* GE (!(N ^ V)) */
1372 case 13: /* LT (N ^ V) */
1373 c
->v1
= tmp
= tcg_temp_new();
1375 tcg_gen_xor_i32(tmp
, QREG_CC_N
, QREG_CC_V
);
1376 tcond
= TCG_COND_LT
;
1378 case 14: /* GT (!(Z || (N ^ V))) */
1379 case 15: /* LE (Z || (N ^ V)) */
1380 c
->v1
= tmp
= tcg_temp_new();
1382 tcg_gen_setcond_i32(TCG_COND_EQ
, tmp
, QREG_CC_Z
, c
->v2
);
1383 tcg_gen_neg_i32(tmp
, tmp
);
1384 tmp2
= tcg_temp_new();
1385 tcg_gen_xor_i32(tmp2
, QREG_CC_N
, QREG_CC_V
);
1386 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1387 tcg_temp_free(tmp2
);
1388 tcond
= TCG_COND_LT
;
1393 if ((cond
& 1) == 0) {
1394 tcond
= tcg_invert_cond(tcond
);
1399 static void free_cond(DisasCompare
*c
)
1402 tcg_temp_free(c
->v1
);
1405 tcg_temp_free(c
->v2
);
1409 static void gen_jmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
1413 gen_cc_cond(&c
, s
, cond
);
1415 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
1419 /* Force a TB lookup after an instruction that changes the CPU state. */
1420 static void gen_lookup_tb(DisasContext
*s
)
1423 tcg_gen_movi_i32(QREG_PC
, s
->pc
);
1424 s
->is_jmp
= DISAS_UPDATE
;
1427 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1428 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1429 op_sign ? EA_LOADS : EA_LOADU); \
1430 if (IS_NULL_QREG(result)) { \
1431 gen_addr_fault(s); \
1436 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1437 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1438 if (IS_NULL_QREG(ea_result)) { \
1439 gen_addr_fault(s); \
1444 static inline bool use_goto_tb(DisasContext
*s
, uint32_t dest
)
1446 #ifndef CONFIG_USER_ONLY
1447 return (s
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
1448 (s
->insn_pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
1454 /* Generate a jump to an immediate address. */
1455 static void gen_jmp_tb(DisasContext
*s
, int n
, uint32_t dest
)
1457 if (unlikely(s
->singlestep_enabled
)) {
1458 gen_exception(s
, dest
, EXCP_DEBUG
);
1459 } else if (use_goto_tb(s
, dest
)) {
1461 tcg_gen_movi_i32(QREG_PC
, dest
);
1462 tcg_gen_exit_tb((uintptr_t)s
->tb
+ n
);
1464 gen_jmp_im(s
, dest
);
1467 s
->is_jmp
= DISAS_TB_JUMP
;
1476 cond
= (insn
>> 8) & 0xf;
1477 gen_cc_cond(&c
, s
, cond
);
1479 tmp
= tcg_temp_new();
1480 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
1483 tcg_gen_neg_i32(tmp
, tmp
);
1484 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
1496 reg
= DREG(insn
, 0);
1498 offset
= (int16_t)read_im16(env
, s
);
1499 l1
= gen_new_label();
1500 gen_jmpcc(s
, (insn
>> 8) & 0xf, l1
);
1502 tmp
= tcg_temp_new();
1503 tcg_gen_ext16s_i32(tmp
, reg
);
1504 tcg_gen_addi_i32(tmp
, tmp
, -1);
1505 gen_partset_reg(OS_WORD
, reg
, tmp
);
1506 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, -1, l1
);
1507 gen_jmp_tb(s
, 1, base
+ offset
);
1509 gen_jmp_tb(s
, 0, s
->pc
);
1512 DISAS_INSN(undef_mac
)
1514 gen_exception(s
, s
->insn_pc
, EXCP_LINEA
);
1517 DISAS_INSN(undef_fpu
)
1519 gen_exception(s
, s
->insn_pc
, EXCP_LINEF
);
1524 /* ??? This is both instructions that are as yet unimplemented
1525 for the 680x0 series, as well as those that are implemented
1526 but actually illegal for CPU32 or pre-68020. */
1527 qemu_log_mask(LOG_UNIMP
, "Illegal instruction: %04x @ %08x",
1529 gen_exception(s
, s
->insn_pc
, EXCP_UNSUPPORTED
);
1539 sign
= (insn
& 0x100) != 0;
1540 reg
= DREG(insn
, 9);
1541 tmp
= tcg_temp_new();
1543 tcg_gen_ext16s_i32(tmp
, reg
);
1545 tcg_gen_ext16u_i32(tmp
, reg
);
1546 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1547 tcg_gen_mul_i32(tmp
, tmp
, src
);
1548 tcg_gen_mov_i32(reg
, tmp
);
1549 gen_logic_cc(s
, tmp
, OS_LONG
);
1559 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1561 sign
= (insn
& 0x100) != 0;
1563 /* dest.l / src.w */
1565 SRC_EA(env
, src
, OS_WORD
, sign
, NULL
);
1566 destr
= tcg_const_i32(REG(insn
, 9));
1568 gen_helper_divsw(cpu_env
, destr
, src
);
1570 gen_helper_divuw(cpu_env
, destr
, src
);
1572 tcg_temp_free(destr
);
1574 set_cc_op(s
, CC_OP_FLAGS
);
1583 ext
= read_im16(env
, s
);
1585 sign
= (ext
& 0x0800) != 0;
1588 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
1589 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
1593 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1595 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1596 num
= tcg_const_i32(REG(ext
, 12));
1597 reg
= tcg_const_i32(REG(ext
, 0));
1599 gen_helper_divsll(cpu_env
, num
, reg
, den
);
1601 gen_helper_divull(cpu_env
, num
, reg
, den
);
1605 set_cc_op(s
, CC_OP_FLAGS
);
1609 /* divX.l <EA>, Dq 32/32 -> 32q */
1610 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1612 SRC_EA(env
, den
, OS_LONG
, 0, NULL
);
1613 num
= tcg_const_i32(REG(ext
, 12));
1614 reg
= tcg_const_i32(REG(ext
, 0));
1616 gen_helper_divsl(cpu_env
, num
, reg
, den
);
1618 gen_helper_divul(cpu_env
, num
, reg
, den
);
1623 set_cc_op(s
, CC_OP_FLAGS
);
1626 static void bcd_add(TCGv dest
, TCGv src
)
1630 /* dest10 = dest10 + src10 + X
1634 * t3 = t2 + dest + X
1638 * t7 = (t6 >> 2) | (t6 >> 3)
1642 /* t1 = (src + 0x066) + dest + X
1643 * = result with some possible exceding 0x6
1646 t0
= tcg_const_i32(0x066);
1647 tcg_gen_add_i32(t0
, t0
, src
);
1649 t1
= tcg_temp_new();
1650 tcg_gen_add_i32(t1
, t0
, dest
);
1651 tcg_gen_add_i32(t1
, t1
, QREG_CC_X
);
1653 /* we will remove exceding 0x6 where there is no carry */
1655 /* t0 = (src + 0x0066) ^ dest
1656 * = t1 without carries
1659 tcg_gen_xor_i32(t0
, t0
, dest
);
1661 /* extract the carries
1663 * = only the carries
1666 tcg_gen_xor_i32(t0
, t0
, t1
);
1668 /* generate 0x1 where there is no carry
1669 * and for each 0x10, generate a 0x6
1672 tcg_gen_shri_i32(t0
, t0
, 3);
1673 tcg_gen_not_i32(t0
, t0
);
1674 tcg_gen_andi_i32(t0
, t0
, 0x22);
1675 tcg_gen_add_i32(dest
, t0
, t0
);
1676 tcg_gen_add_i32(dest
, dest
, t0
);
1679 /* remove the exceding 0x6
1680 * for digits that have not generated a carry
1683 tcg_gen_sub_i32(dest
, t1
, dest
);
1687 static void bcd_sub(TCGv dest
, TCGv src
)
1691 /* dest10 = dest10 - src10 - X
1692 * = bcd_add(dest + 1 - X, 0x199 - src)
1695 /* t0 = 0x066 + (0x199 - src) */
1697 t0
= tcg_temp_new();
1698 tcg_gen_subfi_i32(t0
, 0x1ff, src
);
1700 /* t1 = t0 + dest + 1 - X*/
1702 t1
= tcg_temp_new();
1703 tcg_gen_add_i32(t1
, t0
, dest
);
1704 tcg_gen_addi_i32(t1
, t1
, 1);
1705 tcg_gen_sub_i32(t1
, t1
, QREG_CC_X
);
1707 /* t2 = t0 ^ dest */
1709 t2
= tcg_temp_new();
1710 tcg_gen_xor_i32(t2
, t0
, dest
);
1714 tcg_gen_xor_i32(t0
, t1
, t2
);
1717 * t0 = (t2 >> 2) | (t2 >> 3)
1719 * to fit on 8bit operands, changed in:
1721 * t2 = ~(t0 >> 3) & 0x22
1726 tcg_gen_shri_i32(t2
, t0
, 3);
1727 tcg_gen_not_i32(t2
, t2
);
1728 tcg_gen_andi_i32(t2
, t2
, 0x22);
1729 tcg_gen_add_i32(t0
, t2
, t2
);
1730 tcg_gen_add_i32(t0
, t0
, t2
);
1733 /* return t1 - t0 */
1735 tcg_gen_sub_i32(dest
, t1
, t0
);
1740 static void bcd_flags(TCGv val
)
1742 tcg_gen_andi_i32(QREG_CC_C
, val
, 0x0ff);
1743 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_C
);
1745 tcg_gen_extract_i32(QREG_CC_C
, val
, 8, 1);
1747 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
1750 DISAS_INSN(abcd_reg
)
1755 gen_flush_flags(s
); /* !Z is sticky */
1757 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1758 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1760 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1765 DISAS_INSN(abcd_mem
)
1767 TCGv src
, dest
, addr
;
1769 gen_flush_flags(s
); /* !Z is sticky */
1771 /* Indirect pre-decrement load (mode 4) */
1773 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1774 NULL_QREG
, NULL
, EA_LOADU
);
1775 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1776 NULL_QREG
, &addr
, EA_LOADU
);
1780 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
, EA_STORE
);
1785 DISAS_INSN(sbcd_reg
)
1789 gen_flush_flags(s
); /* !Z is sticky */
1791 src
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
1792 dest
= gen_extend(DREG(insn
, 9), OS_BYTE
, 0);
1796 gen_partset_reg(OS_BYTE
, DREG(insn
, 9), dest
);
1801 DISAS_INSN(sbcd_mem
)
1803 TCGv src
, dest
, addr
;
1805 gen_flush_flags(s
); /* !Z is sticky */
1807 /* Indirect pre-decrement load (mode 4) */
1809 src
= gen_ea_mode(env
, s
, 4, REG(insn
, 0), OS_BYTE
,
1810 NULL_QREG
, NULL
, EA_LOADU
);
1811 dest
= gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
,
1812 NULL_QREG
, &addr
, EA_LOADU
);
1816 gen_ea_mode(env
, s
, 4, REG(insn
, 9), OS_BYTE
, dest
, &addr
, EA_STORE
);
1826 gen_flush_flags(s
); /* !Z is sticky */
1828 SRC_EA(env
, src
, OS_BYTE
, 0, &addr
);
1830 dest
= tcg_const_i32(0);
1833 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
1837 tcg_temp_free(dest
);
1850 add
= (insn
& 0x4000) != 0;
1851 opsize
= insn_opsize(insn
);
1852 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
1853 dest
= tcg_temp_new();
1855 SRC_EA(env
, tmp
, opsize
, 1, &addr
);
1859 SRC_EA(env
, src
, opsize
, 1, NULL
);
1862 tcg_gen_add_i32(dest
, tmp
, src
);
1863 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, src
);
1864 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
1866 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, tmp
, src
);
1867 tcg_gen_sub_i32(dest
, tmp
, src
);
1868 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
1870 gen_update_cc_add(dest
, src
, opsize
);
1872 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1874 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
1876 tcg_temp_free(dest
);
1879 /* Reverse the order of the bits in REG. */
1883 reg
= DREG(insn
, 0);
1884 gen_helper_bitrev(reg
, reg
);
1887 DISAS_INSN(bitop_reg
)
1897 if ((insn
& 0x38) != 0)
1901 op
= (insn
>> 6) & 3;
1902 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
1905 src2
= tcg_temp_new();
1906 if (opsize
== OS_BYTE
)
1907 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 7);
1909 tcg_gen_andi_i32(src2
, DREG(insn
, 9), 31);
1911 tmp
= tcg_const_i32(1);
1912 tcg_gen_shl_i32(tmp
, tmp
, src2
);
1913 tcg_temp_free(src2
);
1915 tcg_gen_and_i32(QREG_CC_Z
, src1
, tmp
);
1917 dest
= tcg_temp_new();
1920 tcg_gen_xor_i32(dest
, src1
, tmp
);
1923 tcg_gen_andc_i32(dest
, src1
, tmp
);
1926 tcg_gen_or_i32(dest
, src1
, tmp
);
1933 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
1935 tcg_temp_free(dest
);
1941 reg
= DREG(insn
, 0);
1943 gen_helper_sats(reg
, reg
, QREG_CC_V
);
1944 gen_logic_cc(s
, reg
, OS_LONG
);
1947 static void gen_push(DisasContext
*s
, TCGv val
)
1951 tmp
= tcg_temp_new();
1952 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
1953 gen_store(s
, OS_LONG
, tmp
, val
);
1954 tcg_gen_mov_i32(QREG_SP
, tmp
);
1958 static TCGv
mreg(int reg
)
1962 return cpu_dregs
[reg
];
1965 return cpu_aregs
[reg
& 7];
1970 TCGv addr
, incr
, tmp
, r
[16];
1971 int is_load
= (insn
& 0x0400) != 0;
1972 int opsize
= (insn
& 0x40) != 0 ? OS_LONG
: OS_WORD
;
1973 uint16_t mask
= read_im16(env
, s
);
1974 int mode
= extract32(insn
, 3, 3);
1975 int reg0
= REG(insn
, 0);
1978 tmp
= cpu_aregs
[reg0
];
1981 case 0: /* data register direct */
1982 case 1: /* addr register direct */
1987 case 2: /* indirect */
1990 case 3: /* indirect post-increment */
1992 /* post-increment is not allowed */
1997 case 4: /* indirect pre-decrement */
1999 /* pre-decrement is not allowed */
2002 /* We want a bare copy of the address reg, without any pre-decrement
2003 adjustment, as gen_lea would provide. */
2007 tmp
= gen_lea_mode(env
, s
, mode
, reg0
, opsize
);
2008 if (IS_NULL_QREG(tmp
)) {
2014 addr
= tcg_temp_new();
2015 tcg_gen_mov_i32(addr
, tmp
);
2016 incr
= tcg_const_i32(opsize_bytes(opsize
));
2019 /* memory to register */
2020 for (i
= 0; i
< 16; i
++) {
2021 if (mask
& (1 << i
)) {
2022 r
[i
] = gen_load(s
, opsize
, addr
, 1);
2023 tcg_gen_add_i32(addr
, addr
, incr
);
2026 for (i
= 0; i
< 16; i
++) {
2027 if (mask
& (1 << i
)) {
2028 tcg_gen_mov_i32(mreg(i
), r
[i
]);
2029 tcg_temp_free(r
[i
]);
2033 /* post-increment: movem (An)+,X */
2034 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2037 /* register to memory */
2039 /* pre-decrement: movem X,-(An) */
2040 for (i
= 15; i
>= 0; i
--) {
2041 if ((mask
<< i
) & 0x8000) {
2042 tcg_gen_sub_i32(addr
, addr
, incr
);
2043 if (reg0
+ 8 == i
&&
2044 m68k_feature(s
->env
, M68K_FEATURE_EXT_FULL
)) {
2045 /* M68020+: if the addressing register is the
2046 * register moved to memory, the value written
2047 * is the initial value decremented by the size of
2048 * the operation, regardless of how many actual
2049 * stores have been performed until this point.
2050 * M68000/M68010: the value is the initial value.
2052 tmp
= tcg_temp_new();
2053 tcg_gen_sub_i32(tmp
, cpu_aregs
[reg0
], incr
);
2054 gen_store(s
, opsize
, addr
, tmp
);
2057 gen_store(s
, opsize
, addr
, mreg(i
));
2061 tcg_gen_mov_i32(cpu_aregs
[reg0
], addr
);
2063 for (i
= 0; i
< 16; i
++) {
2064 if (mask
& (1 << i
)) {
2065 gen_store(s
, opsize
, addr
, mreg(i
));
2066 tcg_gen_add_i32(addr
, addr
, incr
);
2072 tcg_temp_free(incr
);
2073 tcg_temp_free(addr
);
2076 DISAS_INSN(bitop_im
)
2086 if ((insn
& 0x38) != 0)
2090 op
= (insn
>> 6) & 3;
2092 bitnum
= read_im16(env
, s
);
2093 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2094 if (bitnum
& 0xfe00) {
2095 disas_undef(env
, s
, insn
);
2099 if (bitnum
& 0xff00) {
2100 disas_undef(env
, s
, insn
);
2105 SRC_EA(env
, src1
, opsize
, 0, op
? &addr
: NULL
);
2108 if (opsize
== OS_BYTE
)
2114 tcg_gen_andi_i32(QREG_CC_Z
, src1
, mask
);
2117 tmp
= tcg_temp_new();
2120 tcg_gen_xori_i32(tmp
, src1
, mask
);
2123 tcg_gen_andi_i32(tmp
, src1
, ~mask
);
2126 tcg_gen_ori_i32(tmp
, src1
, mask
);
2131 DEST_EA(env
, insn
, opsize
, tmp
, &addr
);
2136 static TCGv
gen_get_ccr(DisasContext
*s
)
2141 dest
= tcg_temp_new();
2142 gen_helper_get_ccr(dest
, cpu_env
);
2146 static TCGv
gen_get_sr(DisasContext
*s
)
2151 ccr
= gen_get_ccr(s
);
2152 sr
= tcg_temp_new();
2153 tcg_gen_andi_i32(sr
, QREG_SR
, 0xffe0);
2154 tcg_gen_or_i32(sr
, sr
, ccr
);
2158 static void gen_set_sr_im(DisasContext
*s
, uint16_t val
, int ccr_only
)
2161 tcg_gen_movi_i32(QREG_CC_C
, val
& CCF_C
? 1 : 0);
2162 tcg_gen_movi_i32(QREG_CC_V
, val
& CCF_V
? -1 : 0);
2163 tcg_gen_movi_i32(QREG_CC_Z
, val
& CCF_Z
? 0 : 1);
2164 tcg_gen_movi_i32(QREG_CC_N
, val
& CCF_N
? -1 : 0);
2165 tcg_gen_movi_i32(QREG_CC_X
, val
& CCF_X
? 1 : 0);
2167 TCGv sr
= tcg_const_i32(val
);
2168 gen_helper_set_sr(cpu_env
, sr
);
2171 set_cc_op(s
, CC_OP_FLAGS
);
2174 static void gen_set_sr(DisasContext
*s
, TCGv val
, int ccr_only
)
2177 gen_helper_set_ccr(cpu_env
, val
);
2179 gen_helper_set_sr(cpu_env
, val
);
2181 set_cc_op(s
, CC_OP_FLAGS
);
2184 static void gen_move_to_sr(CPUM68KState
*env
, DisasContext
*s
, uint16_t insn
,
2187 if ((insn
& 0x3f) == 0x3c) {
2189 val
= read_im16(env
, s
);
2190 gen_set_sr_im(s
, val
, ccr_only
);
2193 SRC_EA(env
, src
, OS_WORD
, 0, NULL
);
2194 gen_set_sr(s
, src
, ccr_only
);
2198 DISAS_INSN(arith_im
)
2206 bool with_SR
= ((insn
& 0x3f) == 0x3c);
2208 op
= (insn
>> 9) & 7;
2209 opsize
= insn_opsize(insn
);
2212 im
= tcg_const_i32((int8_t)read_im8(env
, s
));
2215 im
= tcg_const_i32((int16_t)read_im16(env
, s
));
2218 im
= tcg_const_i32(read_im32(env
, s
));
2225 /* SR/CCR can only be used with andi/eori/ori */
2226 if (op
== 2 || op
== 3 || op
== 6) {
2227 disas_undef(env
, s
, insn
);
2232 src1
= gen_get_ccr(s
);
2236 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
2239 src1
= gen_get_sr(s
);
2242 disas_undef(env
, s
, insn
);
2246 SRC_EA(env
, src1
, opsize
, 1, (op
== 6) ? NULL
: &addr
);
2248 dest
= tcg_temp_new();
2251 tcg_gen_or_i32(dest
, src1
, im
);
2253 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2255 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2256 gen_logic_cc(s
, dest
, opsize
);
2260 tcg_gen_and_i32(dest
, src1
, im
);
2262 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2264 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2265 gen_logic_cc(s
, dest
, opsize
);
2269 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, src1
, im
);
2270 tcg_gen_sub_i32(dest
, src1
, im
);
2271 gen_update_cc_add(dest
, im
, opsize
);
2272 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2273 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2276 tcg_gen_add_i32(dest
, src1
, im
);
2277 gen_update_cc_add(dest
, im
, opsize
);
2278 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, im
);
2279 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2280 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2283 tcg_gen_xor_i32(dest
, src1
, im
);
2285 gen_set_sr(s
, dest
, opsize
== OS_BYTE
);
2287 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2288 gen_logic_cc(s
, dest
, opsize
);
2292 gen_update_cc_cmp(s
, src1
, im
, opsize
);
2298 tcg_temp_free(dest
);
2310 switch ((insn
>> 9) & 3) {
2324 g_assert_not_reached();
2327 ext
= read_im16(env
, s
);
2329 /* cas Dc,Du,<EA> */
2331 addr
= gen_lea(env
, s
, insn
, opsize
);
2332 if (IS_NULL_QREG(addr
)) {
2337 cmp
= gen_extend(DREG(ext
, 0), opsize
, 1);
2339 /* if <EA> == Dc then
2341 * Dc = <EA> (because <EA> == Dc)
2346 load
= tcg_temp_new();
2347 tcg_gen_atomic_cmpxchg_i32(load
, addr
, cmp
, DREG(ext
, 6),
2349 /* update flags before setting cmp to load */
2350 gen_update_cc_cmp(s
, load
, cmp
, opsize
);
2351 gen_partset_reg(opsize
, DREG(ext
, 0), load
);
2353 tcg_temp_free(load
);
2355 switch (extract32(insn
, 3, 3)) {
2356 case 3: /* Indirect postincrement. */
2357 tcg_gen_addi_i32(AREG(insn
, 0), addr
, opsize_bytes(opsize
));
2359 case 4: /* Indirect predecrememnt. */
2360 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
2367 uint16_t ext1
, ext2
;
2371 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2373 ext1
= read_im16(env
, s
);
2375 if (ext1
& 0x8000) {
2376 /* Address Register */
2377 addr1
= AREG(ext1
, 12);
2380 addr1
= DREG(ext1
, 12);
2383 ext2
= read_im16(env
, s
);
2384 if (ext2
& 0x8000) {
2385 /* Address Register */
2386 addr2
= AREG(ext2
, 12);
2389 addr2
= DREG(ext2
, 12);
2392 /* if (R1) == Dc1 && (R2) == Dc2 then
2400 regs
= tcg_const_i32(REG(ext2
, 6) |
2401 (REG(ext1
, 6) << 3) |
2402 (REG(ext2
, 0) << 6) |
2403 (REG(ext1
, 0) << 9));
2404 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2405 gen_helper_exit_atomic(cpu_env
);
2407 gen_helper_cas2w(cpu_env
, regs
, addr1
, addr2
);
2409 tcg_temp_free(regs
);
2411 /* Note that cas2w also assigned to env->cc_op. */
2412 s
->cc_op
= CC_OP_CMPW
;
2413 s
->cc_op_synced
= 1;
2418 uint16_t ext1
, ext2
;
2419 TCGv addr1
, addr2
, regs
;
2421 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2423 ext1
= read_im16(env
, s
);
2425 if (ext1
& 0x8000) {
2426 /* Address Register */
2427 addr1
= AREG(ext1
, 12);
2430 addr1
= DREG(ext1
, 12);
2433 ext2
= read_im16(env
, s
);
2434 if (ext2
& 0x8000) {
2435 /* Address Register */
2436 addr2
= AREG(ext2
, 12);
2439 addr2
= DREG(ext2
, 12);
2442 /* if (R1) == Dc1 && (R2) == Dc2 then
2450 regs
= tcg_const_i32(REG(ext2
, 6) |
2451 (REG(ext1
, 6) << 3) |
2452 (REG(ext2
, 0) << 6) |
2453 (REG(ext1
, 0) << 9));
2454 if (tb_cflags(s
->tb
) & CF_PARALLEL
) {
2455 gen_helper_cas2l_parallel(cpu_env
, regs
, addr1
, addr2
);
2457 gen_helper_cas2l(cpu_env
, regs
, addr1
, addr2
);
2459 tcg_temp_free(regs
);
2461 /* Note that cas2l also assigned to env->cc_op. */
2462 s
->cc_op
= CC_OP_CMPL
;
2463 s
->cc_op_synced
= 1;
2470 reg
= DREG(insn
, 0);
2471 tcg_gen_bswap32_i32(reg
, reg
);
2481 switch (insn
>> 12) {
2482 case 1: /* move.b */
2485 case 2: /* move.l */
2488 case 3: /* move.w */
2494 SRC_EA(env
, src
, opsize
, 1, NULL
);
2495 op
= (insn
>> 6) & 7;
2498 /* The value will already have been sign extended. */
2499 dest
= AREG(insn
, 9);
2500 tcg_gen_mov_i32(dest
, src
);
2504 dest_ea
= ((insn
>> 9) & 7) | (op
<< 3);
2505 DEST_EA(env
, dest_ea
, opsize
, src
, NULL
);
2506 /* This will be correct because loads sign extend. */
2507 gen_logic_cc(s
, src
, opsize
);
2518 opsize
= insn_opsize(insn
);
2519 SRC_EA(env
, src
, opsize
, 1, &addr
);
2521 gen_flush_flags(s
); /* compute old Z */
2523 /* Perform substract with borrow.
2524 * (X, N) = -(src + X);
2527 z
= tcg_const_i32(0);
2528 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, z
, QREG_CC_X
, z
);
2529 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, z
, z
, QREG_CC_N
, QREG_CC_X
);
2531 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
2533 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
2535 /* Compute signed-overflow for negation. The normal formula for
2536 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2537 * this simplies to res & src.
2540 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_N
, src
);
2542 /* Copy the rest of the results into place. */
2543 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
2544 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
2546 set_cc_op(s
, CC_OP_FLAGS
);
2548 /* result is in QREG_CC_N */
2550 DEST_EA(env
, insn
, opsize
, QREG_CC_N
, &addr
);
2558 reg
= AREG(insn
, 9);
2559 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2560 if (IS_NULL_QREG(tmp
)) {
2564 tcg_gen_mov_i32(reg
, tmp
);
2572 zero
= tcg_const_i32(0);
2574 opsize
= insn_opsize(insn
);
2575 DEST_EA(env
, insn
, opsize
, zero
, NULL
);
2576 gen_logic_cc(s
, zero
, opsize
);
2577 tcg_temp_free(zero
);
2580 DISAS_INSN(move_from_ccr
)
2584 ccr
= gen_get_ccr(s
);
2585 DEST_EA(env
, insn
, OS_WORD
, ccr
, NULL
);
2595 opsize
= insn_opsize(insn
);
2596 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2597 dest
= tcg_temp_new();
2598 tcg_gen_neg_i32(dest
, src1
);
2599 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2600 gen_update_cc_add(dest
, src1
, opsize
);
2601 tcg_gen_setcondi_i32(TCG_COND_NE
, QREG_CC_X
, dest
, 0);
2602 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2603 tcg_temp_free(dest
);
2606 DISAS_INSN(move_to_ccr
)
2608 gen_move_to_sr(env
, s
, insn
, true);
2618 opsize
= insn_opsize(insn
);
2619 SRC_EA(env
, src1
, opsize
, 1, &addr
);
2620 dest
= tcg_temp_new();
2621 tcg_gen_not_i32(dest
, src1
);
2622 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2623 gen_logic_cc(s
, dest
, opsize
);
2632 src1
= tcg_temp_new();
2633 src2
= tcg_temp_new();
2634 reg
= DREG(insn
, 0);
2635 tcg_gen_shli_i32(src1
, reg
, 16);
2636 tcg_gen_shri_i32(src2
, reg
, 16);
2637 tcg_gen_or_i32(reg
, src1
, src2
);
2638 tcg_temp_free(src2
);
2639 tcg_temp_free(src1
);
2640 gen_logic_cc(s
, reg
, OS_LONG
);
2645 gen_exception(s
, s
->insn_pc
, EXCP_DEBUG
);
2652 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2653 if (IS_NULL_QREG(tmp
)) {
2666 reg
= DREG(insn
, 0);
2667 op
= (insn
>> 6) & 7;
2668 tmp
= tcg_temp_new();
2670 tcg_gen_ext16s_i32(tmp
, reg
);
2672 tcg_gen_ext8s_i32(tmp
, reg
);
2674 gen_partset_reg(OS_WORD
, reg
, tmp
);
2676 tcg_gen_mov_i32(reg
, tmp
);
2677 gen_logic_cc(s
, tmp
, OS_LONG
);
2686 opsize
= insn_opsize(insn
);
2687 SRC_EA(env
, tmp
, opsize
, 1, NULL
);
2688 gen_logic_cc(s
, tmp
, opsize
);
2693 /* Implemented as a NOP. */
2698 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
2701 /* ??? This should be atomic. */
2708 dest
= tcg_temp_new();
2709 SRC_EA(env
, src1
, OS_BYTE
, 1, &addr
);
2710 gen_logic_cc(s
, src1
, OS_BYTE
);
2711 tcg_gen_ori_i32(dest
, src1
, 0x80);
2712 DEST_EA(env
, insn
, OS_BYTE
, dest
, &addr
);
2713 tcg_temp_free(dest
);
2722 ext
= read_im16(env
, s
);
2727 if (!m68k_feature(s
->env
, M68K_FEATURE_QUAD_MULDIV
)) {
2728 gen_exception(s
, s
->insn_pc
, EXCP_UNSUPPORTED
);
2732 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2735 tcg_gen_muls2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2737 tcg_gen_mulu2_i32(QREG_CC_Z
, QREG_CC_N
, src1
, DREG(ext
, 12));
2739 /* if Dl == Dh, 68040 returns low word */
2740 tcg_gen_mov_i32(DREG(ext
, 0), QREG_CC_N
);
2741 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_Z
);
2742 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
);
2744 tcg_gen_movi_i32(QREG_CC_V
, 0);
2745 tcg_gen_movi_i32(QREG_CC_C
, 0);
2747 set_cc_op(s
, CC_OP_FLAGS
);
2750 SRC_EA(env
, src1
, OS_LONG
, 0, NULL
);
2751 if (m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
2752 tcg_gen_movi_i32(QREG_CC_C
, 0);
2754 tcg_gen_muls2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2755 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2756 tcg_gen_sari_i32(QREG_CC_Z
, QREG_CC_N
, 31);
2757 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_Z
);
2759 tcg_gen_mulu2_i32(QREG_CC_N
, QREG_CC_V
, src1
, DREG(ext
, 12));
2760 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2761 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, QREG_CC_C
);
2763 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
2764 tcg_gen_mov_i32(DREG(ext
, 12), QREG_CC_N
);
2766 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
2768 set_cc_op(s
, CC_OP_FLAGS
);
2770 /* The upper 32 bits of the product are discarded, so
2771 muls.l and mulu.l are functionally equivalent. */
2772 tcg_gen_mul_i32(DREG(ext
, 12), src1
, DREG(ext
, 12));
2773 gen_logic_cc(s
, DREG(ext
, 12), OS_LONG
);
2777 static void gen_link(DisasContext
*s
, uint16_t insn
, int32_t offset
)
2782 reg
= AREG(insn
, 0);
2783 tmp
= tcg_temp_new();
2784 tcg_gen_subi_i32(tmp
, QREG_SP
, 4);
2785 gen_store(s
, OS_LONG
, tmp
, reg
);
2786 if ((insn
& 7) != 7) {
2787 tcg_gen_mov_i32(reg
, tmp
);
2789 tcg_gen_addi_i32(QREG_SP
, tmp
, offset
);
2797 offset
= read_im16(env
, s
);
2798 gen_link(s
, insn
, offset
);
2805 offset
= read_im32(env
, s
);
2806 gen_link(s
, insn
, offset
);
2815 src
= tcg_temp_new();
2816 reg
= AREG(insn
, 0);
2817 tcg_gen_mov_i32(src
, reg
);
2818 tmp
= gen_load(s
, OS_LONG
, src
, 0);
2819 tcg_gen_mov_i32(reg
, tmp
);
2820 tcg_gen_addi_i32(QREG_SP
, src
, 4);
2824 #if defined(CONFIG_SOFTMMU)
2828 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
2832 gen_helper_reset(cpu_env
);
2843 int16_t offset
= read_im16(env
, s
);
2845 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
2846 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, offset
+ 4);
2854 tmp
= gen_load(s
, OS_LONG
, QREG_SP
, 0);
2855 tcg_gen_addi_i32(QREG_SP
, QREG_SP
, 4);
2863 /* Load the target address first to ensure correct exception
2865 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
2866 if (IS_NULL_QREG(tmp
)) {
2870 if ((insn
& 0x40) == 0) {
2872 gen_push(s
, tcg_const_i32(s
->pc
));
2886 if ((insn
& 070) == 010) {
2887 /* Operation on address register is always long. */
2890 opsize
= insn_opsize(insn
);
2892 SRC_EA(env
, src
, opsize
, 1, &addr
);
2893 imm
= (insn
>> 9) & 7;
2897 val
= tcg_const_i32(imm
);
2898 dest
= tcg_temp_new();
2899 tcg_gen_mov_i32(dest
, src
);
2900 if ((insn
& 0x38) == 0x08) {
2901 /* Don't update condition codes if the destination is an
2902 address register. */
2903 if (insn
& 0x0100) {
2904 tcg_gen_sub_i32(dest
, dest
, val
);
2906 tcg_gen_add_i32(dest
, dest
, val
);
2909 if (insn
& 0x0100) {
2910 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2911 tcg_gen_sub_i32(dest
, dest
, val
);
2912 set_cc_op(s
, CC_OP_SUBB
+ opsize
);
2914 tcg_gen_add_i32(dest
, dest
, val
);
2915 tcg_gen_setcond_i32(TCG_COND_LTU
, QREG_CC_X
, dest
, val
);
2916 set_cc_op(s
, CC_OP_ADDB
+ opsize
);
2918 gen_update_cc_add(dest
, val
, opsize
);
2921 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
2922 tcg_temp_free(dest
);
2928 case 2: /* One extension word. */
2931 case 3: /* Two extension words. */
2934 case 4: /* No extension words. */
2937 disas_undef(env
, s
, insn
);
2949 op
= (insn
>> 8) & 0xf;
2950 offset
= (int8_t)insn
;
2952 offset
= (int16_t)read_im16(env
, s
);
2953 } else if (offset
== -1) {
2954 offset
= read_im32(env
, s
);
2958 gen_push(s
, tcg_const_i32(s
->pc
));
2962 l1
= gen_new_label();
2963 gen_jmpcc(s
, ((insn
>> 8) & 0xf) ^ 1, l1
);
2964 gen_jmp_tb(s
, 1, base
+ offset
);
2966 gen_jmp_tb(s
, 0, s
->pc
);
2968 /* Unconditional branch. */
2970 gen_jmp_tb(s
, 0, base
+ offset
);
2976 tcg_gen_movi_i32(DREG(insn
, 9), (int8_t)insn
);
2977 gen_logic_cc(s
, DREG(insn
, 9), OS_LONG
);
2990 SRC_EA(env
, src
, opsize
, (insn
& 0x80) == 0, NULL
);
2991 reg
= DREG(insn
, 9);
2992 tcg_gen_mov_i32(reg
, src
);
2993 gen_logic_cc(s
, src
, opsize
);
3004 opsize
= insn_opsize(insn
);
3005 reg
= gen_extend(DREG(insn
, 9), opsize
, 0);
3006 dest
= tcg_temp_new();
3008 SRC_EA(env
, src
, opsize
, 0, &addr
);
3009 tcg_gen_or_i32(dest
, src
, reg
);
3010 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3012 SRC_EA(env
, src
, opsize
, 0, NULL
);
3013 tcg_gen_or_i32(dest
, src
, reg
);
3014 gen_partset_reg(opsize
, DREG(insn
, 9), dest
);
3016 gen_logic_cc(s
, dest
, opsize
);
3017 tcg_temp_free(dest
);
3025 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3026 reg
= AREG(insn
, 9);
3027 tcg_gen_sub_i32(reg
, reg
, src
);
3030 static inline void gen_subx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3034 gen_flush_flags(s
); /* compute old Z */
3036 /* Perform substract with borrow.
3037 * (X, N) = dest - (src + X);
3040 tmp
= tcg_const_i32(0);
3041 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, src
, tmp
, QREG_CC_X
, tmp
);
3042 tcg_gen_sub2_i32(QREG_CC_N
, QREG_CC_X
, dest
, tmp
, QREG_CC_N
, QREG_CC_X
);
3043 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3044 tcg_gen_andi_i32(QREG_CC_X
, QREG_CC_X
, 1);
3046 /* Compute signed-overflow for substract. */
3048 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, dest
);
3049 tcg_gen_xor_i32(tmp
, dest
, src
);
3050 tcg_gen_and_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3053 /* Copy the rest of the results into place. */
3054 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3055 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3057 set_cc_op(s
, CC_OP_FLAGS
);
3059 /* result is in QREG_CC_N */
3062 DISAS_INSN(subx_reg
)
3068 opsize
= insn_opsize(insn
);
3070 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3071 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3073 gen_subx(s
, src
, dest
, opsize
);
3075 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3078 DISAS_INSN(subx_mem
)
3086 opsize
= insn_opsize(insn
);
3088 addr_src
= AREG(insn
, 0);
3089 tcg_gen_subi_i32(addr_src
, addr_src
, opsize
);
3090 src
= gen_load(s
, opsize
, addr_src
, 1);
3092 addr_dest
= AREG(insn
, 9);
3093 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize
);
3094 dest
= gen_load(s
, opsize
, addr_dest
, 1);
3096 gen_subx(s
, src
, dest
, opsize
);
3098 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
3106 val
= (insn
>> 9) & 7;
3109 src
= tcg_const_i32(val
);
3110 gen_logic_cc(s
, src
, OS_LONG
);
3111 DEST_EA(env
, insn
, OS_LONG
, src
, NULL
);
3121 opsize
= insn_opsize(insn
);
3122 SRC_EA(env
, src
, opsize
, 1, NULL
);
3123 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
3124 gen_update_cc_cmp(s
, reg
, src
, opsize
);
3138 SRC_EA(env
, src
, opsize
, 1, NULL
);
3139 reg
= AREG(insn
, 9);
3140 gen_update_cc_cmp(s
, reg
, src
, OS_LONG
);
3145 int opsize
= insn_opsize(insn
);
3148 /* Post-increment load (mode 3) from Ay. */
3149 src
= gen_ea_mode(env
, s
, 3, REG(insn
, 0), opsize
,
3150 NULL_QREG
, NULL
, EA_LOADS
);
3151 /* Post-increment load (mode 3) from Ax. */
3152 dst
= gen_ea_mode(env
, s
, 3, REG(insn
, 9), opsize
,
3153 NULL_QREG
, NULL
, EA_LOADS
);
3155 gen_update_cc_cmp(s
, dst
, src
, opsize
);
3165 opsize
= insn_opsize(insn
);
3167 SRC_EA(env
, src
, opsize
, 0, &addr
);
3168 dest
= tcg_temp_new();
3169 tcg_gen_xor_i32(dest
, src
, DREG(insn
, 9));
3170 gen_logic_cc(s
, dest
, opsize
);
3171 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3172 tcg_temp_free(dest
);
3175 static void do_exg(TCGv reg1
, TCGv reg2
)
3177 TCGv temp
= tcg_temp_new();
3178 tcg_gen_mov_i32(temp
, reg1
);
3179 tcg_gen_mov_i32(reg1
, reg2
);
3180 tcg_gen_mov_i32(reg2
, temp
);
3181 tcg_temp_free(temp
);
3186 /* exchange Dx and Dy */
3187 do_exg(DREG(insn
, 9), DREG(insn
, 0));
3192 /* exchange Ax and Ay */
3193 do_exg(AREG(insn
, 9), AREG(insn
, 0));
3198 /* exchange Dx and Ay */
3199 do_exg(DREG(insn
, 9), AREG(insn
, 0));
3210 dest
= tcg_temp_new();
3212 opsize
= insn_opsize(insn
);
3213 reg
= DREG(insn
, 9);
3215 SRC_EA(env
, src
, opsize
, 0, &addr
);
3216 tcg_gen_and_i32(dest
, src
, reg
);
3217 DEST_EA(env
, insn
, opsize
, dest
, &addr
);
3219 SRC_EA(env
, src
, opsize
, 0, NULL
);
3220 tcg_gen_and_i32(dest
, src
, reg
);
3221 gen_partset_reg(opsize
, reg
, dest
);
3223 gen_logic_cc(s
, dest
, opsize
);
3224 tcg_temp_free(dest
);
3232 SRC_EA(env
, src
, (insn
& 0x100) ? OS_LONG
: OS_WORD
, 1, NULL
);
3233 reg
= AREG(insn
, 9);
3234 tcg_gen_add_i32(reg
, reg
, src
);
3237 static inline void gen_addx(DisasContext
*s
, TCGv src
, TCGv dest
, int opsize
)
3241 gen_flush_flags(s
); /* compute old Z */
3243 /* Perform addition with carry.
3244 * (X, N) = src + dest + X;
3247 tmp
= tcg_const_i32(0);
3248 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_X
, tmp
, dest
, tmp
);
3249 tcg_gen_add2_i32(QREG_CC_N
, QREG_CC_X
, QREG_CC_N
, QREG_CC_X
, src
, tmp
);
3250 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3252 /* Compute signed-overflow for addition. */
3254 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3255 tcg_gen_xor_i32(tmp
, dest
, src
);
3256 tcg_gen_andc_i32(QREG_CC_V
, QREG_CC_V
, tmp
);
3259 /* Copy the rest of the results into place. */
3260 tcg_gen_or_i32(QREG_CC_Z
, QREG_CC_Z
, QREG_CC_N
); /* !Z is sticky */
3261 tcg_gen_mov_i32(QREG_CC_C
, QREG_CC_X
);
3263 set_cc_op(s
, CC_OP_FLAGS
);
3265 /* result is in QREG_CC_N */
3268 DISAS_INSN(addx_reg
)
3274 opsize
= insn_opsize(insn
);
3276 dest
= gen_extend(DREG(insn
, 9), opsize
, 1);
3277 src
= gen_extend(DREG(insn
, 0), opsize
, 1);
3279 gen_addx(s
, src
, dest
, opsize
);
3281 gen_partset_reg(opsize
, DREG(insn
, 9), QREG_CC_N
);
3284 DISAS_INSN(addx_mem
)
3292 opsize
= insn_opsize(insn
);
3294 addr_src
= AREG(insn
, 0);
3295 tcg_gen_subi_i32(addr_src
, addr_src
, opsize_bytes(opsize
));
3296 src
= gen_load(s
, opsize
, addr_src
, 1);
3298 addr_dest
= AREG(insn
, 9);
3299 tcg_gen_subi_i32(addr_dest
, addr_dest
, opsize_bytes(opsize
));
3300 dest
= gen_load(s
, opsize
, addr_dest
, 1);
3302 gen_addx(s
, src
, dest
, opsize
);
3304 gen_store(s
, opsize
, addr_dest
, QREG_CC_N
);
3307 static inline void shift_im(DisasContext
*s
, uint16_t insn
, int opsize
)
3309 int count
= (insn
>> 9) & 7;
3310 int logical
= insn
& 8;
3311 int left
= insn
& 0x100;
3312 int bits
= opsize_bytes(opsize
) * 8;
3313 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3319 tcg_gen_movi_i32(QREG_CC_V
, 0);
3321 tcg_gen_shri_i32(QREG_CC_C
, reg
, bits
- count
);
3322 tcg_gen_shli_i32(QREG_CC_N
, reg
, count
);
3324 /* Note that ColdFire always clears V (done above),
3325 while M68000 sets if the most significant bit is changed at
3326 any time during the shift operation */
3327 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3328 /* if shift count >= bits, V is (reg != 0) */
3329 if (count
>= bits
) {
3330 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, reg
, QREG_CC_V
);
3332 TCGv t0
= tcg_temp_new();
3333 tcg_gen_sari_i32(QREG_CC_V
, reg
, bits
- 1);
3334 tcg_gen_sari_i32(t0
, reg
, bits
- count
- 1);
3335 tcg_gen_setcond_i32(TCG_COND_NE
, QREG_CC_V
, QREG_CC_V
, t0
);
3338 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3341 tcg_gen_shri_i32(QREG_CC_C
, reg
, count
- 1);
3343 tcg_gen_shri_i32(QREG_CC_N
, reg
, count
);
3345 tcg_gen_sari_i32(QREG_CC_N
, reg
, count
);
3349 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3350 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3351 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3352 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3354 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3355 set_cc_op(s
, CC_OP_FLAGS
);
3358 static inline void shift_reg(DisasContext
*s
, uint16_t insn
, int opsize
)
3360 int logical
= insn
& 8;
3361 int left
= insn
& 0x100;
3362 int bits
= opsize_bytes(opsize
) * 8;
3363 TCGv reg
= gen_extend(DREG(insn
, 0), opsize
, !logical
);
3367 t64
= tcg_temp_new_i64();
3368 s64
= tcg_temp_new_i64();
3369 s32
= tcg_temp_new();
3371 /* Note that m68k truncates the shift count modulo 64, not 32.
3372 In addition, a 64-bit shift makes it easy to find "the last
3373 bit shifted out", for the carry flag. */
3374 tcg_gen_andi_i32(s32
, DREG(insn
, 9), 63);
3375 tcg_gen_extu_i32_i64(s64
, s32
);
3376 tcg_gen_extu_i32_i64(t64
, reg
);
3378 /* Optimistically set V=0. Also used as a zero source below. */
3379 tcg_gen_movi_i32(QREG_CC_V
, 0);
3381 tcg_gen_shl_i64(t64
, t64
, s64
);
3383 if (opsize
== OS_LONG
) {
3384 tcg_gen_extr_i64_i32(QREG_CC_N
, QREG_CC_C
, t64
);
3385 /* Note that C=0 if shift count is 0, and we get that for free. */
3387 TCGv zero
= tcg_const_i32(0);
3388 tcg_gen_extrl_i64_i32(QREG_CC_N
, t64
);
3389 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_N
, bits
);
3390 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3391 s32
, zero
, zero
, QREG_CC_C
);
3392 tcg_temp_free(zero
);
3394 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3396 /* X = C, but only if the shift count was non-zero. */
3397 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3398 QREG_CC_C
, QREG_CC_X
);
3400 /* M68000 sets V if the most significant bit is changed at
3401 * any time during the shift operation. Do this via creating
3402 * an extension of the sign bit, comparing, and discarding
3403 * the bits below the sign bit. I.e.
3404 * int64_t s = (intN_t)reg;
3405 * int64_t t = (int64_t)(intN_t)reg << count;
3406 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3408 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3409 TCGv_i64 tt
= tcg_const_i64(32);
3410 /* if shift is greater than 32, use 32 */
3411 tcg_gen_movcond_i64(TCG_COND_GT
, s64
, s64
, tt
, tt
, s64
);
3412 tcg_temp_free_i64(tt
);
3413 /* Sign extend the input to 64 bits; re-do the shift. */
3414 tcg_gen_ext_i32_i64(t64
, reg
);
3415 tcg_gen_shl_i64(s64
, t64
, s64
);
3416 /* Clear all bits that are unchanged. */
3417 tcg_gen_xor_i64(t64
, t64
, s64
);
3418 /* Ignore the bits below the sign bit. */
3419 tcg_gen_andi_i64(t64
, t64
, -1ULL << (bits
- 1));
3420 /* If any bits remain set, we have overflow. */
3421 tcg_gen_setcondi_i64(TCG_COND_NE
, t64
, t64
, 0);
3422 tcg_gen_extrl_i64_i32(QREG_CC_V
, t64
);
3423 tcg_gen_neg_i32(QREG_CC_V
, QREG_CC_V
);
3426 tcg_gen_shli_i64(t64
, t64
, 32);
3428 tcg_gen_shr_i64(t64
, t64
, s64
);
3430 tcg_gen_sar_i64(t64
, t64
, s64
);
3432 tcg_gen_extr_i64_i32(QREG_CC_C
, QREG_CC_N
, t64
);
3434 /* Note that C=0 if shift count is 0, and we get that for free. */
3435 tcg_gen_shri_i32(QREG_CC_C
, QREG_CC_C
, 31);
3437 /* X = C, but only if the shift count was non-zero. */
3438 tcg_gen_movcond_i32(TCG_COND_NE
, QREG_CC_X
, s32
, QREG_CC_V
,
3439 QREG_CC_C
, QREG_CC_X
);
3441 gen_ext(QREG_CC_N
, QREG_CC_N
, opsize
, 1);
3442 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3445 tcg_temp_free_i64(s64
);
3446 tcg_temp_free_i64(t64
);
3448 /* Write back the result. */
3449 gen_partset_reg(opsize
, DREG(insn
, 0), QREG_CC_N
);
3450 set_cc_op(s
, CC_OP_FLAGS
);
3453 DISAS_INSN(shift8_im
)
3455 shift_im(s
, insn
, OS_BYTE
);
3458 DISAS_INSN(shift16_im
)
3460 shift_im(s
, insn
, OS_WORD
);
3463 DISAS_INSN(shift_im
)
3465 shift_im(s
, insn
, OS_LONG
);
3468 DISAS_INSN(shift8_reg
)
3470 shift_reg(s
, insn
, OS_BYTE
);
3473 DISAS_INSN(shift16_reg
)
3475 shift_reg(s
, insn
, OS_WORD
);
3478 DISAS_INSN(shift_reg
)
3480 shift_reg(s
, insn
, OS_LONG
);
3483 DISAS_INSN(shift_mem
)
3485 int logical
= insn
& 8;
3486 int left
= insn
& 0x100;
3490 SRC_EA(env
, src
, OS_WORD
, !logical
, &addr
);
3491 tcg_gen_movi_i32(QREG_CC_V
, 0);
3493 tcg_gen_shri_i32(QREG_CC_C
, src
, 15);
3494 tcg_gen_shli_i32(QREG_CC_N
, src
, 1);
3496 /* Note that ColdFire always clears V,
3497 while M68000 sets if the most significant bit is changed at
3498 any time during the shift operation */
3499 if (!logical
&& m68k_feature(s
->env
, M68K_FEATURE_M68000
)) {
3500 src
= gen_extend(src
, OS_WORD
, 1);
3501 tcg_gen_xor_i32(QREG_CC_V
, QREG_CC_N
, src
);
3504 tcg_gen_mov_i32(QREG_CC_C
, src
);
3506 tcg_gen_shri_i32(QREG_CC_N
, src
, 1);
3508 tcg_gen_sari_i32(QREG_CC_N
, src
, 1);
3512 gen_ext(QREG_CC_N
, QREG_CC_N
, OS_WORD
, 1);
3513 tcg_gen_andi_i32(QREG_CC_C
, QREG_CC_C
, 1);
3514 tcg_gen_mov_i32(QREG_CC_Z
, QREG_CC_N
);
3515 tcg_gen_mov_i32(QREG_CC_X
, QREG_CC_C
);
3517 DEST_EA(env
, insn
, OS_WORD
, QREG_CC_N
, &addr
);
3518 set_cc_op(s
, CC_OP_FLAGS
);
3521 static void rotate(TCGv reg
, TCGv shift
, int left
, int size
)
3525 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3526 tcg_gen_ext8u_i32(reg
, reg
);
3527 tcg_gen_muli_i32(reg
, reg
, 0x01010101);
3530 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3531 tcg_gen_deposit_i32(reg
, reg
, reg
, 16, 16);
3536 tcg_gen_rotl_i32(reg
, reg
, shift
);
3538 tcg_gen_rotr_i32(reg
, reg
, shift
);
3546 tcg_gen_ext8s_i32(reg
, reg
);
3549 tcg_gen_ext16s_i32(reg
, reg
);
3555 /* QREG_CC_X is not affected */
3557 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3558 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3561 tcg_gen_andi_i32(QREG_CC_C
, reg
, 1);
3563 tcg_gen_shri_i32(QREG_CC_C
, reg
, 31);
3566 tcg_gen_movi_i32(QREG_CC_V
, 0); /* always cleared */
3569 static void rotate_x_flags(TCGv reg
, TCGv X
, int size
)
3573 tcg_gen_ext8s_i32(reg
, reg
);
3576 tcg_gen_ext16s_i32(reg
, reg
);
3581 tcg_gen_mov_i32(QREG_CC_N
, reg
);
3582 tcg_gen_mov_i32(QREG_CC_Z
, reg
);
3583 tcg_gen_mov_i32(QREG_CC_X
, X
);
3584 tcg_gen_mov_i32(QREG_CC_C
, X
);
3585 tcg_gen_movi_i32(QREG_CC_V
, 0);
3588 /* Result of rotate_x() is valid if 0 <= shift <= size */
3589 static TCGv
rotate_x(TCGv reg
, TCGv shift
, int left
, int size
)
3591 TCGv X
, shl
, shr
, shx
, sz
, zero
;
3593 sz
= tcg_const_i32(size
);
3595 shr
= tcg_temp_new();
3596 shl
= tcg_temp_new();
3597 shx
= tcg_temp_new();
3599 tcg_gen_mov_i32(shl
, shift
); /* shl = shift */
3600 tcg_gen_movi_i32(shr
, size
+ 1);
3601 tcg_gen_sub_i32(shr
, shr
, shift
); /* shr = size + 1 - shift */
3602 tcg_gen_subi_i32(shx
, shift
, 1); /* shx = shift - 1 */
3603 /* shx = shx < 0 ? size : shx; */
3604 zero
= tcg_const_i32(0);
3605 tcg_gen_movcond_i32(TCG_COND_LT
, shx
, shx
, zero
, sz
, shx
);
3606 tcg_temp_free(zero
);
3608 tcg_gen_mov_i32(shr
, shift
); /* shr = shift */
3609 tcg_gen_movi_i32(shl
, size
+ 1);
3610 tcg_gen_sub_i32(shl
, shl
, shift
); /* shl = size + 1 - shift */
3611 tcg_gen_sub_i32(shx
, sz
, shift
); /* shx = size - shift */
3614 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3616 tcg_gen_shl_i32(shl
, reg
, shl
);
3617 tcg_gen_shr_i32(shr
, reg
, shr
);
3618 tcg_gen_or_i32(reg
, shl
, shr
);
3621 tcg_gen_shl_i32(shx
, QREG_CC_X
, shx
);
3622 tcg_gen_or_i32(reg
, reg
, shx
);
3625 /* X = (reg >> size) & 1 */
3628 tcg_gen_shr_i32(X
, reg
, sz
);
3629 tcg_gen_andi_i32(X
, X
, 1);
3635 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3636 static TCGv
rotate32_x(TCGv reg
, TCGv shift
, int left
)
3638 TCGv_i64 t0
, shift64
;
3639 TCGv X
, lo
, hi
, zero
;
3641 shift64
= tcg_temp_new_i64();
3642 tcg_gen_extu_i32_i64(shift64
, shift
);
3644 t0
= tcg_temp_new_i64();
3647 lo
= tcg_temp_new();
3648 hi
= tcg_temp_new();
3651 /* create [reg:X:..] */
3653 tcg_gen_shli_i32(lo
, QREG_CC_X
, 31);
3654 tcg_gen_concat_i32_i64(t0
, lo
, reg
);
3658 tcg_gen_rotl_i64(t0
, t0
, shift64
);
3659 tcg_temp_free_i64(shift64
);
3661 /* result is [reg:..:reg:X] */
3663 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3664 tcg_gen_andi_i32(X
, lo
, 1);
3666 tcg_gen_shri_i32(lo
, lo
, 1);
3668 /* create [..:X:reg] */
3670 tcg_gen_concat_i32_i64(t0
, reg
, QREG_CC_X
);
3672 tcg_gen_rotr_i64(t0
, t0
, shift64
);
3673 tcg_temp_free_i64(shift64
);
3675 /* result is value: [X:reg:..:reg] */
3677 tcg_gen_extr_i64_i32(lo
, hi
, t0
);
3681 tcg_gen_shri_i32(X
, hi
, 31);
3683 /* extract result */
3685 tcg_gen_shli_i32(hi
, hi
, 1);
3687 tcg_temp_free_i64(t0
);
3688 tcg_gen_or_i32(lo
, lo
, hi
);
3691 /* if shift == 0, register and X are not affected */
3693 zero
= tcg_const_i32(0);
3694 tcg_gen_movcond_i32(TCG_COND_EQ
, X
, shift
, zero
, QREG_CC_X
, X
);
3695 tcg_gen_movcond_i32(TCG_COND_EQ
, reg
, shift
, zero
, reg
, lo
);
3696 tcg_temp_free(zero
);
3702 DISAS_INSN(rotate_im
)
3706 int left
= (insn
& 0x100);
3708 tmp
= (insn
>> 9) & 7;
3713 shift
= tcg_const_i32(tmp
);
3715 rotate(DREG(insn
, 0), shift
, left
, 32);
3717 TCGv X
= rotate32_x(DREG(insn
, 0), shift
, left
);
3718 rotate_x_flags(DREG(insn
, 0), X
, 32);
3721 tcg_temp_free(shift
);
3723 set_cc_op(s
, CC_OP_FLAGS
);
3726 DISAS_INSN(rotate8_im
)
3728 int left
= (insn
& 0x100);
3733 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3735 tmp
= (insn
>> 9) & 7;
3740 shift
= tcg_const_i32(tmp
);
3742 rotate(reg
, shift
, left
, 8);
3744 TCGv X
= rotate_x(reg
, shift
, left
, 8);
3745 rotate_x_flags(reg
, X
, 8);
3748 tcg_temp_free(shift
);
3749 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3750 set_cc_op(s
, CC_OP_FLAGS
);
3753 DISAS_INSN(rotate16_im
)
3755 int left
= (insn
& 0x100);
3760 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3761 tmp
= (insn
>> 9) & 7;
3766 shift
= tcg_const_i32(tmp
);
3768 rotate(reg
, shift
, left
, 16);
3770 TCGv X
= rotate_x(reg
, shift
, left
, 16);
3771 rotate_x_flags(reg
, X
, 16);
3774 tcg_temp_free(shift
);
3775 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3776 set_cc_op(s
, CC_OP_FLAGS
);
3779 DISAS_INSN(rotate_reg
)
3784 int left
= (insn
& 0x100);
3786 reg
= DREG(insn
, 0);
3787 src
= DREG(insn
, 9);
3788 /* shift in [0..63] */
3789 t0
= tcg_temp_new();
3790 tcg_gen_andi_i32(t0
, src
, 63);
3791 t1
= tcg_temp_new_i32();
3793 tcg_gen_andi_i32(t1
, src
, 31);
3794 rotate(reg
, t1
, left
, 32);
3795 /* if shift == 0, clear C */
3796 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3797 t0
, QREG_CC_V
/* 0 */,
3798 QREG_CC_V
/* 0 */, QREG_CC_C
);
3802 tcg_gen_movi_i32(t1
, 33);
3803 tcg_gen_remu_i32(t1
, t0
, t1
);
3804 X
= rotate32_x(DREG(insn
, 0), t1
, left
);
3805 rotate_x_flags(DREG(insn
, 0), X
, 32);
3810 set_cc_op(s
, CC_OP_FLAGS
);
3813 DISAS_INSN(rotate8_reg
)
3818 int left
= (insn
& 0x100);
3820 reg
= gen_extend(DREG(insn
, 0), OS_BYTE
, 0);
3821 src
= DREG(insn
, 9);
3822 /* shift in [0..63] */
3823 t0
= tcg_temp_new_i32();
3824 tcg_gen_andi_i32(t0
, src
, 63);
3825 t1
= tcg_temp_new_i32();
3827 tcg_gen_andi_i32(t1
, src
, 7);
3828 rotate(reg
, t1
, left
, 8);
3829 /* if shift == 0, clear C */
3830 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3831 t0
, QREG_CC_V
/* 0 */,
3832 QREG_CC_V
/* 0 */, QREG_CC_C
);
3836 tcg_gen_movi_i32(t1
, 9);
3837 tcg_gen_remu_i32(t1
, t0
, t1
);
3838 X
= rotate_x(reg
, t1
, left
, 8);
3839 rotate_x_flags(reg
, X
, 8);
3844 gen_partset_reg(OS_BYTE
, DREG(insn
, 0), reg
);
3845 set_cc_op(s
, CC_OP_FLAGS
);
3848 DISAS_INSN(rotate16_reg
)
3853 int left
= (insn
& 0x100);
3855 reg
= gen_extend(DREG(insn
, 0), OS_WORD
, 0);
3856 src
= DREG(insn
, 9);
3857 /* shift in [0..63] */
3858 t0
= tcg_temp_new_i32();
3859 tcg_gen_andi_i32(t0
, src
, 63);
3860 t1
= tcg_temp_new_i32();
3862 tcg_gen_andi_i32(t1
, src
, 15);
3863 rotate(reg
, t1
, left
, 16);
3864 /* if shift == 0, clear C */
3865 tcg_gen_movcond_i32(TCG_COND_EQ
, QREG_CC_C
,
3866 t0
, QREG_CC_V
/* 0 */,
3867 QREG_CC_V
/* 0 */, QREG_CC_C
);
3871 tcg_gen_movi_i32(t1
, 17);
3872 tcg_gen_remu_i32(t1
, t0
, t1
);
3873 X
= rotate_x(reg
, t1
, left
, 16);
3874 rotate_x_flags(reg
, X
, 16);
3879 gen_partset_reg(OS_WORD
, DREG(insn
, 0), reg
);
3880 set_cc_op(s
, CC_OP_FLAGS
);
3883 DISAS_INSN(rotate_mem
)
3888 int left
= (insn
& 0x100);
3890 SRC_EA(env
, src
, OS_WORD
, 0, &addr
);
3892 shift
= tcg_const_i32(1);
3893 if (insn
& 0x0200) {
3894 rotate(src
, shift
, left
, 16);
3896 TCGv X
= rotate_x(src
, shift
, left
, 16);
3897 rotate_x_flags(src
, X
, 16);
3900 tcg_temp_free(shift
);
3901 DEST_EA(env
, insn
, OS_WORD
, src
, &addr
);
3902 set_cc_op(s
, CC_OP_FLAGS
);
3905 DISAS_INSN(bfext_reg
)
3907 int ext
= read_im16(env
, s
);
3908 int is_sign
= insn
& 0x200;
3909 TCGv src
= DREG(insn
, 0);
3910 TCGv dst
= DREG(ext
, 12);
3911 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
3912 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
3913 int pos
= 32 - ofs
- len
; /* little bit-endian */
3914 TCGv tmp
= tcg_temp_new();
3917 /* In general, we're going to rotate the field so that it's at the
3918 top of the word and then right-shift by the compliment of the
3919 width to extend the field. */
3921 /* Variable width. */
3923 /* Variable offset. */
3924 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
3925 tcg_gen_rotl_i32(tmp
, src
, tmp
);
3927 tcg_gen_rotli_i32(tmp
, src
, ofs
);
3930 shift
= tcg_temp_new();
3931 tcg_gen_neg_i32(shift
, DREG(ext
, 0));
3932 tcg_gen_andi_i32(shift
, shift
, 31);
3933 tcg_gen_sar_i32(QREG_CC_N
, tmp
, shift
);
3935 tcg_gen_mov_i32(dst
, QREG_CC_N
);
3937 tcg_gen_shr_i32(dst
, tmp
, shift
);
3939 tcg_temp_free(shift
);
3941 /* Immediate width. */
3943 /* Variable offset */
3944 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
3945 tcg_gen_rotl_i32(tmp
, src
, tmp
);
3949 /* Immediate offset. If the field doesn't wrap around the
3950 end of the word, rely on (s)extract completely. */
3952 tcg_gen_rotli_i32(tmp
, src
, ofs
);
3958 tcg_gen_sextract_i32(QREG_CC_N
, src
, pos
, len
);
3960 tcg_gen_mov_i32(dst
, QREG_CC_N
);
3962 tcg_gen_extract_i32(dst
, src
, pos
, len
);
3967 set_cc_op(s
, CC_OP_LOGIC
);
3970 DISAS_INSN(bfext_mem
)
3972 int ext
= read_im16(env
, s
);
3973 int is_sign
= insn
& 0x200;
3974 TCGv dest
= DREG(ext
, 12);
3975 TCGv addr
, len
, ofs
;
3977 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
3978 if (IS_NULL_QREG(addr
)) {
3986 len
= tcg_const_i32(extract32(ext
, 0, 5));
3991 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
3995 gen_helper_bfexts_mem(dest
, cpu_env
, addr
, ofs
, len
);
3996 tcg_gen_mov_i32(QREG_CC_N
, dest
);
3998 TCGv_i64 tmp
= tcg_temp_new_i64();
3999 gen_helper_bfextu_mem(tmp
, cpu_env
, addr
, ofs
, len
);
4000 tcg_gen_extr_i64_i32(dest
, QREG_CC_N
, tmp
);
4001 tcg_temp_free_i64(tmp
);
4003 set_cc_op(s
, CC_OP_LOGIC
);
4005 if (!(ext
& 0x20)) {
4008 if (!(ext
& 0x800)) {
4013 DISAS_INSN(bfop_reg
)
4015 int ext
= read_im16(env
, s
);
4016 TCGv src
= DREG(insn
, 0);
4017 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4018 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4019 TCGv mask
, tofs
, tlen
;
4023 if ((insn
& 0x0f00) == 0x0d00) { /* bfffo */
4024 tofs
= tcg_temp_new();
4025 tlen
= tcg_temp_new();
4028 if ((ext
& 0x820) == 0) {
4029 /* Immediate width and offset. */
4030 uint32_t maski
= 0x7fffffffu
>> (len
- 1);
4031 if (ofs
+ len
<= 32) {
4032 tcg_gen_shli_i32(QREG_CC_N
, src
, ofs
);
4034 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4036 tcg_gen_andi_i32(QREG_CC_N
, QREG_CC_N
, ~maski
);
4037 mask
= tcg_const_i32(ror32(maski
, ofs
));
4039 tcg_gen_movi_i32(tofs
, ofs
);
4040 tcg_gen_movi_i32(tlen
, len
);
4043 TCGv tmp
= tcg_temp_new();
4045 /* Variable width */
4046 tcg_gen_subi_i32(tmp
, DREG(ext
, 0), 1);
4047 tcg_gen_andi_i32(tmp
, tmp
, 31);
4048 mask
= tcg_const_i32(0x7fffffffu
);
4049 tcg_gen_shr_i32(mask
, mask
, tmp
);
4051 tcg_gen_addi_i32(tlen
, tmp
, 1);
4054 /* Immediate width */
4055 mask
= tcg_const_i32(0x7fffffffu
>> (len
- 1));
4057 tcg_gen_movi_i32(tlen
, len
);
4061 /* Variable offset */
4062 tcg_gen_andi_i32(tmp
, DREG(ext
, 6), 31);
4063 tcg_gen_rotl_i32(QREG_CC_N
, src
, tmp
);
4064 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4065 tcg_gen_rotr_i32(mask
, mask
, tmp
);
4067 tcg_gen_mov_i32(tofs
, tmp
);
4070 /* Immediate offset (and variable width) */
4071 tcg_gen_rotli_i32(QREG_CC_N
, src
, ofs
);
4072 tcg_gen_andc_i32(QREG_CC_N
, QREG_CC_N
, mask
);
4073 tcg_gen_rotri_i32(mask
, mask
, ofs
);
4075 tcg_gen_movi_i32(tofs
, ofs
);
4080 set_cc_op(s
, CC_OP_LOGIC
);
4082 switch (insn
& 0x0f00) {
4083 case 0x0a00: /* bfchg */
4084 tcg_gen_eqv_i32(src
, src
, mask
);
4086 case 0x0c00: /* bfclr */
4087 tcg_gen_and_i32(src
, src
, mask
);
4089 case 0x0d00: /* bfffo */
4090 gen_helper_bfffo_reg(DREG(ext
, 12), QREG_CC_N
, tofs
, tlen
);
4091 tcg_temp_free(tlen
);
4092 tcg_temp_free(tofs
);
4094 case 0x0e00: /* bfset */
4095 tcg_gen_orc_i32(src
, src
, mask
);
4097 case 0x0800: /* bftst */
4098 /* flags already set; no other work to do. */
4101 g_assert_not_reached();
4103 tcg_temp_free(mask
);
4106 DISAS_INSN(bfop_mem
)
4108 int ext
= read_im16(env
, s
);
4109 TCGv addr
, len
, ofs
;
4112 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4113 if (IS_NULL_QREG(addr
)) {
4121 len
= tcg_const_i32(extract32(ext
, 0, 5));
4126 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4129 switch (insn
& 0x0f00) {
4130 case 0x0a00: /* bfchg */
4131 gen_helper_bfchg_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4133 case 0x0c00: /* bfclr */
4134 gen_helper_bfclr_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4136 case 0x0d00: /* bfffo */
4137 t64
= tcg_temp_new_i64();
4138 gen_helper_bfffo_mem(t64
, cpu_env
, addr
, ofs
, len
);
4139 tcg_gen_extr_i64_i32(DREG(ext
, 12), QREG_CC_N
, t64
);
4140 tcg_temp_free_i64(t64
);
4142 case 0x0e00: /* bfset */
4143 gen_helper_bfset_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4145 case 0x0800: /* bftst */
4146 gen_helper_bfexts_mem(QREG_CC_N
, cpu_env
, addr
, ofs
, len
);
4149 g_assert_not_reached();
4151 set_cc_op(s
, CC_OP_LOGIC
);
4153 if (!(ext
& 0x20)) {
4156 if (!(ext
& 0x800)) {
4161 DISAS_INSN(bfins_reg
)
4163 int ext
= read_im16(env
, s
);
4164 TCGv dst
= DREG(insn
, 0);
4165 TCGv src
= DREG(ext
, 12);
4166 int len
= ((extract32(ext
, 0, 5) - 1) & 31) + 1;
4167 int ofs
= extract32(ext
, 6, 5); /* big bit-endian */
4168 int pos
= 32 - ofs
- len
; /* little bit-endian */
4171 tmp
= tcg_temp_new();
4174 /* Variable width */
4175 tcg_gen_neg_i32(tmp
, DREG(ext
, 0));
4176 tcg_gen_andi_i32(tmp
, tmp
, 31);
4177 tcg_gen_shl_i32(QREG_CC_N
, src
, tmp
);
4179 /* Immediate width */
4180 tcg_gen_shli_i32(QREG_CC_N
, src
, 32 - len
);
4182 set_cc_op(s
, CC_OP_LOGIC
);
4184 /* Immediate width and offset */
4185 if ((ext
& 0x820) == 0) {
4186 /* Check for suitability for deposit. */
4188 tcg_gen_deposit_i32(dst
, dst
, src
, pos
, len
);
4190 uint32_t maski
= -2U << (len
- 1);
4191 uint32_t roti
= (ofs
+ len
) & 31;
4192 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4193 tcg_gen_rotri_i32(tmp
, tmp
, roti
);
4194 tcg_gen_andi_i32(dst
, dst
, ror32(maski
, roti
));
4195 tcg_gen_or_i32(dst
, dst
, tmp
);
4198 TCGv mask
= tcg_temp_new();
4199 TCGv rot
= tcg_temp_new();
4202 /* Variable width */
4203 tcg_gen_subi_i32(rot
, DREG(ext
, 0), 1);
4204 tcg_gen_andi_i32(rot
, rot
, 31);
4205 tcg_gen_movi_i32(mask
, -2);
4206 tcg_gen_shl_i32(mask
, mask
, rot
);
4207 tcg_gen_mov_i32(rot
, DREG(ext
, 0));
4208 tcg_gen_andc_i32(tmp
, src
, mask
);
4210 /* Immediate width (variable offset) */
4211 uint32_t maski
= -2U << (len
- 1);
4212 tcg_gen_andi_i32(tmp
, src
, ~maski
);
4213 tcg_gen_movi_i32(mask
, maski
);
4214 tcg_gen_movi_i32(rot
, len
& 31);
4217 /* Variable offset */
4218 tcg_gen_add_i32(rot
, rot
, DREG(ext
, 6));
4220 /* Immediate offset (variable width) */
4221 tcg_gen_addi_i32(rot
, rot
, ofs
);
4223 tcg_gen_andi_i32(rot
, rot
, 31);
4224 tcg_gen_rotr_i32(mask
, mask
, rot
);
4225 tcg_gen_rotr_i32(tmp
, tmp
, rot
);
4226 tcg_gen_and_i32(dst
, dst
, mask
);
4227 tcg_gen_or_i32(dst
, dst
, tmp
);
4230 tcg_temp_free(mask
);
4235 DISAS_INSN(bfins_mem
)
4237 int ext
= read_im16(env
, s
);
4238 TCGv src
= DREG(ext
, 12);
4239 TCGv addr
, len
, ofs
;
4241 addr
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4242 if (IS_NULL_QREG(addr
)) {
4250 len
= tcg_const_i32(extract32(ext
, 0, 5));
4255 ofs
= tcg_const_i32(extract32(ext
, 6, 5));
4258 gen_helper_bfins_mem(QREG_CC_N
, cpu_env
, addr
, src
, ofs
, len
);
4259 set_cc_op(s
, CC_OP_LOGIC
);
4261 if (!(ext
& 0x20)) {
4264 if (!(ext
& 0x800)) {
4272 reg
= DREG(insn
, 0);
4273 gen_logic_cc(s
, reg
, OS_LONG
);
4274 gen_helper_ff1(reg
, reg
);
4282 switch ((insn
>> 7) & 3) {
4287 if (m68k_feature(env
, M68K_FEATURE_CHK2
)) {
4293 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4296 SRC_EA(env
, src
, opsize
, 1, NULL
);
4297 reg
= gen_extend(DREG(insn
, 9), opsize
, 1);
4300 gen_helper_chk(cpu_env
, reg
, src
);
4306 TCGv addr1
, addr2
, bound1
, bound2
, reg
;
4309 switch ((insn
>> 9) & 3) {
4320 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4324 ext
= read_im16(env
, s
);
4325 if ((ext
& 0x0800) == 0) {
4326 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4330 addr1
= gen_lea(env
, s
, insn
, OS_UNSIZED
);
4331 addr2
= tcg_temp_new();
4332 tcg_gen_addi_i32(addr2
, addr1
, opsize_bytes(opsize
));
4334 bound1
= gen_load(s
, opsize
, addr1
, 1);
4335 tcg_temp_free(addr1
);
4336 bound2
= gen_load(s
, opsize
, addr2
, 1);
4337 tcg_temp_free(addr2
);
4339 reg
= tcg_temp_new();
4341 tcg_gen_mov_i32(reg
, AREG(ext
, 12));
4343 gen_ext(reg
, DREG(ext
, 12), opsize
, 1);
4347 gen_helper_chk2(cpu_env
, reg
, bound1
, bound2
);
4351 static void m68k_copy_line(TCGv dst
, TCGv src
, int index
)
4356 addr
= tcg_temp_new();
4358 t0
= tcg_temp_new_i64();
4359 t1
= tcg_temp_new_i64();
4361 tcg_gen_andi_i32(addr
, src
, ~15);
4362 tcg_gen_qemu_ld64(t0
, addr
, index
);
4363 tcg_gen_addi_i32(addr
, addr
, 8);
4364 tcg_gen_qemu_ld64(t1
, addr
, index
);
4366 tcg_gen_andi_i32(addr
, dst
, ~15);
4367 tcg_gen_qemu_st64(t0
, addr
, index
);
4368 tcg_gen_addi_i32(addr
, addr
, 8);
4369 tcg_gen_qemu_st64(t1
, addr
, index
);
4371 tcg_temp_free_i64(t0
);
4372 tcg_temp_free_i64(t1
);
4373 tcg_temp_free(addr
);
4376 DISAS_INSN(move16_reg
)
4378 int index
= IS_USER(s
);
4382 ext
= read_im16(env
, s
);
4383 if ((ext
& (1 << 15)) == 0) {
4384 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4387 m68k_copy_line(AREG(ext
, 12), AREG(insn
, 0), index
);
4389 /* Ax can be Ay, so save Ay before incrementing Ax */
4390 tmp
= tcg_temp_new();
4391 tcg_gen_mov_i32(tmp
, AREG(ext
, 12));
4392 tcg_gen_addi_i32(AREG(insn
, 0), AREG(insn
, 0), 16);
4393 tcg_gen_addi_i32(AREG(ext
, 12), tmp
, 16);
4397 DISAS_INSN(move16_mem
)
4399 int index
= IS_USER(s
);
4402 reg
= AREG(insn
, 0);
4403 addr
= tcg_const_i32(read_im32(env
, s
));
4405 if ((insn
>> 3) & 1) {
4406 /* MOVE16 (xxx).L, (Ay) */
4407 m68k_copy_line(reg
, addr
, index
);
4409 /* MOVE16 (Ay), (xxx).L */
4410 m68k_copy_line(addr
, reg
, index
);
4413 tcg_temp_free(addr
);
4415 if (((insn
>> 3) & 2) == 0) {
4417 tcg_gen_addi_i32(reg
, reg
, 16);
4427 ext
= read_im16(env
, s
);
4428 if (ext
!= 0x46FC) {
4429 gen_exception(s
, addr
, EXCP_UNSUPPORTED
);
4432 ext
= read_im16(env
, s
);
4433 if (IS_USER(s
) || (ext
& SR_S
) == 0) {
4434 gen_exception(s
, addr
, EXCP_PRIVILEGE
);
4437 gen_push(s
, gen_get_sr(s
));
4438 gen_set_sr_im(s
, ext
, 0);
4441 DISAS_INSN(move_from_sr
)
4445 if (IS_USER(s
) && !m68k_feature(env
, M68K_FEATURE_M68000
)) {
4446 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4450 DEST_EA(env
, insn
, OS_WORD
, sr
, NULL
);
4453 #if defined(CONFIG_SOFTMMU)
4454 DISAS_INSN(move_to_sr
)
4457 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4460 gen_move_to_sr(env
, s
, insn
, false);
4464 DISAS_INSN(move_from_usp
)
4467 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4470 tcg_gen_ld_i32(AREG(insn
, 0), cpu_env
,
4471 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4474 DISAS_INSN(move_to_usp
)
4477 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4480 tcg_gen_st_i32(AREG(insn
, 0), cpu_env
,
4481 offsetof(CPUM68KState
, sp
[M68K_USP
]));
4487 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4491 gen_exception(s
, s
->pc
, EXCP_HALT_INSN
);
4499 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4503 ext
= read_im16(env
, s
);
4505 gen_set_sr_im(s
, ext
, 0);
4506 tcg_gen_movi_i32(cpu_halted
, 1);
4507 gen_exception(s
, s
->pc
, EXCP_HLT
);
4513 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4516 gen_exception(s
, s
->insn_pc
, EXCP_RTE
);
4519 DISAS_INSN(cf_movec
)
4525 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4529 ext
= read_im16(env
, s
);
4532 reg
= AREG(ext
, 12);
4534 reg
= DREG(ext
, 12);
4536 gen_helper_cf_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4540 DISAS_INSN(m68k_movec
)
4546 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4550 ext
= read_im16(env
, s
);
4553 reg
= AREG(ext
, 12);
4555 reg
= DREG(ext
, 12);
4558 gen_helper_m68k_movec_to(cpu_env
, tcg_const_i32(ext
& 0xfff), reg
);
4560 gen_helper_m68k_movec_from(reg
, cpu_env
, tcg_const_i32(ext
& 0xfff));
4568 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4571 /* ICache fetch. Implement as no-op. */
4577 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4580 /* Cache push/invalidate. Implement as no-op. */
4586 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4589 /* Cache push/invalidate. Implement as no-op. */
4595 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4598 /* Invalidate cache line. Implement as no-op. */
4603 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4608 M68kCPU
*cpu
= m68k_env_get_cpu(env
);
4611 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
4614 /* TODO: Implement wdebug. */
4615 cpu_abort(CPU(cpu
), "WDEBUG not implemented");
4621 gen_exception(s
, s
->insn_pc
, EXCP_TRAP0
+ (insn
& 0xf));
4624 static void gen_load_fcr(DisasContext
*s
, TCGv res
, int reg
)
4628 tcg_gen_movi_i32(res
, 0);
4631 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4634 tcg_gen_ld_i32(res
, cpu_env
, offsetof(CPUM68KState
, fpcr
));
4639 static void gen_store_fcr(DisasContext
*s
, TCGv val
, int reg
)
4645 tcg_gen_st_i32(val
, cpu_env
, offsetof(CPUM68KState
, fpsr
));
4648 gen_helper_set_fpcr(cpu_env
, val
);
4653 static void gen_qemu_store_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4655 int index
= IS_USER(s
);
4658 tmp
= tcg_temp_new();
4659 gen_load_fcr(s
, tmp
, reg
);
4660 tcg_gen_qemu_st32(tmp
, addr
, index
);
4664 static void gen_qemu_load_fcr(DisasContext
*s
, TCGv addr
, int reg
)
4666 int index
= IS_USER(s
);
4669 tmp
= tcg_temp_new();
4670 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
4671 gen_store_fcr(s
, tmp
, reg
);
4676 static void gen_op_fmove_fcr(CPUM68KState
*env
, DisasContext
*s
,
4677 uint32_t insn
, uint32_t ext
)
4679 int mask
= (ext
>> 10) & 7;
4680 int is_write
= (ext
>> 13) & 1;
4681 int mode
= extract32(insn
, 3, 3);
4687 if (mask
!= M68K_FPIAR
&& mask
!= M68K_FPSR
&& mask
!= M68K_FPCR
) {
4688 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4692 gen_load_fcr(s
, DREG(insn
, 0), mask
);
4694 gen_store_fcr(s
, DREG(insn
, 0), mask
);
4697 case 1: /* An, only with FPIAR */
4698 if (mask
!= M68K_FPIAR
) {
4699 gen_exception(s
, s
->insn_pc
, EXCP_ILLEGAL
);
4703 gen_load_fcr(s
, AREG(insn
, 0), mask
);
4705 gen_store_fcr(s
, AREG(insn
, 0), mask
);
4712 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
4713 if (IS_NULL_QREG(tmp
)) {
4718 addr
= tcg_temp_new();
4719 tcg_gen_mov_i32(addr
, tmp
);
4723 * 0b100 Floating-Point Control Register
4724 * 0b010 Floating-Point Status Register
4725 * 0b001 Floating-Point Instruction Address Register
4729 if (is_write
&& mode
== 4) {
4730 for (i
= 2; i
>= 0; i
--, mask
>>= 1) {
4732 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4734 tcg_gen_subi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4738 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4740 for (i
= 0; i
< 3; i
++, mask
>>= 1) {
4743 gen_qemu_store_fcr(s
, addr
, 1 << i
);
4745 gen_qemu_load_fcr(s
, addr
, 1 << i
);
4747 if (mask
!= 1 || mode
== 3) {
4748 tcg_gen_addi_i32(addr
, addr
, opsize_bytes(OS_LONG
));
4753 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
4756 tcg_temp_free_i32(addr
);
4759 static void gen_op_fmovem(CPUM68KState
*env
, DisasContext
*s
,
4760 uint32_t insn
, uint32_t ext
)
4764 int mode
= (ext
>> 11) & 0x3;
4765 int is_load
= ((ext
& 0x2000) == 0);
4767 if (m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4768 opsize
= OS_EXTENDED
;
4770 opsize
= OS_DOUBLE
; /* FIXME */
4773 addr
= gen_lea(env
, s
, insn
, opsize
);
4774 if (IS_NULL_QREG(addr
)) {
4779 tmp
= tcg_temp_new();
4781 /* Dynamic register list */
4782 tcg_gen_ext8u_i32(tmp
, DREG(ext
, 4));
4784 /* Static register list */
4785 tcg_gen_movi_i32(tmp
, ext
& 0xff);
4788 if (!is_load
&& (mode
& 2) == 0) {
4789 /* predecrement addressing mode
4790 * only available to store register to memory
4792 if (opsize
== OS_EXTENDED
) {
4793 gen_helper_fmovemx_st_predec(tmp
, cpu_env
, addr
, tmp
);
4795 gen_helper_fmovemd_st_predec(tmp
, cpu_env
, addr
, tmp
);
4798 /* postincrement addressing mode */
4799 if (opsize
== OS_EXTENDED
) {
4801 gen_helper_fmovemx_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4803 gen_helper_fmovemx_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4807 gen_helper_fmovemd_ld_postinc(tmp
, cpu_env
, addr
, tmp
);
4809 gen_helper_fmovemd_st_postinc(tmp
, cpu_env
, addr
, tmp
);
4813 if ((insn
& 070) == 030 || (insn
& 070) == 040) {
4814 tcg_gen_mov_i32(AREG(insn
, 0), tmp
);
4819 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
4820 immediately before the next FP instruction is executed. */
4826 TCGv_ptr cpu_src
, cpu_dest
;
4828 ext
= read_im16(env
, s
);
4829 opmode
= ext
& 0x7f;
4830 switch ((ext
>> 13) & 7) {
4836 if (insn
== 0xf200 && (ext
& 0xfc00) == 0x5c00) {
4838 TCGv rom_offset
= tcg_const_i32(opmode
);
4839 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
4840 gen_helper_fconst(cpu_env
, cpu_dest
, rom_offset
);
4841 tcg_temp_free_ptr(cpu_dest
);
4842 tcg_temp_free(rom_offset
);
4846 case 3: /* fmove out */
4847 cpu_src
= gen_fp_ptr(REG(ext
, 7));
4848 opsize
= ext_opsize(ext
, 10);
4849 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
, EA_STORE
) == -1) {
4852 gen_helper_ftst(cpu_env
, cpu_src
);
4853 tcg_temp_free_ptr(cpu_src
);
4855 case 4: /* fmove to control register. */
4856 case 5: /* fmove from control register. */
4857 gen_op_fmove_fcr(env
, s
, insn
, ext
);
4859 case 6: /* fmovem */
4861 if ((ext
& 0x1000) == 0 && !m68k_feature(s
->env
, M68K_FEATURE_FPU
)) {
4864 gen_op_fmovem(env
, s
, insn
, ext
);
4867 if (ext
& (1 << 14)) {
4868 /* Source effective address. */
4869 opsize
= ext_opsize(ext
, 10);
4870 cpu_src
= gen_fp_result_ptr();
4871 if (gen_ea_fp(env
, s
, insn
, opsize
, cpu_src
, EA_LOADS
) == -1) {
4876 /* Source register. */
4877 opsize
= OS_EXTENDED
;
4878 cpu_src
= gen_fp_ptr(REG(ext
, 10));
4880 cpu_dest
= gen_fp_ptr(REG(ext
, 7));
4883 gen_fp_move(cpu_dest
, cpu_src
);
4885 case 0x40: /* fsmove */
4886 gen_helper_fsround(cpu_env
, cpu_dest
, cpu_src
);
4888 case 0x44: /* fdmove */
4889 gen_helper_fdround(cpu_env
, cpu_dest
, cpu_src
);
4892 gen_helper_firound(cpu_env
, cpu_dest
, cpu_src
);
4894 case 3: /* fintrz */
4895 gen_helper_fitrunc(cpu_env
, cpu_dest
, cpu_src
);
4898 gen_helper_fsqrt(cpu_env
, cpu_dest
, cpu_src
);
4900 case 0x41: /* fssqrt */
4901 gen_helper_fssqrt(cpu_env
, cpu_dest
, cpu_src
);
4903 case 0x45: /* fdsqrt */
4904 gen_helper_fdsqrt(cpu_env
, cpu_dest
, cpu_src
);
4906 case 0x18: /* fabs */
4907 gen_helper_fabs(cpu_env
, cpu_dest
, cpu_src
);
4909 case 0x58: /* fsabs */
4910 gen_helper_fsabs(cpu_env
, cpu_dest
, cpu_src
);
4912 case 0x5c: /* fdabs */
4913 gen_helper_fdabs(cpu_env
, cpu_dest
, cpu_src
);
4915 case 0x1a: /* fneg */
4916 gen_helper_fneg(cpu_env
, cpu_dest
, cpu_src
);
4918 case 0x5a: /* fsneg */
4919 gen_helper_fsneg(cpu_env
, cpu_dest
, cpu_src
);
4921 case 0x5e: /* fdneg */
4922 gen_helper_fdneg(cpu_env
, cpu_dest
, cpu_src
);
4924 case 0x20: /* fdiv */
4925 gen_helper_fdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4927 case 0x60: /* fsdiv */
4928 gen_helper_fsdiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4930 case 0x64: /* fddiv */
4931 gen_helper_fddiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4933 case 0x22: /* fadd */
4934 gen_helper_fadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4936 case 0x62: /* fsadd */
4937 gen_helper_fsadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4939 case 0x66: /* fdadd */
4940 gen_helper_fdadd(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4942 case 0x23: /* fmul */
4943 gen_helper_fmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4945 case 0x63: /* fsmul */
4946 gen_helper_fsmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4948 case 0x67: /* fdmul */
4949 gen_helper_fdmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4951 case 0x24: /* fsgldiv */
4952 gen_helper_fsgldiv(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4954 case 0x27: /* fsglmul */
4955 gen_helper_fsglmul(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4957 case 0x28: /* fsub */
4958 gen_helper_fsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4960 case 0x68: /* fssub */
4961 gen_helper_fssub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4963 case 0x6c: /* fdsub */
4964 gen_helper_fdsub(cpu_env
, cpu_dest
, cpu_src
, cpu_dest
);
4966 case 0x38: /* fcmp */
4967 gen_helper_fcmp(cpu_env
, cpu_src
, cpu_dest
);
4969 case 0x3a: /* ftst */
4970 gen_helper_ftst(cpu_env
, cpu_src
);
4975 tcg_temp_free_ptr(cpu_src
);
4976 gen_helper_ftst(cpu_env
, cpu_dest
);
4977 tcg_temp_free_ptr(cpu_dest
);
4980 /* FIXME: Is this right for offset addressing modes? */
4982 disas_undef_fpu(env
, s
, insn
);
4985 static void gen_fcc_cond(DisasCompare
*c
, DisasContext
*s
, int cond
)
4990 c
->v2
= tcg_const_i32(0);
4992 /* TODO: Raise BSUN exception. */
4993 fpsr
= tcg_temp_new();
4994 gen_load_fcr(s
, fpsr
, M68K_FPSR
);
4997 case 16: /* Signaling False */
4999 c
->tcond
= TCG_COND_NEVER
;
5001 case 1: /* EQual Z */
5002 case 17: /* Signaling EQual Z */
5003 c
->v1
= tcg_temp_new();
5005 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5006 c
->tcond
= TCG_COND_NE
;
5008 case 2: /* Ordered Greater Than !(A || Z || N) */
5009 case 18: /* Greater Than !(A || Z || N) */
5010 c
->v1
= tcg_temp_new();
5012 tcg_gen_andi_i32(c
->v1
, fpsr
,
5013 FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5014 c
->tcond
= TCG_COND_EQ
;
5016 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5017 case 19: /* Greater than or Equal Z || !(A || N) */
5018 c
->v1
= tcg_temp_new();
5020 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5021 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5022 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_Z
| FPSR_CC_N
);
5023 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5024 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5025 c
->tcond
= TCG_COND_NE
;
5027 case 4: /* Ordered Less Than !(!N || A || Z); */
5028 case 20: /* Less Than !(!N || A || Z); */
5029 c
->v1
= tcg_temp_new();
5031 tcg_gen_xori_i32(c
->v1
, fpsr
, FPSR_CC_N
);
5032 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_N
| FPSR_CC_A
| FPSR_CC_Z
);
5033 c
->tcond
= TCG_COND_EQ
;
5035 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5036 case 21: /* Less than or Equal Z || (N && !A) */
5037 c
->v1
= tcg_temp_new();
5039 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5040 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_A
));
5041 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5042 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_Z
| FPSR_CC_N
);
5043 c
->tcond
= TCG_COND_NE
;
5045 case 6: /* Ordered Greater or Less than !(A || Z) */
5046 case 22: /* Greater or Less than !(A || Z) */
5047 c
->v1
= tcg_temp_new();
5049 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5050 c
->tcond
= TCG_COND_EQ
;
5052 case 7: /* Ordered !A */
5053 case 23: /* Greater, Less or Equal !A */
5054 c
->v1
= tcg_temp_new();
5056 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5057 c
->tcond
= TCG_COND_EQ
;
5059 case 8: /* Unordered A */
5060 case 24: /* Not Greater, Less or Equal A */
5061 c
->v1
= tcg_temp_new();
5063 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
);
5064 c
->tcond
= TCG_COND_NE
;
5066 case 9: /* Unordered or Equal A || Z */
5067 case 25: /* Not Greater or Less then A || Z */
5068 c
->v1
= tcg_temp_new();
5070 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
);
5071 c
->tcond
= TCG_COND_NE
;
5073 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5074 case 26: /* Not Less or Equal A || !(N || Z)) */
5075 c
->v1
= tcg_temp_new();
5077 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5078 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5079 tcg_gen_andi_i32(fpsr
, fpsr
, FPSR_CC_A
| FPSR_CC_N
);
5080 tcg_gen_or_i32(c
->v1
, c
->v1
, fpsr
);
5081 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5082 c
->tcond
= TCG_COND_NE
;
5084 case 11: /* Unordered or Greater or Equal A || Z || !N */
5085 case 27: /* Not Less Than A || Z || !N */
5086 c
->v1
= tcg_temp_new();
5088 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5089 tcg_gen_xori_i32(c
->v1
, c
->v1
, FPSR_CC_N
);
5090 c
->tcond
= TCG_COND_NE
;
5092 case 12: /* Unordered or Less Than A || (N && !Z) */
5093 case 28: /* Not Greater than or Equal A || (N && !Z) */
5094 c
->v1
= tcg_temp_new();
5096 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5097 tcg_gen_shli_i32(c
->v1
, c
->v1
, ctz32(FPSR_CC_N
) - ctz32(FPSR_CC_Z
));
5098 tcg_gen_andc_i32(c
->v1
, fpsr
, c
->v1
);
5099 tcg_gen_andi_i32(c
->v1
, c
->v1
, FPSR_CC_A
| FPSR_CC_N
);
5100 c
->tcond
= TCG_COND_NE
;
5102 case 13: /* Unordered or Less or Equal A || Z || N */
5103 case 29: /* Not Greater Than A || Z || N */
5104 c
->v1
= tcg_temp_new();
5106 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_A
| FPSR_CC_Z
| FPSR_CC_N
);
5107 c
->tcond
= TCG_COND_NE
;
5109 case 14: /* Not Equal !Z */
5110 case 30: /* Signaling Not Equal !Z */
5111 c
->v1
= tcg_temp_new();
5113 tcg_gen_andi_i32(c
->v1
, fpsr
, FPSR_CC_Z
);
5114 c
->tcond
= TCG_COND_EQ
;
5117 case 31: /* Signaling True */
5119 c
->tcond
= TCG_COND_ALWAYS
;
5122 tcg_temp_free(fpsr
);
5125 static void gen_fjmpcc(DisasContext
*s
, int cond
, TCGLabel
*l1
)
5129 gen_fcc_cond(&c
, s
, cond
);
5131 tcg_gen_brcond_i32(c
.tcond
, c
.v1
, c
.v2
, l1
);
5142 offset
= (int16_t)read_im16(env
, s
);
5143 if (insn
& (1 << 6)) {
5144 offset
= (offset
<< 16) | read_im16(env
, s
);
5147 l1
= gen_new_label();
5149 gen_fjmpcc(s
, insn
& 0x3f, l1
);
5150 gen_jmp_tb(s
, 0, s
->pc
);
5152 gen_jmp_tb(s
, 1, base
+ offset
);
5162 ext
= read_im16(env
, s
);
5164 gen_fcc_cond(&c
, s
, cond
);
5166 tmp
= tcg_temp_new();
5167 tcg_gen_setcond_i32(c
.tcond
, tmp
, c
.v1
, c
.v2
);
5170 tcg_gen_neg_i32(tmp
, tmp
);
5171 DEST_EA(env
, insn
, OS_BYTE
, tmp
, NULL
);
5175 #if defined(CONFIG_SOFTMMU)
5176 static void QEMU_NORETURN
disas_frestore(CPUM68KState
*env
,
5177 DisasContext
*s
, uint16_t insn
);
5178 DISAS_INSN(frestore
)
5183 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
5186 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5187 SRC_EA(env
, addr
, OS_LONG
, 0, NULL
);
5188 /* FIXME: check the state frame */
5190 disas_undef(env
, s
, insn
);
5194 static void QEMU_NORETURN
disas_fsave(CPUM68KState
*env
,
5195 DisasContext
*s
, uint16_t insn
);
5199 gen_exception(s
, s
->insn_pc
, EXCP_PRIVILEGE
);
5203 if (m68k_feature(s
->env
, M68K_FEATURE_M68040
)) {
5204 /* always write IDLE */
5205 TCGv idle
= tcg_const_i32(0x41000000);
5206 DEST_EA(env
, insn
, OS_LONG
, idle
, NULL
);
5207 tcg_temp_free(idle
);
5209 disas_undef(env
, s
, insn
);
5214 static inline TCGv
gen_mac_extract_word(DisasContext
*s
, TCGv val
, int upper
)
5216 TCGv tmp
= tcg_temp_new();
5217 if (s
->env
->macsr
& MACSR_FI
) {
5219 tcg_gen_andi_i32(tmp
, val
, 0xffff0000);
5221 tcg_gen_shli_i32(tmp
, val
, 16);
5222 } else if (s
->env
->macsr
& MACSR_SU
) {
5224 tcg_gen_sari_i32(tmp
, val
, 16);
5226 tcg_gen_ext16s_i32(tmp
, val
);
5229 tcg_gen_shri_i32(tmp
, val
, 16);
5231 tcg_gen_ext16u_i32(tmp
, val
);
5236 static void gen_mac_clear_flags(void)
5238 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
,
5239 ~(MACSR_V
| MACSR_Z
| MACSR_N
| MACSR_EV
));
5255 s
->mactmp
= tcg_temp_new_i64();
5259 ext
= read_im16(env
, s
);
5261 acc
= ((insn
>> 7) & 1) | ((ext
>> 3) & 2);
5262 dual
= ((insn
& 0x30) != 0 && (ext
& 3) != 0);
5263 if (dual
&& !m68k_feature(s
->env
, M68K_FEATURE_CF_EMAC_B
)) {
5264 disas_undef(env
, s
, insn
);
5268 /* MAC with load. */
5269 tmp
= gen_lea(env
, s
, insn
, OS_LONG
);
5270 addr
= tcg_temp_new();
5271 tcg_gen_and_i32(addr
, tmp
, QREG_MAC_MASK
);
5272 /* Load the value now to ensure correct exception behavior.
5273 Perform writeback after reading the MAC inputs. */
5274 loadval
= gen_load(s
, OS_LONG
, addr
, 0);
5277 rx
= (ext
& 0x8000) ? AREG(ext
, 12) : DREG(insn
, 12);
5278 ry
= (ext
& 8) ? AREG(ext
, 0) : DREG(ext
, 0);
5280 loadval
= addr
= NULL_QREG
;
5281 rx
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5282 ry
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5285 gen_mac_clear_flags();
5288 /* Disabled because conditional branches clobber temporary vars. */
5289 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && !dual
) {
5290 /* Skip the multiply if we know we will ignore it. */
5291 l1
= gen_new_label();
5292 tmp
= tcg_temp_new();
5293 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 1 << (acc
+ 8));
5294 gen_op_jmp_nz32(tmp
, l1
);
5298 if ((ext
& 0x0800) == 0) {
5300 rx
= gen_mac_extract_word(s
, rx
, (ext
& 0x80) != 0);
5301 ry
= gen_mac_extract_word(s
, ry
, (ext
& 0x40) != 0);
5303 if (s
->env
->macsr
& MACSR_FI
) {
5304 gen_helper_macmulf(s
->mactmp
, cpu_env
, rx
, ry
);
5306 if (s
->env
->macsr
& MACSR_SU
)
5307 gen_helper_macmuls(s
->mactmp
, cpu_env
, rx
, ry
);
5309 gen_helper_macmulu(s
->mactmp
, cpu_env
, rx
, ry
);
5310 switch ((ext
>> 9) & 3) {
5312 tcg_gen_shli_i64(s
->mactmp
, s
->mactmp
, 1);
5315 tcg_gen_shri_i64(s
->mactmp
, s
->mactmp
, 1);
5321 /* Save the overflow flag from the multiply. */
5322 saved_flags
= tcg_temp_new();
5323 tcg_gen_mov_i32(saved_flags
, QREG_MACSR
);
5325 saved_flags
= NULL_QREG
;
5329 /* Disabled because conditional branches clobber temporary vars. */
5330 if ((s
->env
->macsr
& MACSR_OMC
) != 0 && dual
) {
5331 /* Skip the accumulate if the value is already saturated. */
5332 l1
= gen_new_label();
5333 tmp
= tcg_temp_new();
5334 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5335 gen_op_jmp_nz32(tmp
, l1
);
5340 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5342 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5344 if (s
->env
->macsr
& MACSR_FI
)
5345 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5346 else if (s
->env
->macsr
& MACSR_SU
)
5347 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5349 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5352 /* Disabled because conditional branches clobber temporary vars. */
5358 /* Dual accumulate variant. */
5359 acc
= (ext
>> 2) & 3;
5360 /* Restore the overflow flag from the multiplier. */
5361 tcg_gen_mov_i32(QREG_MACSR
, saved_flags
);
5363 /* Disabled because conditional branches clobber temporary vars. */
5364 if ((s
->env
->macsr
& MACSR_OMC
) != 0) {
5365 /* Skip the accumulate if the value is already saturated. */
5366 l1
= gen_new_label();
5367 tmp
= tcg_temp_new();
5368 gen_op_and32(tmp
, QREG_MACSR
, tcg_const_i32(MACSR_PAV0
<< acc
));
5369 gen_op_jmp_nz32(tmp
, l1
);
5373 tcg_gen_sub_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5375 tcg_gen_add_i64(MACREG(acc
), MACREG(acc
), s
->mactmp
);
5376 if (s
->env
->macsr
& MACSR_FI
)
5377 gen_helper_macsatf(cpu_env
, tcg_const_i32(acc
));
5378 else if (s
->env
->macsr
& MACSR_SU
)
5379 gen_helper_macsats(cpu_env
, tcg_const_i32(acc
));
5381 gen_helper_macsatu(cpu_env
, tcg_const_i32(acc
));
5383 /* Disabled because conditional branches clobber temporary vars. */
5388 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(acc
));
5392 rw
= (insn
& 0x40) ? AREG(insn
, 9) : DREG(insn
, 9);
5393 tcg_gen_mov_i32(rw
, loadval
);
5394 /* FIXME: Should address writeback happen with the masked or
5396 switch ((insn
>> 3) & 7) {
5397 case 3: /* Post-increment. */
5398 tcg_gen_addi_i32(AREG(insn
, 0), addr
, 4);
5400 case 4: /* Pre-decrement. */
5401 tcg_gen_mov_i32(AREG(insn
, 0), addr
);
5406 DISAS_INSN(from_mac
)
5412 rx
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5413 accnum
= (insn
>> 9) & 3;
5414 acc
= MACREG(accnum
);
5415 if (s
->env
->macsr
& MACSR_FI
) {
5416 gen_helper_get_macf(rx
, cpu_env
, acc
);
5417 } else if ((s
->env
->macsr
& MACSR_OMC
) == 0) {
5418 tcg_gen_extrl_i64_i32(rx
, acc
);
5419 } else if (s
->env
->macsr
& MACSR_SU
) {
5420 gen_helper_get_macs(rx
, acc
);
5422 gen_helper_get_macu(rx
, acc
);
5425 tcg_gen_movi_i64(acc
, 0);
5426 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5430 DISAS_INSN(move_mac
)
5432 /* FIXME: This can be done without a helper. */
5436 dest
= tcg_const_i32((insn
>> 9) & 3);
5437 gen_helper_mac_move(cpu_env
, dest
, tcg_const_i32(src
));
5438 gen_mac_clear_flags();
5439 gen_helper_mac_set_flags(cpu_env
, dest
);
5442 DISAS_INSN(from_macsr
)
5446 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5447 tcg_gen_mov_i32(reg
, QREG_MACSR
);
5450 DISAS_INSN(from_mask
)
5453 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5454 tcg_gen_mov_i32(reg
, QREG_MAC_MASK
);
5457 DISAS_INSN(from_mext
)
5461 reg
= (insn
& 8) ? AREG(insn
, 0) : DREG(insn
, 0);
5462 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5463 if (s
->env
->macsr
& MACSR_FI
)
5464 gen_helper_get_mac_extf(reg
, cpu_env
, acc
);
5466 gen_helper_get_mac_exti(reg
, cpu_env
, acc
);
5469 DISAS_INSN(macsr_to_ccr
)
5471 TCGv tmp
= tcg_temp_new();
5472 tcg_gen_andi_i32(tmp
, QREG_MACSR
, 0xf);
5473 gen_helper_set_sr(cpu_env
, tmp
);
5475 set_cc_op(s
, CC_OP_FLAGS
);
5483 accnum
= (insn
>> 9) & 3;
5484 acc
= MACREG(accnum
);
5485 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5486 if (s
->env
->macsr
& MACSR_FI
) {
5487 tcg_gen_ext_i32_i64(acc
, val
);
5488 tcg_gen_shli_i64(acc
, acc
, 8);
5489 } else if (s
->env
->macsr
& MACSR_SU
) {
5490 tcg_gen_ext_i32_i64(acc
, val
);
5492 tcg_gen_extu_i32_i64(acc
, val
);
5494 tcg_gen_andi_i32(QREG_MACSR
, QREG_MACSR
, ~(MACSR_PAV0
<< accnum
));
5495 gen_mac_clear_flags();
5496 gen_helper_mac_set_flags(cpu_env
, tcg_const_i32(accnum
));
5499 DISAS_INSN(to_macsr
)
5502 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5503 gen_helper_set_macsr(cpu_env
, val
);
5510 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5511 tcg_gen_ori_i32(QREG_MAC_MASK
, val
, 0xffff0000);
5518 SRC_EA(env
, val
, OS_LONG
, 0, NULL
);
5519 acc
= tcg_const_i32((insn
& 0x400) ? 2 : 0);
5520 if (s
->env
->macsr
& MACSR_FI
)
5521 gen_helper_set_mac_extf(cpu_env
, val
, acc
);
5522 else if (s
->env
->macsr
& MACSR_SU
)
5523 gen_helper_set_mac_exts(cpu_env
, val
, acc
);
5525 gen_helper_set_mac_extu(cpu_env
, val
, acc
);
5528 static disas_proc opcode_table
[65536];
5531 register_opcode (disas_proc proc
, uint16_t opcode
, uint16_t mask
)
5537 /* Sanity check. All set bits must be included in the mask. */
5538 if (opcode
& ~mask
) {
5540 "qemu internal error: bogus opcode definition %04x/%04x\n",
5544 /* This could probably be cleverer. For now just optimize the case where
5545 the top bits are known. */
5546 /* Find the first zero bit in the mask. */
5548 while ((i
& mask
) != 0)
5550 /* Iterate over all combinations of this and lower bits. */
5555 from
= opcode
& ~(i
- 1);
5557 for (i
= from
; i
< to
; i
++) {
5558 if ((i
& mask
) == opcode
)
5559 opcode_table
[i
] = proc
;
5563 /* Register m68k opcode handlers. Order is important.
5564 Later insn override earlier ones. */
5565 void register_m68k_insns (CPUM68KState
*env
)
5567 /* Build the opcode table only once to avoid
5568 multithreading issues. */
5569 if (opcode_table
[0] != NULL
) {
5573 /* use BASE() for instruction available
5574 * for CF_ISA_A and M68000.
5576 #define BASE(name, opcode, mask) \
5577 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5578 #define INSN(name, opcode, mask, feature) do { \
5579 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5580 BASE(name, opcode, mask); \
5582 BASE(undef
, 0000, 0000);
5583 INSN(arith_im
, 0080, fff8
, CF_ISA_A
);
5584 INSN(arith_im
, 0000, ff00
, M68000
);
5585 INSN(chk2
, 00c0
, f9c0
, CHK2
);
5586 INSN(bitrev
, 00c0
, fff8
, CF_ISA_APLUSC
);
5587 BASE(bitop_reg
, 0100, f1c0
);
5588 BASE(bitop_reg
, 0140, f1c0
);
5589 BASE(bitop_reg
, 0180, f1c0
);
5590 BASE(bitop_reg
, 01c0
, f1c0
);
5591 INSN(arith_im
, 0280, fff8
, CF_ISA_A
);
5592 INSN(arith_im
, 0200, ff00
, M68000
);
5593 INSN(undef
, 02c0
, ffc0
, M68000
);
5594 INSN(byterev
, 02c0
, fff8
, CF_ISA_APLUSC
);
5595 INSN(arith_im
, 0480, fff8
, CF_ISA_A
);
5596 INSN(arith_im
, 0400, ff00
, M68000
);
5597 INSN(undef
, 04c0
, ffc0
, M68000
);
5598 INSN(arith_im
, 0600, ff00
, M68000
);
5599 INSN(undef
, 06c0
, ffc0
, M68000
);
5600 INSN(ff1
, 04c0
, fff8
, CF_ISA_APLUSC
);
5601 INSN(arith_im
, 0680, fff8
, CF_ISA_A
);
5602 INSN(arith_im
, 0c00
, ff38
, CF_ISA_A
);
5603 INSN(arith_im
, 0c00
, ff00
, M68000
);
5604 BASE(bitop_im
, 0800, ffc0
);
5605 BASE(bitop_im
, 0840, ffc0
);
5606 BASE(bitop_im
, 0880, ffc0
);
5607 BASE(bitop_im
, 08c0
, ffc0
);
5608 INSN(arith_im
, 0a80
, fff8
, CF_ISA_A
);
5609 INSN(arith_im
, 0a00
, ff00
, M68000
);
5610 INSN(cas
, 0ac0
, ffc0
, CAS
);
5611 INSN(cas
, 0cc0
, ffc0
, CAS
);
5612 INSN(cas
, 0ec0
, ffc0
, CAS
);
5613 INSN(cas2w
, 0cfc
, ffff
, CAS
);
5614 INSN(cas2l
, 0efc
, ffff
, CAS
);
5615 BASE(move
, 1000, f000
);
5616 BASE(move
, 2000, f000
);
5617 BASE(move
, 3000, f000
);
5618 INSN(chk
, 4000, f040
, M68000
);
5619 INSN(strldsr
, 40e7
, ffff
, CF_ISA_APLUSC
);
5620 INSN(negx
, 4080, fff8
, CF_ISA_A
);
5621 INSN(negx
, 4000, ff00
, M68000
);
5622 INSN(undef
, 40c0
, ffc0
, M68000
);
5623 INSN(move_from_sr
, 40c0
, fff8
, CF_ISA_A
);
5624 INSN(move_from_sr
, 40c0
, ffc0
, M68000
);
5625 BASE(lea
, 41c0
, f1c0
);
5626 BASE(clr
, 4200, ff00
);
5627 BASE(undef
, 42c0
, ffc0
);
5628 INSN(move_from_ccr
, 42c0
, fff8
, CF_ISA_A
);
5629 INSN(move_from_ccr
, 42c0
, ffc0
, M68000
);
5630 INSN(neg
, 4480, fff8
, CF_ISA_A
);
5631 INSN(neg
, 4400, ff00
, M68000
);
5632 INSN(undef
, 44c0
, ffc0
, M68000
);
5633 BASE(move_to_ccr
, 44c0
, ffc0
);
5634 INSN(not, 4680, fff8
, CF_ISA_A
);
5635 INSN(not, 4600, ff00
, M68000
);
5636 #if defined(CONFIG_SOFTMMU)
5637 BASE(move_to_sr
, 46c0
, ffc0
);
5639 INSN(nbcd
, 4800, ffc0
, M68000
);
5640 INSN(linkl
, 4808, fff8
, M68000
);
5641 BASE(pea
, 4840, ffc0
);
5642 BASE(swap
, 4840, fff8
);
5643 INSN(bkpt
, 4848, fff8
, BKPT
);
5644 INSN(movem
, 48d0
, fbf8
, CF_ISA_A
);
5645 INSN(movem
, 48e8
, fbf8
, CF_ISA_A
);
5646 INSN(movem
, 4880, fb80
, M68000
);
5647 BASE(ext
, 4880, fff8
);
5648 BASE(ext
, 48c0
, fff8
);
5649 BASE(ext
, 49c0
, fff8
);
5650 BASE(tst
, 4a00
, ff00
);
5651 INSN(tas
, 4ac0
, ffc0
, CF_ISA_B
);
5652 INSN(tas
, 4ac0
, ffc0
, M68000
);
5653 #if defined(CONFIG_SOFTMMU)
5654 INSN(halt
, 4ac8
, ffff
, CF_ISA_A
);
5656 INSN(pulse
, 4acc
, ffff
, CF_ISA_A
);
5657 BASE(illegal
, 4afc
, ffff
);
5658 INSN(mull
, 4c00
, ffc0
, CF_ISA_A
);
5659 INSN(mull
, 4c00
, ffc0
, LONG_MULDIV
);
5660 INSN(divl
, 4c40
, ffc0
, CF_ISA_A
);
5661 INSN(divl
, 4c40
, ffc0
, LONG_MULDIV
);
5662 INSN(sats
, 4c80
, fff8
, CF_ISA_B
);
5663 BASE(trap
, 4e40
, fff0
);
5664 BASE(link
, 4e50
, fff8
);
5665 BASE(unlk
, 4e58
, fff8
);
5666 #if defined(CONFIG_SOFTMMU)
5667 INSN(move_to_usp
, 4e60
, fff8
, USP
);
5668 INSN(move_from_usp
, 4e68
, fff8
, USP
);
5669 INSN(reset
, 4e70
, ffff
, M68000
);
5670 BASE(stop
, 4e72
, ffff
);
5671 BASE(rte
, 4e73
, ffff
);
5672 INSN(cf_movec
, 4e7b
, ffff
, CF_ISA_A
);
5673 INSN(m68k_movec
, 4e7a
, fffe
, M68000
);
5675 BASE(nop
, 4e71
, ffff
);
5676 INSN(rtd
, 4e74
, ffff
, RTD
);
5677 BASE(rts
, 4e75
, ffff
);
5678 BASE(jump
, 4e80
, ffc0
);
5679 BASE(jump
, 4ec0
, ffc0
);
5680 INSN(addsubq
, 5000, f080
, M68000
);
5681 BASE(addsubq
, 5080, f0c0
);
5682 INSN(scc
, 50c0
, f0f8
, CF_ISA_A
); /* Scc.B Dx */
5683 INSN(scc
, 50c0
, f0c0
, M68000
); /* Scc.B <EA> */
5684 INSN(dbcc
, 50c8
, f0f8
, M68000
);
5685 INSN(tpf
, 51f8
, fff8
, CF_ISA_A
);
5687 /* Branch instructions. */
5688 BASE(branch
, 6000, f000
);
5689 /* Disable long branch instructions, then add back the ones we want. */
5690 BASE(undef
, 60ff
, f0ff
); /* All long branches. */
5691 INSN(branch
, 60ff
, f0ff
, CF_ISA_B
);
5692 INSN(undef
, 60ff
, ffff
, CF_ISA_B
); /* bra.l */
5693 INSN(branch
, 60ff
, ffff
, BRAL
);
5694 INSN(branch
, 60ff
, f0ff
, BCCL
);
5696 BASE(moveq
, 7000, f100
);
5697 INSN(mvzs
, 7100, f100
, CF_ISA_B
);
5698 BASE(or, 8000, f000
);
5699 BASE(divw
, 80c0
, f0c0
);
5700 INSN(sbcd_reg
, 8100, f1f8
, M68000
);
5701 INSN(sbcd_mem
, 8108, f1f8
, M68000
);
5702 BASE(addsub
, 9000, f000
);
5703 INSN(undef
, 90c0
, f0c0
, CF_ISA_A
);
5704 INSN(subx_reg
, 9180, f1f8
, CF_ISA_A
);
5705 INSN(subx_reg
, 9100, f138
, M68000
);
5706 INSN(subx_mem
, 9108, f138
, M68000
);
5707 INSN(suba
, 91c0
, f1c0
, CF_ISA_A
);
5708 INSN(suba
, 90c0
, f0c0
, M68000
);
5710 BASE(undef_mac
, a000
, f000
);
5711 INSN(mac
, a000
, f100
, CF_EMAC
);
5712 INSN(from_mac
, a180
, f9b0
, CF_EMAC
);
5713 INSN(move_mac
, a110
, f9fc
, CF_EMAC
);
5714 INSN(from_macsr
,a980
, f9f0
, CF_EMAC
);
5715 INSN(from_mask
, ad80
, fff0
, CF_EMAC
);
5716 INSN(from_mext
, ab80
, fbf0
, CF_EMAC
);
5717 INSN(macsr_to_ccr
, a9c0
, ffff
, CF_EMAC
);
5718 INSN(to_mac
, a100
, f9c0
, CF_EMAC
);
5719 INSN(to_macsr
, a900
, ffc0
, CF_EMAC
);
5720 INSN(to_mext
, ab00
, fbc0
, CF_EMAC
);
5721 INSN(to_mask
, ad00
, ffc0
, CF_EMAC
);
5723 INSN(mov3q
, a140
, f1c0
, CF_ISA_B
);
5724 INSN(cmp
, b000
, f1c0
, CF_ISA_B
); /* cmp.b */
5725 INSN(cmp
, b040
, f1c0
, CF_ISA_B
); /* cmp.w */
5726 INSN(cmpa
, b0c0
, f1c0
, CF_ISA_B
); /* cmpa.w */
5727 INSN(cmp
, b080
, f1c0
, CF_ISA_A
);
5728 INSN(cmpa
, b1c0
, f1c0
, CF_ISA_A
);
5729 INSN(cmp
, b000
, f100
, M68000
);
5730 INSN(eor
, b100
, f100
, M68000
);
5731 INSN(cmpm
, b108
, f138
, M68000
);
5732 INSN(cmpa
, b0c0
, f0c0
, M68000
);
5733 INSN(eor
, b180
, f1c0
, CF_ISA_A
);
5734 BASE(and, c000
, f000
);
5735 INSN(exg_dd
, c140
, f1f8
, M68000
);
5736 INSN(exg_aa
, c148
, f1f8
, M68000
);
5737 INSN(exg_da
, c188
, f1f8
, M68000
);
5738 BASE(mulw
, c0c0
, f0c0
);
5739 INSN(abcd_reg
, c100
, f1f8
, M68000
);
5740 INSN(abcd_mem
, c108
, f1f8
, M68000
);
5741 BASE(addsub
, d000
, f000
);
5742 INSN(undef
, d0c0
, f0c0
, CF_ISA_A
);
5743 INSN(addx_reg
, d180
, f1f8
, CF_ISA_A
);
5744 INSN(addx_reg
, d100
, f138
, M68000
);
5745 INSN(addx_mem
, d108
, f138
, M68000
);
5746 INSN(adda
, d1c0
, f1c0
, CF_ISA_A
);
5747 INSN(adda
, d0c0
, f0c0
, M68000
);
5748 INSN(shift_im
, e080
, f0f0
, CF_ISA_A
);
5749 INSN(shift_reg
, e0a0
, f0f0
, CF_ISA_A
);
5750 INSN(shift8_im
, e000
, f0f0
, M68000
);
5751 INSN(shift16_im
, e040
, f0f0
, M68000
);
5752 INSN(shift_im
, e080
, f0f0
, M68000
);
5753 INSN(shift8_reg
, e020
, f0f0
, M68000
);
5754 INSN(shift16_reg
, e060
, f0f0
, M68000
);
5755 INSN(shift_reg
, e0a0
, f0f0
, M68000
);
5756 INSN(shift_mem
, e0c0
, fcc0
, M68000
);
5757 INSN(rotate_im
, e090
, f0f0
, M68000
);
5758 INSN(rotate8_im
, e010
, f0f0
, M68000
);
5759 INSN(rotate16_im
, e050
, f0f0
, M68000
);
5760 INSN(rotate_reg
, e0b0
, f0f0
, M68000
);
5761 INSN(rotate8_reg
, e030
, f0f0
, M68000
);
5762 INSN(rotate16_reg
, e070
, f0f0
, M68000
);
5763 INSN(rotate_mem
, e4c0
, fcc0
, M68000
);
5764 INSN(bfext_mem
, e9c0
, fdc0
, BITFIELD
); /* bfextu & bfexts */
5765 INSN(bfext_reg
, e9c0
, fdf8
, BITFIELD
);
5766 INSN(bfins_mem
, efc0
, ffc0
, BITFIELD
);
5767 INSN(bfins_reg
, efc0
, fff8
, BITFIELD
);
5768 INSN(bfop_mem
, eac0
, ffc0
, BITFIELD
); /* bfchg */
5769 INSN(bfop_reg
, eac0
, fff8
, BITFIELD
); /* bfchg */
5770 INSN(bfop_mem
, ecc0
, ffc0
, BITFIELD
); /* bfclr */
5771 INSN(bfop_reg
, ecc0
, fff8
, BITFIELD
); /* bfclr */
5772 INSN(bfop_mem
, edc0
, ffc0
, BITFIELD
); /* bfffo */
5773 INSN(bfop_reg
, edc0
, fff8
, BITFIELD
); /* bfffo */
5774 INSN(bfop_mem
, eec0
, ffc0
, BITFIELD
); /* bfset */
5775 INSN(bfop_reg
, eec0
, fff8
, BITFIELD
); /* bfset */
5776 INSN(bfop_mem
, e8c0
, ffc0
, BITFIELD
); /* bftst */
5777 INSN(bfop_reg
, e8c0
, fff8
, BITFIELD
); /* bftst */
5778 BASE(undef_fpu
, f000
, f000
);
5779 INSN(fpu
, f200
, ffc0
, CF_FPU
);
5780 INSN(fbcc
, f280
, ffc0
, CF_FPU
);
5781 INSN(fpu
, f200
, ffc0
, FPU
);
5782 INSN(fscc
, f240
, ffc0
, FPU
);
5783 INSN(fbcc
, f280
, ff80
, FPU
);
5784 #if defined(CONFIG_SOFTMMU)
5785 INSN(frestore
, f340
, ffc0
, CF_FPU
);
5786 INSN(fsave
, f300
, ffc0
, CF_FPU
);
5787 INSN(frestore
, f340
, ffc0
, FPU
);
5788 INSN(fsave
, f300
, ffc0
, FPU
);
5789 INSN(intouch
, f340
, ffc0
, CF_ISA_A
);
5790 INSN(cpushl
, f428
, ff38
, CF_ISA_A
);
5791 INSN(cpush
, f420
, ff20
, M68040
);
5792 INSN(cinv
, f400
, ff20
, M68040
);
5793 INSN(wddata
, fb00
, ff00
, CF_ISA_A
);
5794 INSN(wdebug
, fbc0
, ffc0
, CF_ISA_A
);
5796 INSN(move16_mem
, f600
, ffe0
, M68040
);
5797 INSN(move16_reg
, f620
, fff8
, M68040
);
5801 /* ??? Some of this implementation is not exception safe. We should always
5802 write back the result to memory before setting the condition codes. */
5803 static void disas_m68k_insn(CPUM68KState
* env
, DisasContext
*s
)
5805 uint16_t insn
= read_im16(env
, s
);
5806 opcode_table
[insn
](env
, s
, insn
);
5810 /* generate intermediate code for basic block 'tb'. */
5811 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
)
5813 CPUM68KState
*env
= cs
->env_ptr
;
5814 DisasContext dc1
, *dc
= &dc1
;
5815 target_ulong pc_start
;
5820 /* generate intermediate code */
5826 dc
->is_jmp
= DISAS_NEXT
;
5828 dc
->cc_op
= CC_OP_DYNAMIC
;
5829 dc
->cc_op_synced
= 1;
5830 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
5831 dc
->user
= (env
->sr
& SR_S
) == 0;
5833 dc
->writeback_mask
= 0;
5835 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
5836 if (max_insns
== 0) {
5837 max_insns
= CF_COUNT_MASK
;
5839 if (max_insns
> TCG_MAX_INSNS
) {
5840 max_insns
= TCG_MAX_INSNS
;
5845 pc_offset
= dc
->pc
- pc_start
;
5846 tcg_gen_insn_start(dc
->pc
, dc
->cc_op
);
5849 if (unlikely(cpu_breakpoint_test(cs
, dc
->pc
, BP_ANY
))) {
5850 gen_exception(dc
, dc
->pc
, EXCP_DEBUG
);
5851 dc
->is_jmp
= DISAS_JUMP
;
5852 /* The address covered by the breakpoint must be included in
5853 [tb->pc, tb->pc + tb->size) in order to for it to be
5854 properly cleared -- thus we increment the PC here so that
5855 the logic setting tb->size below does the right thing. */
5860 if (num_insns
== max_insns
&& (tb_cflags(tb
) & CF_LAST_IO
)) {
5864 dc
->insn_pc
= dc
->pc
;
5865 disas_m68k_insn(env
, dc
);
5866 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
5867 !cs
->singlestep_enabled
&&
5869 (pc_offset
) < (TARGET_PAGE_SIZE
- 32) &&
5870 num_insns
< max_insns
);
5872 if (tb_cflags(tb
) & CF_LAST_IO
)
5874 if (unlikely(cs
->singlestep_enabled
)) {
5875 /* Make sure the pc is updated, and raise a debug exception. */
5878 tcg_gen_movi_i32(QREG_PC
, dc
->pc
);
5880 gen_helper_raise_exception(cpu_env
, tcg_const_i32(EXCP_DEBUG
));
5882 switch(dc
->is_jmp
) {
5885 gen_jmp_tb(dc
, 0, dc
->pc
);
5891 /* indicate that the hash table must be used to find the next TB */
5895 /* nothing more to generate */
5899 gen_tb_end(tb
, num_insns
);
5902 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
5903 && qemu_log_in_addr_range(pc_start
)) {
5905 qemu_log("----------------\n");
5906 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
5907 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
);
5912 tb
->size
= dc
->pc
- pc_start
;
5913 tb
->icount
= num_insns
;
5916 static double floatx80_to_double(CPUM68KState
*env
, uint16_t high
, uint64_t low
)
5918 floatx80 a
= { .high
= high
, .low
= low
};
5924 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
5928 void m68k_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
5931 M68kCPU
*cpu
= M68K_CPU(cs
);
5932 CPUM68KState
*env
= &cpu
->env
;
5935 for (i
= 0; i
< 8; i
++) {
5936 cpu_fprintf(f
, "D%d = %08x A%d = %08x "
5937 "F%d = %04x %016"PRIx64
" (%12g)\n",
5938 i
, env
->dregs
[i
], i
, env
->aregs
[i
],
5939 i
, env
->fregs
[i
].l
.upper
, env
->fregs
[i
].l
.lower
,
5940 floatx80_to_double(env
, env
->fregs
[i
].l
.upper
,
5941 env
->fregs
[i
].l
.lower
));
5943 cpu_fprintf (f
, "PC = %08x ", env
->pc
);
5944 sr
= env
->sr
| cpu_m68k_get_ccr(env
);
5945 cpu_fprintf(f
, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
5946 sr
, (sr
& SR_T
) >> SR_T_SHIFT
, (sr
& SR_I
) >> SR_I_SHIFT
,
5947 (sr
& SR_S
) ? 'S' : 'U', (sr
& SR_M
) ? '%' : 'I',
5948 (sr
& CCF_X
) ? 'X' : '-', (sr
& CCF_N
) ? 'N' : '-',
5949 (sr
& CCF_Z
) ? 'Z' : '-', (sr
& CCF_V
) ? 'V' : '-',
5950 (sr
& CCF_C
) ? 'C' : '-');
5951 cpu_fprintf(f
, "FPSR = %08x %c%c%c%c ", env
->fpsr
,
5952 (env
->fpsr
& FPSR_CC_A
) ? 'A' : '-',
5953 (env
->fpsr
& FPSR_CC_I
) ? 'I' : '-',
5954 (env
->fpsr
& FPSR_CC_Z
) ? 'Z' : '-',
5955 (env
->fpsr
& FPSR_CC_N
) ? 'N' : '-');
5956 cpu_fprintf(f
, "\n "
5957 "FPCR = %04x ", env
->fpcr
);
5958 switch (env
->fpcr
& FPCR_PREC_MASK
) {
5960 cpu_fprintf(f
, "X ");
5963 cpu_fprintf(f
, "S ");
5966 cpu_fprintf(f
, "D ");
5969 switch (env
->fpcr
& FPCR_RND_MASK
) {
5971 cpu_fprintf(f
, "RN ");
5974 cpu_fprintf(f
, "RZ ");
5977 cpu_fprintf(f
, "RM ");
5980 cpu_fprintf(f
, "RP ");
5983 cpu_fprintf(f
, "\n");
5984 #ifdef CONFIG_SOFTMMU
5985 cpu_fprintf(f
, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
5986 env
->current_sp
== M68K_SSP
? "->" : " ", env
->sp
[M68K_SSP
],
5987 env
->current_sp
== M68K_USP
? "->" : " ", env
->sp
[M68K_USP
],
5988 env
->current_sp
== M68K_ISP
? "->" : " ", env
->sp
[M68K_ISP
]);
5989 cpu_fprintf(f
, "VBR = 0x%08x\n", env
->vbr
);
5993 void restore_state_to_opc(CPUM68KState
*env
, TranslationBlock
*tb
,
5996 int cc_op
= data
[1];
5998 if (cc_op
!= CC_OP_DYNAMIC
) {