| commit | f85bcec31ee578eccf6182be158d6ac6d9b90a4c | |
| author | Nicholas Piggin <npiggin@gmail.com> | |
| Thu, 20 Oct 2016 06:59:10 +0000 (20 17:59 +1100) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Thu, 27 Oct 2016 22:36:58 +0000 (28 09:36 +1100) | ||
| tree | 567e904942415e82c526d49bb4cfffbb30d86cba | treesnapshot (tar.gz zip) |
| parent | e3403258a20c61859ca1917bb86bc206e5846784 | commitdiff |
ppc: fix MSR_ME handling for system reset interrupt
Power ISA specifies ME bit handling for system reset interrupt:
if the interrupt occurred while the thread was in power-saving
mode, set to 1; otherwise not altered
Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Power ISA specifies ME bit handling for system reset interrupt:
if the interrupt occurred while the thread was in power-saving
mode, set to 1; otherwise not altered
Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target-ppc/excp_helper.c | diffblobblamehistory |