| commit | e6b332097d1a4713173a82f17d039b4c78bc6f59 | |
| author | Michael Davidsaver <mdavidsaver@gmail.com> | |
| Fri, 27 Jan 2017 15:20:23 +0000 (27 15:20 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 27 Jan 2017 15:29:08 +0000 (27 15:29 +0000) | ||
| tree | 751c88de5f71438d1ff50a7e691140357f2e2ae3 | treesnapshot (tar.gz zip) |
| parent | 2c4da50d9477fb830d778bb5d6a11215aa359b44 | commitdiff |
armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR
Implement the v7M system registers CCR, CFSR, HFSR, DFSR, BFAR and
MMFAR. For the moment these simply read as written (with some basic
handling of RAZ/WI bits and W1C semantics).
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-5-git-send-email-peter.maydell@linaro.org
[PMM: drop warning about setting unimplemented CCR bits;
tweak commit message; add DFSR]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Implement the v7M system registers CCR, CFSR, HFSR, DFSR, BFAR and
MMFAR. For the moment these simply read as written (with some basic
handling of RAZ/WI bits and W1C semantics).
Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-5-git-send-email-peter.maydell@linaro.org
[PMM: drop warning about setting unimplemented CCR bits;
tweak commit message; add DFSR]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/intc/armv7m_nvic.c | diffblobblamehistory |