| commit | c6f3f334d157ff6b9bdc4e1b9d9874234138836a | |
| author | Max Filippov <jcmvbkbc@gmail.com> | |
| Tue, 26 Apr 2022 16:24:01 +0000 (26 09:24 -0700) | ||
| committer | Max Filippov <jcmvbkbc@gmail.com> | |
| Fri, 6 May 2022 22:27:40 +0000 (6 15:27 -0700) | ||
| tree | ae4f9c8f07bab8bf6e9b034019bee9b661b0ced2 | treesnapshot (tar.gz zip) |
| parent | 9e377be1f042e8618c54ee786d1022caa0e2409d | commitdiff |
hw/xtensa: fix reset value of MIROUT register of MX PIC
MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| hw/xtensa/mx_pic.c | diffblobblamehistory |