| commit | 59f11543e2ccd5cab283732a7c59aeeaa6790138 | |
| author | Víctor Colombo <victor.colombo@eldorado.org.br> | |
| Wed, 22 Jun 2022 19:32:03 +0000 (22 16:32 -0300) | ||
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | |
| Wed, 6 Jul 2022 13:22:37 +0000 (6 10:22 -0300) | ||
| tree | 554317e1166dc54d0fc8d81e6d22143f617c97e4 | treesnapshot (tar.gz zip) |
| parent | 21870aab36355ff5a1a0dbdb06d2071f3214cab2 | commitdiff |
target/ppc: Change FPSCR_* to follow POWER ISA numbering convention
FPSCR_* bit values in QEMU are in the 'inverted' order from what Power
ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h).
Now that PPC_BIT_NR macro was introduced to fix this situation for the
MSR bits, we can use it for the FPSCR bits too.
Also, adjust the comments to make then fit in 80 columns
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220622193203.127698-1-victor.colombo@eldorado.org.br>
[danielhb: fixed 'exceptio' typo in target/ppc/cpu.h]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
FPSCR_* bit values in QEMU are in the 'inverted' order from what Power
ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h).
Now that PPC_BIT_NR macro was introduced to fix this situation for the
MSR bits, we can use it for the FPSCR bits too.
Also, adjust the comments to make then fit in 80 columns
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220622193203.127698-1-victor.colombo@eldorado.org.br>
[danielhb: fixed 'exceptio' typo in target/ppc/cpu.h]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| target/ppc/cpu.h | diffblobblamehistory |