| commit | 58858759c198dc56498095e387a31178d0d852b9 | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Wed, 23 Mar 2022 07:28:42 +0000 (23 08:28 +0100) | ||
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | |
| Wed, 20 Apr 2022 21:00:30 +0000 (20 18:00 -0300) | ||
| tree | a8002544b3d7c7bb5ee85eca591616b76cb88f28 | treesnapshot (tar.gz zip) |
| parent | 4c7daca302a4f4d0f66f1112e094307863c4f6c8 | commitdiff |
ppc/pnv: Fix PSI IRQ definition
On HW, the PSI and FSP interrupt levels are muxed under the same
interrupt number. For coding reasons, an extra IRQ number was
introduced to index register values in an array. It increased the
count of IRQs which do not fit in the PSI IRQ range anymore.
The PSI and FSP interrupts should be modeled with an extra level of
GPIO lines but since QEMU does not support them, simply drop the extra
number to stay within the IRQ range.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220323072846.1780212-2-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
On HW, the PSI and FSP interrupt levels are muxed under the same
interrupt number. For coding reasons, an extra IRQ number was
introduced to index register values in an array. It increased the
count of IRQs which do not fit in the PSI IRQ range anymore.
The PSI and FSP interrupts should be modeled with an extra level of
GPIO lines but since QEMU does not support them, simply drop the extra
number to stay within the IRQ range.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220323072846.1780212-2-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| hw/ppc/pnv_psi.c | diffblobblamehistory | |
| include/hw/ppc/pnv_psi.h | diffblobblamehistory |