| commit | 4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490 | |
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
| Tue, 11 Apr 2017 15:29:59 +0000 (11 17:29 +0200) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Wed, 26 Apr 2017 02:41:55 +0000 (26 12:41 +1000) | ||
| tree | df8f3cc20ec8a2c29ab9b5ffed551f1887104acc | treesnapshot (tar.gz zip) |
| parent | 71cd4dace9abf51469cfbf6db622124993955f78 | commitdiff |
ppc/pnv: Add support for POWER8+ LPC Controller
It adds the Naples chip which supports proper LPC interrupts via the
LPC controller rather than via an external CPLD.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - updated for qemu-2.9
- ported on latest PowerNV patchset
- moved the IRQ handler in pnv_lpc.c
- introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
It adds the Naples chip which supports proper LPC interrupts via the
LPC controller rather than via an external CPLD.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - updated for qemu-2.9
- ported on latest PowerNV patchset
- moved the IRQ handler in pnv_lpc.c
- introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| hw/ppc/pnv.c | diffblobblamehistory | |
| hw/ppc/pnv_lpc.c | diffblobblamehistory | |
| include/hw/ppc/pnv_lpc.h | diffblobblamehistory |