| commit | 3d9bada2408329269424628a3be6340c6c28de0e | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Tue, 25 Sep 2018 13:02:33 +0000 (25 14:02 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 25 Sep 2018 14:13:24 +0000 (25 15:13 +0100) | ||
| tree | 42e4def4d497143af54aa33650f1f54f4dabaea7 | treesnapshot (tar.gz zip) |
| parent | 03f1d7201a8ac6adeb3aae8c575f3e67e153c54a | commitdiff |
hw/arm/aspeed: change the FMC flash model of the AST2500 evb
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit
to make the chip operate in 4 Byte address mode at power up. This
should be an interesting feature to model as it will exercise a bit
more the SMC controllers and MMIO execution at boot time.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180921161939.822-3-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit
to make the chip operate in 4 Byte address mode at power up. This
should be an interesting feature to model as it will exercise a bit
more the SMC controllers and MMIO execution at boot time.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180921161939.822-3-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/aspeed.c | diffblobblamehistory |