| commit | 24ac0fb129f9ce9dd96901b2377fc6271dc55b2b | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 15 Feb 2018 18:29:37 +0000 (15 18:29 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 15 Feb 2018 18:29:49 +0000 (15 18:29 +0000) | ||
| tree | 46dc892a0c6393c7fb38691d96c3b3ebd06fd08a | treesnapshot (tar.gz zip) |
| parent | 43bbce7fbef22adf687dd84934fd0b2f8df807a8 | commitdiff |
hw/intc/armv7m_nvic: Implement SCR
We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
| hw/intc/armv7m_nvic.c | diffblobblamehistory | |
| target/arm/cpu.h | diffblobblamehistory | |
| target/arm/machine.c | diffblobblamehistory |