| commit | 3db3ee7b371a565df52d3ca6c9aa08af0e754c21 | |
| author | Hollis Blanchard <hollisb@us.ibm.com> | |
| Wed, 30 Apr 2008 21:03:37 +0000 (30 16:03 -0500) | ||
| committer | Avi Kivity <avi@qumranet.com> | |
| Sun, 4 May 2008 08:18:06 +0000 (4 11:18 +0300) | ||
| tree | d109b15ecbb0893de427c910af28e02bd81f0be7 | treesnapshot (tar.gz zip) |
| parent | 9fa02ac3e08ea240f2c931770582fa379da33005 | commitdiff |
Ppc: Remember the state of level-triggered interrupts
This fixes the following race condition:
1. target handles an interrupt and begins to EOI
2. device raises an interrupt, setting UIC SR
3. target finishes EOI by clearing SR bit
On hardware, a device with a level-triggered interrupt would instantly
re-assert SR after step 3, so we need to do the same.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Avi Kivity <avi@qumranet.com>
This fixes the following race condition:
1. target handles an interrupt and begins to EOI
2. device raises an interrupt, setting UIC SR
3. target finishes EOI by clearing SR bit
On hardware, a device with a level-triggered interrupt would instantly
re-assert SR after step 3, so we need to do the same.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Avi Kivity <avi@qumranet.com>
| hw/ppc4xx_devs.c | diffblobblamehistory |