| commit | 8a6d4ced4c0d17626c3875d5f8819efa3ac0f155 | |
| author | David Brownell <dbrownell@users.sourceforge.net> | |
| Wed, 18 Nov 2009 21:23:00 +0000 (18 13:23 -0800) | ||
| committer | David Brownell <dbrownell@users.sourceforge.net> | |
| Wed, 18 Nov 2009 21:23:00 +0000 (18 13:23 -0800) | ||
| tree | 03fec2659ca4d6611168ab8d6eb100019a3204d1 | treesnapshot (tar.gz zip) |
| parent | bbebfd9e134ec84a29dd68bc3661ead57435a4c3 | commitdiff |
ARM: setup "secure monitor mode" shadow regs
Teach the "armv4_5" register code to understand about the
secure monitor mode:
- Add the other three shadowed registers to the arrays
- Support another internal mode number (sigh) in mappings
- Catch malloc/calloc failures building that register cache
This should kick in for Cortex-A8 and ARM1176.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Teach the "armv4_5" register code to understand about the
secure monitor mode:
- Add the other three shadowed registers to the arrays
- Support another internal mode number (sigh) in mappings
- Catch malloc/calloc failures building that register cache
This should kick in for Cortex-A8 and ARM1176.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
| src/target/armv4_5.c | diffblobblamehistory | |
| src/target/armv4_5.h | diffblobblamehistory |