From 612184176fee6333e5372c4637e3cf54628ee416 Mon Sep 17 00:00:00 2001
From: David Brownell <dbrownell@users.sourceforge.net>
Date: Mon, 19 Jul 2010 16:08:09 -0400
Subject: [PATCH 01/16] more careful luminary init

Set up more of the Luminary-specific signals, and stop cloning
a few of the JTAG defaults.  More comments too.

Still leaves the "dap info 0" bugs unresolved (presumably coupled
to this particular adapter family) where TPIU, ITM, DWT, and other
debug modules wrongly display as extra NVICs.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
 src/jtag/drivers/ft2232.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/jtag/drivers/ft2232.c b/src/jtag/drivers/ft2232.c
index 4dcc045cc..1a0eb4b57 100644
--- a/src/jtag/drivers/ft2232.c
+++ b/src/jtag/drivers/ft2232.c
@@ -316,7 +316,7 @@ static uint8_t                  nSRSTnOE;
 /** the layout being used with this debug session */
 static const struct ft2232_layout *layout;
 
-/** default bitmask values ddriven on DBUS: TCK/TDI/TDO/TMS and GPIOL(0..4) */
+/** default bitmask values driven on DBUS: TCK/TDI/TDO/TMS and GPIOL(0..4) */
 static uint8_t                  low_output     = 0x0;
 
 /* note that direction bit == 1 means that signal is an output */
@@ -2496,9 +2496,11 @@ static int icdi_jtag_init(void)
 	/* Most Luminary eval boards support SWO trace output,
 	 * and should use this "luminary_icdi" layout.
 	 *
-	 * DBUS 0..3 are used for JTAG as usual.  GPIOs are used
+	 * ADBUS 0..3 are used for JTAG as usual.  GPIOs are used
 	 * to switch between JTAG and SWD, or switch the ft2232 UART
-	 * between (i) the target UART or (ii) SWO trace data.
+	 * on the second MPSSE channel/interface (BDBUS)
+	 * between (i) the stellaris UART (on Luminary boards)
+	 * or (ii) SWO trace data (generic).
 	 *
 	 * We come up in JTAG mode and may switch to SWD later (with
 	 * SWO/trace option if SWD is active).
@@ -2511,18 +2513,21 @@ static int icdi_jtag_init(void)
 #define ICDI_JTAG_EN (1 << 7)		/* ADBUS 7 (a.k.a. DBGMOD) */
 #define ICDI_DBG_ENn (1 << 6)		/* ADBUS 6 */
 #define ICDI_SRST (1 << 5)		/* ADBUS 5 */
-#define ICDI_TDI (1 << 2)		/* ADBUS 2 (INPUT) */
 
+
+	/* GPIOs on second channel/interface (UART) ... */
 #define ICDI_SWO_EN (1 << 4)		/* BDBUS 4 */
 #define ICDI_TX_SWO (1 << 1)	 	/* BDBUS 1 */
+#define ICDI_VCP_RX (1 << 0)	 	/* BDBUS 0 (to stellaris UART) */
 
 	nTRST = 0x0;
 	nTRSTnOE = 0x00;
 	nSRST = ICDI_SRST;
-	nSRSTnOE = 0x20;
+	nSRSTnOE = ICDI_SRST;
 
-	low_output    = 0x08 | ICDI_JTAG_EN;
-	low_direction = 0xcb | ICDI_JTAG_EN;
+	low_direction |= ICDI_JTAG_EN | ICDI_DBG_ENn;
+	low_output    |= ICDI_JTAG_EN;
+	low_output    &= ~ICDI_DBG_ENn;
 
 	return ftx232_dbus_write();
 }
-- 
2.11.4.GIT


From 70fee9207b5fd1c6f499b790591446adc4d4467c Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 08:45:45 +0200
Subject: [PATCH 02/16] arm: add error propagation to generic get_ttb fn
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm720t.c     | 16 ++++++++++++----
 src/target/arm920t.c     |  5 +++--
 src/target/arm920t.h     |  2 +-
 src/target/arm926ejs.c   |  6 ++++--
 src/target/armv4_5_mmu.c |  5 ++++-
 src/target/armv4_5_mmu.h |  2 +-
 src/target/cortex_a8.c   | 17 +++++++++++++----
 src/target/xscale.c      | 11 ++++++++---
 8 files changed, 46 insertions(+), 18 deletions(-)

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 0ea6cb2b0..b269f9488 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -134,16 +134,24 @@ static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t v
 	return ERROR_OK;
 }
 
-static uint32_t arm720t_get_ttb(struct target *target)
+static int arm720t_get_ttb(struct target *target, uint32_t *result)
 {
 	uint32_t ttb = 0x0;
 
-	arm720t_read_cp15(target, 0xee120f10, &ttb);
-	jtag_execute_queue();
+	int retval;
+
+	retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	ttb &= 0xffffc000;
 
-	return ttb;
+	*result = ttb;
+
+	return ERROR_OK;
 }
 
 static void arm720t_disable_mmu_caches(struct target *target,
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index fe9bba7e9..9c11d124f 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -318,7 +318,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
 }
 
 // EXPORTED to FA256
-uint32_t arm920t_get_ttb(struct target *target)
+int arm920t_get_ttb(struct target *target, uint32_t *result)
 {
 	int retval;
 	uint32_t ttb = 0x0;
@@ -328,7 +328,8 @@ uint32_t arm920t_get_ttb(struct target *target)
 			0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 		return retval;
 
-	return ttb;
+	*result = ttb;
+	return ERROR_OK;
 }
 
 // EXPORTED to FA256
diff --git a/src/target/arm920t.h b/src/target/arm920t.h
index a75f01ab1..9d5afab8f 100644
--- a/src/target/arm920t.h
+++ b/src/target/arm920t.h
@@ -66,7 +66,7 @@ int arm920t_write_memory(struct target *target,
 	uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 void arm920t_post_debug_entry(struct target *target);
 void arm920t_pre_restore_context(struct target *target);
-	uint32_t arm920t_get_ttb(struct target *target);
+int arm920t_get_ttb(struct target *target, uint32_t *result);
 void arm920t_disable_mmu_caches(struct target *target,
 	int mmu, int d_u_cache, int i_cache);
 void arm920t_enable_mmu_caches(struct target *target,
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d68e5ca34..0cf717356 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -323,7 +323,7 @@ static int arm926ejs_examine_debug_reason(struct target *target)
 	return ERROR_OK;
 }
 
-static uint32_t arm926ejs_get_ttb(struct target *target)
+static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	int retval;
@@ -332,7 +332,9 @@ static uint32_t arm926ejs_get_ttb(struct target *target)
 	if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
 		return retval;
 
-	return ttb;
+	*result = ttb;
+
+	return ERROR_OK;
 }
 
 static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 861410dd8..3d450ae13 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -30,8 +30,11 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
 {
 	uint32_t first_lvl_descriptor = 0x0;
 	uint32_t second_lvl_descriptor = 0x0;
-	uint32_t ttb = armv4_5_mmu->get_ttb(target);
+	uint32_t ttb;
 	int retval;
+	retval = armv4_5_mmu->get_ttb(target, &ttb);
+	if (retval != ERROR_OK)
+	  return retval;
 
 	retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
 		(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h
index 24f399342..d2716fb0f 100644
--- a/src/target/armv4_5_mmu.h
+++ b/src/target/armv4_5_mmu.h
@@ -26,7 +26,7 @@ struct target;
 
 struct armv4_5_mmu_common
 {
-	uint32_t (*get_ttb)(struct target *target);
+	int (*get_ttb)(struct target *target, uint32_t *result);
 	int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 	int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 	void (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index bd1401616..e1acbf74c 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -62,7 +62,7 @@ static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
                 int d_u_cache, int i_cache);
 static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
                 int d_u_cache, int i_cache);
-static uint32_t cortex_a8_get_ttb(struct target *target);
+static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
 
 
 /*
@@ -1853,8 +1853,7 @@ static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
 	return cortex_a8_init_arch_info(target, cortex_a8, target->tap);
 }
 
-/* FIX! error propagation missing from this fn */
-static uint32_t cortex_a8_get_ttb(struct target *target)
+static int cortex_a8_get_ttb(struct target *target, uint32_t *result)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
     struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1869,6 +1868,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
                     0, 1,   /* op1, op2 */
                     2, 0,   /* CRn, CRm */
                     &ttb);
+		if (retval != ERROR_OK)
+			return retval;
     }
     else if(cortex_a8->current_address_mode == ARM_MODE_USR)
     {
@@ -1877,6 +1878,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
                     0, 0,   /* op1, op2 */
                     2, 0,   /* CRn, CRm */
                     &ttb);
+		if (retval != ERROR_OK)
+			return retval;
     }
     /* we don't know whose address is: user or kernel
        we assume that if we are in kernel mode then
@@ -1889,6 +1892,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
                     0, 1,   /* op1, op2 */
                     2, 0,   /* CRn, CRm */
                     &ttb);
+		if (retval != ERROR_OK)
+			return retval;
     }
     else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR)
     {
@@ -1897,6 +1902,8 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
                     0, 0,   /* op1, op2 */
                     2, 0,   /* CRn, CRm */
                     &ttb);
+		if (retval != ERROR_OK)
+			return retval;
     }
     /* finally we don't know whose ttb to use: user or kernel */
     else
@@ -1904,7 +1911,9 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
 
     ttb &= 0xffffc000;
 
-    return ttb;
+    *result = ttb;
+
+    return ERROR_OK;
 }
 
 /* FIX! error propagation missing from this fn */
diff --git a/src/target/xscale.c b/src/target/xscale.c
index d5c212999..35efa8579 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2002,15 +2002,20 @@ static int xscale_bulk_write_memory(struct target *target, uint32_t address,
 	return xscale_write_memory(target, address, 4, count, buffer);
 }
 
-static uint32_t xscale_get_ttb(struct target *target)
+static int xscale_get_ttb(struct target *target, uint32_t *result)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t ttb;
+	int retval;
 
-	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
+	retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
+	if (retval != ERROR_OK)
+		return retval;
 	ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
 
-	return ttb;
+	*result = ttb;
+
+	return ERROR_OK;
 }
 
 static void xscale_disable_mmu_caches(struct target *target, int mmu,
-- 
2.11.4.GIT


From 6a237c23c1adb0be91a82a44d2cf13ff158b3ee2 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 10:58:07 +0200
Subject: [PATCH 03/16] arm: add error propagation for enable/disable mmu
 caches
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm720t.c     | 45 +++++++++++++++++++++++++++-----------
 src/target/arm920t.c     | 28 +++++++++++++++++-------
 src/target/arm920t.h     |  4 ++--
 src/target/arm926ejs.c   | 56 +++++++++++++++++++++++++++++++++++-------------
 src/target/armv4_5_mmu.c | 20 +++++++++++++----
 src/target/armv4_5_mmu.h |  4 ++--
 src/target/cortex_a8.c   | 26 +++++++++++++---------
 src/target/xscale.c      | 44 ++++++++++++++++++++++++++-----------
 8 files changed, 162 insertions(+), 65 deletions(-)

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index b269f9488..6bf38bbc7 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -154,14 +154,19 @@ static int arm720t_get_ttb(struct target *target, uint32_t *result)
 	return ERROR_OK;
 }
 
-static void arm720t_disable_mmu_caches(struct target *target,
+static int arm720t_disable_mmu_caches(struct target *target,
 		int mmu, int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control &= ~0x1U;
@@ -169,17 +174,23 @@ static void arm720t_disable_mmu_caches(struct target *target,
 	if (d_u_cache || i_cache)
 		cp15_control &= ~0x4U;
 
-	arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	return retval;
 }
 
-static void arm720t_enable_mmu_caches(struct target *target,
+static int arm720t_enable_mmu_caches(struct target *target,
 		int mmu, int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm720t_read_cp15(target, 0xee110f10, &cp15_control);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control |= 0x1U;
@@ -187,7 +198,8 @@ static void arm720t_enable_mmu_caches(struct target *target,
 	if (d_u_cache || i_cache)
 		cp15_control |= 0x4U;
 
-	arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
+	return retval;
 }
 
 static void arm720t_post_debug_entry(struct target *target)
@@ -282,12 +294,19 @@ static int arm720t_read_memory(struct target *target,
 
 	/* disable cache, but leave MMU enabled */
 	if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-		arm720t_disable_mmu_caches(target, 0, 1, 0);
-
+	{
+		retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 	retval = arm7_9_read_memory(target, address, size, count, buffer);
 
 	if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-		arm720t_enable_mmu_caches(target, 0, 1, 0);
+	{
+		retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	return retval;
 }
@@ -367,7 +386,9 @@ static int arm720t_soft_reset_halt(struct target *target)
 	armv4_5->pc->dirty = 1;
 	armv4_5->pc->valid = 1;
 
-	arm720t_disable_mmu_caches(target, 1, 1, 1);
+	retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
+	if (retval != ERROR_OK)
+		return retval;
 	arm720t->armv4_5_mmu.mmu_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 9c11d124f..a80a37810 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -333,14 +333,19 @@ int arm920t_get_ttb(struct target *target, uint32_t *result)
 }
 
 // EXPORTED to FA256
-void arm920t_disable_mmu_caches(struct target *target, int mmu,
+int arm920t_disable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-	jtag_execute_queue();
+	retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control &= ~0x1U;
@@ -351,18 +356,24 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu,
 	if (i_cache)
 		cp15_control &= ~0x1000U;
 
-	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+	retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+	return retval;
 }
 
 // EXPORTED to FA256
-void arm920t_enable_mmu_caches(struct target *target, int mmu,
+int arm920t_enable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
-	jtag_execute_queue();
+	retval = arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control |= 0x1U;
@@ -373,7 +384,8 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu,
 	if (i_cache)
 		cp15_control |= 0x1000U;
 
-	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+	retval = arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
+	return retval;
 }
 
 // EXPORTED to FA256
diff --git a/src/target/arm920t.h b/src/target/arm920t.h
index 9d5afab8f..20f614d7d 100644
--- a/src/target/arm920t.h
+++ b/src/target/arm920t.h
@@ -67,9 +67,9 @@ int arm920t_write_memory(struct target *target,
 void arm920t_post_debug_entry(struct target *target);
 void arm920t_pre_restore_context(struct target *target);
 int arm920t_get_ttb(struct target *target, uint32_t *result);
-void arm920t_disable_mmu_caches(struct target *target,
+int arm920t_disable_mmu_caches(struct target *target,
 	int mmu, int d_u_cache, int i_cache);
-void arm920t_enable_mmu_caches(struct target *target,
+int arm920t_enable_mmu_caches(struct target *target,
 	int mmu, int d_u_cache, int i_cache);
 
 extern const struct command_registration arm920t_command_handlers[];
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 0cf717356..f8a4f6294 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -337,20 +337,27 @@ static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
 	return ERROR_OK;
 }
 
-static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-	jtag_execute_queue();
+	retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 	{
 		/* invalidate TLB */
-		arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+		retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x1U;
 	}
@@ -360,17 +367,25 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
 		uint32_t debug_override;
 		/* read-modify-write CP15 debug override register
 		 * to enable "test and clean all" */
-		arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+		retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+		if (retval != ERROR_OK)
+			return retval;
 		debug_override |= 0x80000;
-		arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* clean and invalidate DCache */
-		arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* write CP15 debug override register
 		 * to disable "test and clean all" */
 		debug_override &= ~0x80000;
-		arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		if (retval != ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x4U;
 	}
@@ -378,23 +393,31 @@ static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
 	if (i_cache)
 	{
 		/* invalidate ICache */
-		arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x1000U;
 	}
 
-	arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	return retval;
 }
 
-static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-	jtag_execute_queue();
+	retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control |= 0x1U;
@@ -405,7 +428,8 @@ static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
 	if (i_cache)
 		cp15_control |= 0x1000U;
 
-	arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	return retval;
 }
 
 static void arm926ejs_post_debug_entry(struct target *target)
@@ -564,7 +588,9 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	armv4_5->pc->dirty = 1;
 	armv4_5->pc->valid = 1;
 
-	arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+	retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+	if (retval != ERROR_OK)
+		return retval;
 	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 3d450ae13..8978f354d 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -131,14 +131,20 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *
 		return ERROR_TARGET_NOT_HALTED;
 
 	/* disable MMU and data (or unified) cache */
-	armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* reenable MMU / cache */
-	armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+	retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 		armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 		armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	return retval;
 }
@@ -151,14 +157,20 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common
 		return ERROR_TARGET_NOT_HALTED;
 
 	/* disable MMU and data (or unified) cache */
-	armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* reenable MMU / cache */
-	armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+	retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
 		armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
 		armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	return retval;
 }
diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h
index d2716fb0f..f39834e27 100644
--- a/src/target/armv4_5_mmu.h
+++ b/src/target/armv4_5_mmu.h
@@ -29,8 +29,8 @@ struct armv4_5_mmu_common
 	int (*get_ttb)(struct target *target, uint32_t *result);
 	int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 	int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-	void (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
-	void (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
+	int (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
+	int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
 	struct armv4_5_cache_common armv4_5_cache;
 	int has_tiny_pages;
 	int mmu_enabled;
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index e1acbf74c..9a9018026 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -58,9 +58,9 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
 static int cortex_a8_mmu(struct target *target, int *enabled);
 static int cortex_a8_virt2phys(struct target *target,
                 uint32_t virt, uint32_t *phys);
-static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
                 int d_u_cache, int i_cache);
-static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
                 int d_u_cache, int i_cache);
 static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
 
@@ -1916,19 +1916,21 @@ static int cortex_a8_get_ttb(struct target *target, uint32_t *result)
     return ERROR_OK;
 }
 
-/* FIX! error propagation missing from this fn */
-static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
                 int d_u_cache, int i_cache)
 {
     struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
     struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
     uint32_t cp15_control;
+    int retval;
 
     /* read cp15 control register */
-    armv7a->armv4_5_common.mrc(target, 15,
+    retval = armv7a->armv4_5_common.mrc(target, 15,
                     0, 0,   /* op1, op2 */
                     1, 0,   /* CRn, CRm */
                     &cp15_control);
+    if (retval != ERROR_OK)
+    	return retval;
 
 
     if (mmu)
@@ -1940,25 +1942,28 @@ static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
     if (i_cache)
             cp15_control &= ~0x1000U;
 
-    armv7a->armv4_5_common.mcr(target, 15,
+    retval = armv7a->armv4_5_common.mcr(target, 15,
                     0, 0,   /* op1, op2 */
                     1, 0,   /* CRn, CRm */
                     cp15_control);
+	return retval;
 }
 
-/* FIX! error propagation missing from this fn */
-static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
                 int d_u_cache, int i_cache)
 {
     struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
     struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
     uint32_t cp15_control;
+    int retval;
 
     /* read cp15 control register */
-    armv7a->armv4_5_common.mrc(target, 15,
+    retval = armv7a->armv4_5_common.mrc(target, 15,
                     0, 0,   /* op1, op2 */
                     1, 0,   /* CRn, CRm */
                     &cp15_control);
+    if (retval != ERROR_OK)
+    	return retval;
 
     if (mmu)
             cp15_control |= 0x1U;
@@ -1969,10 +1974,11 @@ static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
     if (i_cache)
             cp15_control |= 0x1000U;
 
-    armv7a->armv4_5_common.mcr(target, 15,
+    retval = armv7a->armv4_5_common.mcr(target, 15,
                     0, 0,   /* op1, op2 */
                     1, 0,   /* CRn, CRm */
                     cp15_control);
+   	return retval;
 }
 
 
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 35efa8579..c0080b2b3 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2018,14 +2018,17 @@ static int xscale_get_ttb(struct target *target, uint32_t *result)
 	return ERROR_OK;
 }
 
-static void xscale_disable_mmu_caches(struct target *target, int mmu,
+static int xscale_disable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	if (retval !=ERROR_OK)
+		return retval;
 	cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 
 	if (mmu)
@@ -2034,11 +2037,17 @@ static void xscale_disable_mmu_caches(struct target *target, int mmu,
 	if (d_u_cache)
 	{
 		/* clean DCache */
-		xscale_send_u32(target, 0x50);
-		xscale_send_u32(target, xscale->cache_clean_address);
+		retval = xscale_send_u32(target, 0x50);
+		if (retval !=ERROR_OK)
+			return retval;
+		retval = xscale_send_u32(target, xscale->cache_clean_address);
+		if (retval !=ERROR_OK)
+			return retval;
 
 		/* invalidate DCache */
-		xscale_send_u32(target, 0x51);
+		retval = xscale_send_u32(target, 0x51);
+		if (retval !=ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x4U;
 	}
@@ -2046,25 +2055,33 @@ static void xscale_disable_mmu_caches(struct target *target, int mmu,
 	if (i_cache)
 	{
 		/* invalidate ICache */
-		xscale_send_u32(target, 0x52);
+		retval = xscale_send_u32(target, 0x52);
+		if (retval !=ERROR_OK)
+			return retval;
 		cp15_control &= ~0x1000U;
 	}
 
 	/* write new cp15 control register */
-	xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* execute cpwait to ensure outstanding operations complete */
-	xscale_send_u32(target, 0x53);
+	retval = xscale_send_u32(target, 0x53);
+	return retval;
 }
 
-static void xscale_enable_mmu_caches(struct target *target, int mmu,
+static int xscale_enable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
+	if (retval !=ERROR_OK)
+		return retval;
 	cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 
 	if (mmu)
@@ -2077,10 +2094,13 @@ static void xscale_enable_mmu_caches(struct target *target, int mmu,
 		cp15_control |= 0x1000U;
 
 	/* write new cp15 control register */
-	xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
+	if (retval !=ERROR_OK)
+		return retval;
 
 	/* execute cpwait to ensure outstanding operations complete */
-	xscale_send_u32(target, 0x53);
+	retval = xscale_send_u32(target, 0x53);
+	return retval;
 }
 
 static int xscale_set_breakpoint(struct target *target,
-- 
2.11.4.GIT


From 6c573df11d1c1bc76c897d0688adfd00ec56ca8e Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 12:17:11 +0200
Subject: [PATCH 04/16] cortex a8: added timeout handling
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/cortex_a8.c | 33 ++++++++++++++++++++++++++++-----
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 9a9018026..76c3d37b1 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -136,6 +136,7 @@ static int cortex_a8_exec_opcode(struct target *target,
 	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
 
 	/* Wait for InstrCompl bit to be set */
+	long long then = timeval_ms();
 	while ((dscr & DSCR_INSTR_COMP) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
@@ -145,12 +146,18 @@ static int cortex_a8_exec_opcode(struct target *target,
 			LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
 			return retval;
 		}
+		if (timeval_ms() > then + 1000)
+		{
+			LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+			return ERROR_FAIL;
+		}
 	}
 
 	retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
 	if (retval != ERROR_OK)
 		return retval;
 
+	then = timeval_ms();
 	do
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
@@ -160,6 +167,11 @@ static int cortex_a8_exec_opcode(struct target *target,
 			LOG_ERROR("Could not read DSCR register");
 			return retval;
 		}
+		if (timeval_ms() > then + 1000)
+		{
+			LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+			return ERROR_FAIL;
+		}
 	}
 	while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
 
@@ -248,12 +260,18 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 	}
 
 	/* Wait for DTRRXfull then read DTRRTX */
+	long long then = timeval_ms();
 	while ((dscr & DSCR_DTR_TX_FULL) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
+		if (timeval_ms() > then + 1000)
+		{
+			LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+			return ERROR_FAIL;
+		}
 	}
 
 	retval = mem_ap_read_atomic_u32(swjdp,
@@ -394,12 +412,18 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
 		dscr = *dscr_p;
 
 	/* Wait for DTRRXfull */
+	long long then = timeval_ms();
 	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
 		retval = mem_ap_read_atomic_u32(swjdp,
 				a8->armv7a_common.debug_base + CPUDBG_DSCR,
 				&dscr);
 		if (retval != ERROR_OK)
 			return retval;
+		if (timeval_ms() > then + 1000)
+		{
+			LOG_ERROR("Timeout waiting for read dcc");
+			return ERROR_FAIL;
+		}
 	}
 
 	retval = mem_ap_read_atomic_u32(swjdp,
@@ -1086,8 +1110,6 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	struct reg *r;
 	int retval;
 
-	int timeout = 100;
-
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
@@ -1132,12 +1154,13 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	if (retval != ERROR_OK)
 		return retval;
 
+	long long then = timeval_ms();
 	while (target->state != TARGET_HALTED)
 	{
 		retval = cortex_a8_poll(target);
 		if (retval != ERROR_OK)
 			return retval;
-		if (--timeout == 0)
+		if (timeval_ms() > then + 1000)
 		{
 			LOG_ERROR("timeout waiting for target halt");
 			return ERROR_FAIL;
@@ -1145,8 +1168,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	}
 
 	cortex_a8_unset_breakpoint(target, &stepbreakpoint);
-	if (timeout > 0)
-		target->debug_reason = DBG_REASON_BREAKPOINT;
+
+	target->debug_reason = DBG_REASON_BREAKPOINT;
 
 	if (breakpoint)
 		cortex_a8_set_breakpoint(target, breakpoint, 0);
-- 
2.11.4.GIT


From 44ef0327dd97c1893afc63cd7fd8025cb1b57827 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 12:34:54 +0200
Subject: [PATCH 05/16] debug: debug entry error propagation
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm11.c         |  2 +-
 src/target/arm720t.c       | 22 +++++++++++++++------
 src/target/arm7_9_common.c | 14 +++++++++++---
 src/target/arm7_9_common.h |  2 +-
 src/target/arm920t.c       | 48 ++++++++++++++++++++++++++++++++++------------
 src/target/arm920t.h       |  2 +-
 src/target/arm926ejs.c     | 38 ++++++++++++++++++++++++++----------
 src/target/armv7a.h        |  2 +-
 src/target/armv7m.h        |  2 +-
 src/target/cortex_a8.c     | 14 +++++++++++---
 src/target/cortex_m3.c     | 11 +++++++++--
 11 files changed, 116 insertions(+), 41 deletions(-)

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 36bbaba12..67f0524e2 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -439,7 +439,7 @@ static int arm11_halt(struct target *target)
 
 	enum target_state old_state	= target->state;
 
-	arm11_debug_entry(arm11);
+	CHECK_RETVAL(arm11_debug_entry(arm11));
 
 	CHECK_RETVAL(
 		target_call_event_callbacks(target,
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 6bf38bbc7..96e0baaf5 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -202,13 +202,18 @@ static int arm720t_enable_mmu_caches(struct target *target,
 	return retval;
 }
 
-static void arm720t_post_debug_entry(struct target *target)
+static int arm720t_post_debug_entry(struct target *target)
 {
 	struct arm720t_common *arm720t = target_to_arm720(target);
+	int retval;
 
 	/* examine cp15 control reg */
-	arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
 	arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
@@ -216,9 +221,14 @@ static void arm720t_post_debug_entry(struct target *target)
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
 	/* save i/d fault status and address register */
-	arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
-	arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
-	jtag_execute_queue();
+	retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	return retval;
 }
 
 static void arm720t_pre_restore_context(struct target *target)
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index abe0c2f13..b742daeb3 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1470,7 +1470,11 @@ static int arm7_9_debug_entry(struct target *target)
 		return retval;
 
 	if (arm7_9->post_debug_entry)
-		arm7_9->post_debug_entry(target);
+	{
+		retval = arm7_9->post_debug_entry(target);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	return ERROR_OK;
 }
@@ -1878,7 +1882,9 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
 				return err;
 			}
 
-			arm7_9_debug_entry(target);
+			retval = arm7_9_debug_entry(target);
+			if (retval != ERROR_OK)
+				return retval;
 			LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
 					buf_get_u32(armv4_5->pc->value, 0, 32));
 
@@ -2079,7 +2085,9 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 	{
 		target->state = TARGET_UNKNOWN;
 	} else {
-		arm7_9_debug_entry(target);
+		retval = arm7_9_debug_entry(target);
+		if (retval != ERROR_OK)
+			return retval;
 		if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 		{
 			return retval;
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index a741c5900..69ea22187 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -100,7 +100,7 @@ struct arm7_9_common
 
 	void (*set_special_dbgrq)(struct target *target); /**< Function for setting DBGRQ if the normal way won't work */
 
-	void (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */
+	int (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */
 
 	void (*pre_restore_context)(struct target *target); /**< Callback function called before restoring the processor context */
 };
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index a80a37810..7627b25e8 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -389,24 +389,33 @@ int arm920t_enable_mmu_caches(struct target *target, int mmu,
 }
 
 // EXPORTED to FA256
-void arm920t_post_debug_entry(struct target *target)
+int arm920t_post_debug_entry(struct target *target)
 {
 	uint32_t cp15c15;
 	struct arm920t_common *arm920t = target_to_arm920(target);
+	int retval;
 
 	/* examine cp15 control reg */
-	arm920t_read_cp15_physical(target,
+	retval = arm920t_read_cp15_physical(target,
 			CP15PHYS_CTRL, &arm920t->cp15_control_reg);
-	jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
 
 	if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
 		uint32_t cache_type_reg;
 		/* identify caches */
-		arm920t_read_cp15_physical(target,
+		retval = arm920t_read_cp15_physical(target,
 				CP15PHYS_CACHETYPE, &cache_type_reg);
-		jtag_execute_queue();
+		if (retval != ERROR_OK)
+			return retval;
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
+			return retval;
 		armv4_5_identify_cache(cache_type_reg,
 				&arm920t->armv4_5_mmu.armv4_5_cache);
 	}
@@ -420,10 +429,18 @@ void arm920t_post_debug_entry(struct target *target)
 
 	/* save i/d fault status and address register */
 			/* FIXME use opcode macros */
-	arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
-	arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
-	arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
-	arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+	retval = arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
+	if (retval != ERROR_OK)
+		return retval;
 
 	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
 		", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32,
@@ -433,13 +450,20 @@ void arm920t_post_debug_entry(struct target *target)
 	{
 		/* read-modify-write CP15 test state register
 		 * to disable I/D-cache linefills */
-		arm920t_read_cp15_physical(target,
+		retval = arm920t_read_cp15_physical(target,
 				CP15PHYS_TESTSTATE, &cp15c15);
-		jtag_execute_queue();
+		if (retval != ERROR_OK)
+			return retval;
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
+			return retval;
 		cp15c15 |= 0x600;
-		arm920t_write_cp15_physical(target,
+		retval = arm920t_write_cp15_physical(target,
 				CP15PHYS_TESTSTATE, cp15c15);
+		if (retval != ERROR_OK)
+			return retval;
 	}
+	return ERROR_OK;
 }
 
 // EXPORTED to FA256
diff --git a/src/target/arm920t.h b/src/target/arm920t.h
index 20f614d7d..02d7f83a9 100644
--- a/src/target/arm920t.h
+++ b/src/target/arm920t.h
@@ -64,7 +64,7 @@ int arm920t_read_memory(struct target *target,
 	uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 int arm920t_write_memory(struct target *target,
 	uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-void arm920t_post_debug_entry(struct target *target);
+int arm920t_post_debug_entry(struct target *target);
 void arm920t_pre_restore_context(struct target *target);
 int arm920t_get_ttb(struct target *target, uint32_t *result);
 int arm920t_disable_mmu_caches(struct target *target,
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index f8a4f6294..aa38d27f8 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -432,21 +432,30 @@ static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
 	return retval;
 }
 
-static void arm926ejs_post_debug_entry(struct target *target)
+static int arm926ejs_post_debug_entry(struct target *target)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
+	int retval;
 
 	/* examine cp15 control reg */
-	arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
-	jtag_execute_queue();
+	retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
 	if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
 		uint32_t cache_type_reg;
 		/* identify caches */
-		arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
-		jtag_execute_queue();
+		retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
+			return retval;
 		armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 	}
 
@@ -455,9 +464,15 @@ static void arm926ejs_post_debug_entry(struct target *target)
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
 	/* save i/d fault status and address register */
-	arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
-	arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
-	arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+	retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+	if (retval != ERROR_OK)
+		return retval;
 
 	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
 		arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
@@ -466,9 +481,12 @@ static void arm926ejs_post_debug_entry(struct target *target)
 
 	/* read-modify-write CP15 cache debug control register
 	 * to disable I/D-cache linefills and force WT */
-	arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+	retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+	if (retval != ERROR_OK)
+		return retval;
 	cache_dbg_ctrl |= 0x7;
-	arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+	retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+	return retval;
 }
 
 static void arm926ejs_pre_restore_context(struct target *target)
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 621761d73..f93245634 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -62,7 +62,7 @@ struct armv7a_common
 	struct armv4_5_mmu_common armv4_5_mmu;
 
 	int (*examine_debug_reason)(struct target *target);
-	void (*post_debug_entry)(struct target *target);
+	int (*post_debug_entry)(struct target *target);
 
 	void (*pre_restore_context)(struct target *target);
 };
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 57d46ede4..8ef380088 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -121,7 +121,7 @@ struct armv7m_common
 	int (*write_core_reg)(struct target *target, unsigned num);
 
 	int (*examine_debug_reason)(struct target *target);
-	void (*post_debug_entry)(struct target *target);
+	int (*post_debug_entry)(struct target *target);
 
 	void (*pre_restore_context)(struct target *target);
 };
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 76c3d37b1..9b3521ac5 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1056,12 +1056,16 @@ static int cortex_a8_debug_entry(struct target *target)
 	/* Are we in an exception handler */
 //	armv4_5->exception_number = 0;
 	if (armv7a->post_debug_entry)
-		armv7a->post_debug_entry(target);
+	{
+		retval = armv7a->post_debug_entry(target);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	return retval;
 }
 
-static void cortex_a8_post_debug_entry(struct target *target)
+static int cortex_a8_post_debug_entry(struct target *target)
 {
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 	struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
@@ -1072,6 +1076,8 @@ static void cortex_a8_post_debug_entry(struct target *target)
 			0, 0,	/* op1, op2 */
 			1, 0,	/* CRn, CRm */
 			&cortex_a8->cp15_control_reg);
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
 
 	if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
@@ -1083,6 +1089,8 @@ static void cortex_a8_post_debug_entry(struct target *target)
 				0, 1,	/* op1, op2 */
 				0, 0,	/* CRn, CRm */
 				&cache_type_reg);
+		if (retval != ERROR_OK)
+			return retval;
 		LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
 
 		/* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
@@ -1097,7 +1105,7 @@ static void cortex_a8_post_debug_entry(struct target *target)
 	armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
 			(cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
 
-
+	return ERROR_OK;
 }
 
 static int cortex_a8_step(struct target *target, int current, uint32_t address,
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 7f6cbafa5..4f3560f76 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -442,7 +442,11 @@ static int cortex_m3_debug_entry(struct target *target)
 		target_state_name(target));
 
 	if (armv7m->post_debug_entry)
-		armv7m->post_debug_entry(target);
+	{
+		retval = armv7m->post_debug_entry(target);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	return ERROR_OK;
 }
@@ -813,7 +817,10 @@ static int cortex_m3_step(struct target *target, int current,
 			" nvic_icsr = 0x%" PRIx32,
 			cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 
-	cortex_m3_debug_entry(target);
+	int retval;
+	retval = cortex_m3_debug_entry(target);
+	if (retval != ERROR_OK)
+		return retval;
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
 	LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
-- 
2.11.4.GIT


From e7a1ec64bface364305e9c355811838e9f310bf3 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 13:45:53 +0200
Subject: [PATCH 06/16] arm_adi_v5: add error propagation for
 dap_setup_accessport
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm_adi_v5.c | 44 +++++++++++++++++++++++++++++++++-----------
 src/target/cortex_m3.c  | 16 ++++++++++++----
 2 files changed, 45 insertions(+), 15 deletions(-)

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index dfb45b496..9a33d8201 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -5,7 +5,7 @@
  *   Copyright (C) 2008 by Spencer Oliver                                  *
  *   spen@spen-soft.co.uk                                                  *
  *                                                                         *
- *   Copyright (C) 2009 by Oyvind Harboe                                   *
+ *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2009-2010 by David Brownell                             *
@@ -309,7 +309,9 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
 		if (blocksize == 0)
 			blocksize = 1;
 
-		dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+		if (retval != ERROR_OK)
+			return retval;
 
 		for (writecount = 0; writecount < blocksize; writecount++)
 		{
@@ -363,7 +365,9 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 		if (blocksize == 0)
 			blocksize = 1;
 
-		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+		retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+		if (retval != ERROR_OK)
+			return retval;
 		writecount = blocksize;
 
 		do
@@ -430,7 +434,9 @@ int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
 
 	while (count > 0)
 	{
-		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		if (retval != ERROR_OK)
+			return retval;
 		uint16_t svalue;
 		memcpy(&svalue, buffer, sizeof(uint16_t));
 		uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
@@ -468,7 +474,9 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 		if (wcount < blocksize)
 			blocksize = wcount;
 
-		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		if (retval != ERROR_OK)
+			return retval;
 		writecount = blocksize;
 
 		do
@@ -534,7 +542,9 @@ int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint3
 
 	while (count > 0)
 	{
-		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		if (retval != ERROR_OK)
+			return retval;
 		uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 		retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 		if (retval != ERROR_OK)
@@ -592,8 +602,10 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 		if (blocksize == 0)
 			blocksize = 1;
 
-		dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
+		retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 				address);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* FIXME remove these three calls to adi_jtag_dp_scan(),
 		 * so this routine becomes transport-neutral.  Be careful
@@ -686,7 +698,9 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 		if (wcount < blocksize)
 			blocksize = wcount;
 
-		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+		retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* handle unaligned data at 4k boundary */
 		if (blocksize == 0)
@@ -739,7 +753,9 @@ int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 
 	while (count > 0)
 	{
-		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 		if (retval != ERROR_OK)
 			break;
@@ -795,7 +811,9 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 		if (wcount < blocksize)
 			blocksize = wcount;
 
-		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		if (retval != ERROR_OK)
+			return retval;
 		readcount = blocksize;
 
 		do
@@ -844,8 +862,12 @@ int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 
 	while (count > 0)
 	{
-		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dap_run(dap);
 		if (retval != ERROR_OK)
 			break;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 4f3560f76..d6090f55b 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -71,13 +71,17 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
 	mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 
 	/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
-	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
 	if (retval != ERROR_OK)
 		return retval;
 
 	/* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
-	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 	if (retval != ERROR_OK)
 		return retval;
@@ -106,12 +110,16 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
 	mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 
 	/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
-	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 	// XXX check retval
 
 	/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
-	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 	// XXX check retval
 
-- 
2.11.4.GIT


From 7dcde11b459f60d40db9ca53f038cd200c852064 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 13:50:28 +0200
Subject: [PATCH 07/16] mem_ap_read_u32 error propagation
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm_adi_v5.c | 20 +++++++++++++++-----
 src/target/cortex_m3.c  | 44 +++++++++++++++++++++++++++++++++-----------
 2 files changed, 48 insertions(+), 16 deletions(-)

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 9a33d8201..496360f73 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1088,11 +1088,21 @@ static int dap_info_command(struct command_context *cmd_ctx,
 			command_print(cmd_ctx, "\tROM table in legacy format");
 
 		/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
-		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
-		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
-		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
-		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
-		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+		retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = dap_run(dap);
 		if (retval != ERROR_OK)
 			return retval;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index d6090f55b..693989046 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -68,7 +68,9 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
 	/* because the DCB_DCRDR is used for the emulated dcc channel
 	 * we have to save/restore the DCB_DCRDR when used */
 
-	mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+	retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
 	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
@@ -107,7 +109,9 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
 	/* because the DCB_DCRDR is used for the emulated dcc channel
 	 * we have to save/restore the DCB_DCRDR when used */
 
-	mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+	retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
@@ -297,33 +301,51 @@ static int cortex_m3_examine_exception_reason(struct target *target)
 	struct adiv5_dap *swjdp = &armv7m->dap;
 	int retval;
 
-	mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+	retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+	if (retval != ERROR_OK)
+		return retval;
 	switch (armv7m->exception_number)
 	{
 		case 2:	/* NMI */
 			break;
 		case 3:	/* Hard Fault */
-			mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+			retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
 			if (except_sr & 0x40000000)
 			{
-				mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+				retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+				if (retval != ERROR_OK)
+					return retval;
 			}
 			break;
 		case 4:	/* Memory Management */
-			mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
-			mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+			retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
+			retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+			if (retval != ERROR_OK)
+				return retval;
 			break;
 		case 5:	/* Bus Fault */
-			mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
-			mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+			retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
+			retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+			if (retval != ERROR_OK)
+				return retval;
 			break;
 		case 6:	/* Usage Fault */
-			mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+			retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
 			break;
 		case 11:	/* SVCall */
 			break;
 		case 12:	/* Debug Monitor */
-			mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+			retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
 			break;
 		case 14:	/* PendSV */
 			break;
-- 
2.11.4.GIT


From a7315891eff5ed84dbd88e950321c6ff2a58e867 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 13:56:59 +0200
Subject: [PATCH 08/16] arm_adi_v5: error propagation of mem_ap_read_atomic_u32
 failure
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm_adi_v5.c | 44 +++++++++++++++++++++++++++++----------
 src/target/cortex_m3.c  | 55 +++++++++++++++++++++++++++++++++++--------------
 2 files changed, 73 insertions(+), 26 deletions(-)

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 496360f73..194865e42 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1124,7 +1124,9 @@ static int dap_info_command(struct command_context *cmd_ctx,
 		entry_offset = 0;
 		do
 		{
-			mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+			retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+			if (retval != ERROR_OK)
+				return retval;
 			command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
 			if (romentry&0x01)
 			{
@@ -1140,33 +1142,51 @@ static int dap_info_command(struct command_context *cmd_ctx,
 				/* IDs are in last 4K section */
 
 
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFE0, &c_pid0);
+				if (retval != ERROR_OK)
+					return retval;
 				c_pid0 &= 0xff;
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFE4, &c_pid1);
+				if (retval != ERROR_OK)
+					return retval;
 				c_pid1 &= 0xff;
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFE8, &c_pid2);
+				if (retval != ERROR_OK)
+					return retval;
 				c_pid2 &= 0xff;
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFEC, &c_pid3);
+				if (retval != ERROR_OK)
+					return retval;
 				c_pid3 &= 0xff;
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFD0, &c_pid4);
+				if (retval != ERROR_OK)
+					return retval;
 				c_pid4 &= 0xff;
 
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFF0, &c_cid0);
+				if (retval != ERROR_OK)
+					return retval;
 				c_cid0 &= 0xff;
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFF4, &c_cid1);
+				if (retval != ERROR_OK)
+					return retval;
 				c_cid1 &= 0xff;
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFF8, &c_cid2);
+				if (retval != ERROR_OK)
+					return retval;
 				c_cid2 &= 0xff;
-				mem_ap_read_atomic_u32(dap,
+				retval = mem_ap_read_atomic_u32(dap,
 					component_base + 0xFFC, &c_cid3);
+				if (retval != ERROR_OK)
+					return retval;
 				c_cid3 &= 0xff;
 
 
@@ -1187,9 +1207,11 @@ static int dap_info_command(struct command_context *cmd_ctx,
 					unsigned minor;
 					char *major = "Reserved", *subtype = "Reserved";
 
-					mem_ap_read_atomic_u32(dap,
+					retval = mem_ap_read_atomic_u32(dap,
 							(component_base & 0xfffff000) | 0xfcc,
 							&devtype);
+					if (retval != ERROR_OK)
+						return retval;
 					minor = (devtype >> 4) & 0x0f;
 					switch (devtype & 0x0f) {
 					case 0:
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 693989046..7bdf7d59a 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -155,12 +155,15 @@ static int cortex_m3_clear_halt(struct target *target)
 {
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	int retval;
 
 	/* clear step if any */
 	cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 
 	/* Read Debug Fault Status Register */
-	mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+	retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Clear Debug Fault Status */
 	mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
@@ -208,14 +211,18 @@ static int cortex_m3_endreset_event(struct target *target)
 	struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 
 	/* REVISIT The four debug monitor bits are currently ignored... */
-	mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+	retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 
 	/* this register is used for emulated dcc channel */
 	mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 
 	/* Enable debug requests */
-	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	if (retval != ERROR_OK)
+		return retval;
 	if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 		mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 
@@ -262,7 +269,7 @@ static int cortex_m3_endreset_event(struct target *target)
 	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
 	/* make sure we have latest dhcsr flags */
-	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
 	return retval;
 }
@@ -396,7 +403,9 @@ static int cortex_m3_debug_entry(struct target *target)
 	LOG_DEBUG(" ");
 
 	cortex_m3_clear_halt(target);
-	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 		return retval;
@@ -508,13 +517,17 @@ static int cortex_m3_poll(struct target *target)
 		target->debug_reason = DBG_REASON_DBGRQ;
 
 		/* refresh status bits */
-		mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+		retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 
 	if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 	{
 		/* check if still in reset */
-		mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+		retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+		if (retval != ERROR_OK)
+			return retval;
 
 		if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 		{
@@ -642,8 +655,10 @@ static int cortex_m3_soft_reset_halt(struct target *target)
 		retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 		if (retval == ERROR_OK)
 		{
-			mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
+			retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 					&cortex_m3->nvic_dfsr);
+			if (retval != ERROR_OK)
+				return retval;
 			if ((dcb_dhcsr & S_HALT)
 					&& (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 			{
@@ -835,7 +850,10 @@ static int cortex_m3_step(struct target *target, int current,
 		cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 	}
 
-	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	int retval;
+	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* registers are now invalid */
 	register_cache_invalidate(cortex_m3->armv7m.core_cache);
@@ -847,7 +865,6 @@ static int cortex_m3_step(struct target *target, int current,
 			" nvic_icsr = 0x%" PRIx32,
 			cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 
-	int retval;
 	retval = cortex_m3_debug_entry(target);
 	if (retval != ERROR_OK)
 		return retval;
@@ -880,7 +897,10 @@ static int cortex_m3_assert_reset(struct target *target)
 		assert_srst = 0;
 
 	/* Enable debug requests */
-	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	int retval;
+	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	if (retval != ERROR_OK)
+		return retval;
 	if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 		mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 
@@ -982,7 +1002,9 @@ static int cortex_m3_assert_reset(struct target *target)
 			 * after reset) on LM3S6918 -- Michael Schwingen
 			 */
 			uint32_t tmp;
-			mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+			retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+			if (retval != ERROR_OK)
+				return retval;
 		}
 	}
 
@@ -993,7 +1015,6 @@ static int cortex_m3_assert_reset(struct target *target)
 
 	if (target->reset_halt)
 	{
-		int retval;
 		if ((retval = target_halt(target)) != ERROR_OK)
 			return retval;
 	}
@@ -1982,7 +2003,9 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+	retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (CMD_ARGC > 0) {
 		unsigned catch = 0;
@@ -2019,7 +2042,9 @@ write:
 
 		/* write, but don't assume it stuck (why not??) */
 		mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
-		mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+		retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* FIXME be sure to clear DEMCR on clean server shutdown.
 		 * Otherwise the vector catch hardware could fire when there's
-- 
2.11.4.GIT


From b62c8d600995638081f9a34c358db58337df7bdb Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 14:03:33 +0200
Subject: [PATCH 09/16] arm_adi_v5: mem_ap_write error propagation
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm_adi_v5.c | 12 ++++---
 src/target/cortex_m3.c  | 91 ++++++++++++++++++++++++++++++++++++++-----------
 2 files changed, 78 insertions(+), 25 deletions(-)

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 194865e42..39d8bde90 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -376,13 +376,14 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 
 			if (nbytes < 4)
 			{
-				if (mem_ap_write_buf_u16(dap, buffer,
-						nbytes, address) != ERROR_OK)
+				retval = mem_ap_write_buf_u16(dap, buffer,
+						nbytes, address);
+				if (retval != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
 						"0x%" PRIx32 ", count 0x%x",
 						address, count);
-					return ERROR_JTAG_DEVICE_ERROR;
+					return retval;
 				}
 
 				address += nbytes >> 1;
@@ -485,12 +486,13 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 
 			if (nbytes < 4)
 			{
-				if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
+				retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
+				if (retval != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
 						"0x%" PRIx32 ", count 0x%x",
 						address, count);
-					return ERROR_JTAG_DEVICE_ERROR;
+					return retval;
 				}
 
 				address += nbytes;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 7bdf7d59a..2a58f5bf0 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -166,7 +166,9 @@ static int cortex_m3_clear_halt(struct target *target)
 		return retval;
 
 	/* Clear Debug Fault Status */
-	mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+	retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 
 	return ERROR_OK;
@@ -177,6 +179,7 @@ static int cortex_m3_single_step_core(struct target *target)
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 	uint32_t dhcsr_save;
+	int retval;
 
 	/* backup dhcsr reg */
 	dhcsr_save = cortex_m3->dcb_dhcsr;
@@ -186,10 +189,16 @@ static int cortex_m3_single_step_core(struct target *target)
 	 * HALT can put the core into an unknown state.
 	 */
 	if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
-		mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+	{
+		retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 				DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
-	mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+		if (retval != ERROR_OK)
+			return retval;
+	}
+	retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 				DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG(" ");
 
 	/* restore dhcsr reg */
@@ -217,14 +226,20 @@ static int cortex_m3_endreset_event(struct target *target)
 	LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 
 	/* this register is used for emulated dcc channel */
-	mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+	retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Enable debug requests */
 	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 	if (retval != ERROR_OK)
 		return retval;
 	if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
-		mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+	{
+		retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	/* clear any interrupt masking */
 	cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
@@ -236,31 +251,44 @@ static int cortex_m3_endreset_event(struct target *target)
 	 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 	 * or manual updates to the NVIC SHCSR and CCR registers.
 	 */
-	mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
+	retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Paranoia: evidently some (early?) chips don't preserve all the
 	 * debug state (including FBP, DWT, etc) across reset...
 	 */
 
 	/* Enable FPB */
-	target_write_u32(target, FP_CTRL, 3);
+	retval = target_write_u32(target, FP_CTRL, 3);
+	if (retval != ERROR_OK)
+		return retval;
+
 	cortex_m3->fpb_enabled = 1;
 
 	/* Restore FPB registers */
 	for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 	{
-		target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
+		retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 
 	/* Restore DWT registers */
 	for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 	{
-		target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
+		retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 				dwt_list[i].comp);
-		target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 				dwt_list[i].mask);
-		target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 				dwt_list[i].function);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 	retval = dap_run(swjdp);
 	if (retval != ERROR_OK)
@@ -639,12 +667,16 @@ static int cortex_m3_soft_reset_halt(struct target *target)
 	int retval, timeout = 0;
 
 	/* Enter debug state on reset; restore DEMCR in endreset_event() */
-	mem_ap_write_u32(swjdp, DCB_DEMCR,
+	retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
 			TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Request a core-only reset */
-	mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+	retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 			AIRCR_VECTKEY | AIRCR_VECTRESET);
+	if (retval != ERROR_OK)
+		return retval;
 	target->state = TARGET_RESET;
 
 	/* registers are now invalid */
@@ -902,16 +934,26 @@ static int cortex_m3_assert_reset(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 	if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
-		mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+	{
+		retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
-	mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+	retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (!target->reset_halt)
 	{
 		/* Set/Clear C_MASKINTS in a separate operation */
 		if (cortex_m3->dcb_dhcsr & C_MASKINTS)
-			mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+		{
+			retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 					DBGKEY | C_DEBUGEN | C_HALT);
+			if (retval != ERROR_OK)
+				return retval;
+		}
 
 		/* clear any debug flags before resuming */
 		cortex_m3_clear_halt(target);
@@ -927,8 +969,10 @@ static int cortex_m3_assert_reset(struct target *target)
 		 * bad vector table entries.  Should this include MMERR or
 		 * other flags too?
 		 */
-		mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
+		retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 				TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 
 	/*
@@ -992,8 +1036,10 @@ static int cortex_m3_assert_reset(struct target *target)
 		 * core, like watchdog timers, if the SoC wires it up
 		 * correctly.  Else VECRESET can reset just the core.
 		 */
-		mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+		retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 				AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+		if (retval != ERROR_OK)
+			return retval;
 		LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 
 		{
@@ -1834,6 +1880,7 @@ static int cortex_m3_examine(struct target *target)
 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
 {
 	uint16_t dcrdr;
+	int retval;
 
 	mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
 	*ctrl = (uint8_t)dcrdr;
@@ -1846,7 +1893,9 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *
 	if (dcrdr & (1 << 0))
 	{
 		dcrdr = 0;
-		mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+		retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 
 	return ERROR_OK;
@@ -2041,7 +2090,9 @@ write:
 		demcr |= catch;
 
 		/* write, but don't assume it stuck (why not??) */
-		mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+		retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+		if (retval != ERROR_OK)
+			return retval;
 		retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
 		if (retval != ERROR_OK)
 			return retval;
-- 
2.11.4.GIT


From 5164fe55639877be4dd6a7c0a504aa1bc279d64d Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 14:22:35 +0200
Subject: [PATCH 10/16] arm_adi_v5: dap_run() error propagation
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm_adi_v5.c | 43 ++++++++++++++++++++++++++++---------------
 1 file changed, 28 insertions(+), 15 deletions(-)

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 39d8bde90..b26175b30 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -321,7 +321,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
 				break;
 		}
 
-		if (dap_run(dap) == ERROR_OK)
+		if ((retval = dap_run(dap)) == ERROR_OK)
 		{
 			wcount = wcount - blocksize;
 			address = address + 4 * blocksize;
@@ -335,8 +335,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint
 		if (errorcount > 1)
 		{
 			LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
-			/* REVISIT return the *actual* fault code */
-			return ERROR_JTAG_DEVICE_ERROR;
+			return retval;
 		}
 	}
 
@@ -406,13 +405,12 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 				if (retval != ERROR_OK)
 					break;
 
-				if (dap_run(dap) != ERROR_OK)
+				if ((retval = dap_run(dap)) != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
 						"0x%" PRIx32 ", count 0x%x",
 						address, count);
-					/* REVISIT return *actual* fault code */
-					return ERROR_JTAG_DEVICE_ERROR;
+					return retval;
 				}
 			}
 
@@ -515,13 +513,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 				if (retval != ERROR_OK)
 					break;
 
-				if (dap_run(dap) != ERROR_OK)
+				if ((retval = dap_run(dap)) != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
 						"0x%" PRIx32 ", count 0x%x",
 						address, count);
-					/* REVISIT return *actual* fault code */
-					return ERROR_JTAG_DEVICE_ERROR;
+					return retval;
 				}
 			}
 
@@ -712,11 +709,12 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 		do
 		{
 			retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
-			if (dap_run(dap) != ERROR_OK)
+			if (retval != ERROR_OK)
+				return retval;
+			if ((retval = dap_run(dap)) != ERROR_OK)
 			{
 				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
-				/* REVISIT return the *actual* fault code */
-				return ERROR_JTAG_DEVICE_ERROR;
+				return retval;
 			}
 
 			nbytes = MIN((readcount << 1), 4);
@@ -821,11 +819,12 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 		do
 		{
 			retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
-			if (dap_run(dap) != ERROR_OK)
+			if (retval != ERROR_OK)
+				return retval;
+			if ((retval = dap_run(dap)) != ERROR_OK)
 			{
 				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
-				/* REVISIT return the *actual* fault code */
-				return ERROR_JTAG_DEVICE_ERROR;
+				return retval;
 			}
 
 			nbytes = MIN(readcount, 4);
@@ -993,7 +992,11 @@ int ahbap_debugport_init(struct adiv5_dap *dap)
 	 * place to scan the table and do any topology detection?
 	 */
 	retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if ((retval = dap_run(dap)) != ERROR_OK)
 		return retval;
@@ -1039,7 +1042,11 @@ static int dap_info_command(struct command_context *cmd_ctx,
 	apselold = dap->apsel;
 	dap_ap_select(dap, apsel);
 	retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_run(dap);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1490,6 +1497,8 @@ COMMAND_HANDLER(dap_baseaddr_command)
 	 * use the ID register to verify it's a MEM-AP.
 	 */
 	retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_run(dap);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1553,6 +1562,8 @@ COMMAND_HANDLER(dap_apsel_command)
 
 	dap_ap_select(dap, apsel);
 	retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_run(dap);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1591,6 +1602,8 @@ COMMAND_HANDLER(dap_apid_command)
 		dap_ap_select(dap, apsel);
 
 	retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = dap_run(dap);
 	if (retval != ERROR_OK)
 		return retval;
-- 
2.11.4.GIT


From 4333840ee3d6d79299bf90b719a3c1628c688690 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 14:37:45 +0200
Subject: [PATCH 11/16] arm: error propagation of arm_jtag_set_instr
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/adi_v5_jtag.c   |  5 ++++-
 src/target/arm7_9_common.c | 27 +++++++++++++++++++++------
 src/target/arm7tdmi.c      | 17 +++++++++++++----
 src/target/arm920t.c       | 14 +++++++++++---
 src/target/arm926ejs.c     | 16 ++++++++++++----
 src/target/arm966e.c       |  8 ++++++--
 src/target/arm9tdmi.c      | 16 ++++++++++++----
 src/target/embeddedice.c   | 22 +++++++++++++++++-----
 src/target/etm.c           | 10 ++++++++--
 src/target/feroceon.c      |  5 ++++-
 10 files changed, 108 insertions(+), 32 deletions(-)

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 0a374bea8..185bd5437 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -86,8 +86,11 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
 	struct arm_jtag *jtag_info = dap->jtag_info;
 	struct scan_field fields[2];
 	uint8_t out_addr_buf;
+	int retval;
 
-	arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Scan out a read or write operation using some DP or AP register.
 	 * For APACC access with any sticky error flag set, this is discarded.
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b742daeb3..abfb21bd9 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -690,9 +690,13 @@ int arm7_9_execute_sys_speed(struct target *target)
 	/* set RESTART instruction */
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
-		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+		retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+		if (retval != ERROR_OK)
+			return retval;
 	}
-	arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	long long then = timeval_ms();
 	int timeout;
@@ -738,13 +742,18 @@ static int arm7_9_execute_fast_sys_speed(struct target *target)
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 	struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+	int retval;
 
 	/* set RESTART instruction */
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
-		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+		retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+		if (retval != ERROR_OK)
+			return retval;
 	}
-	arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (!set)
 	{
@@ -1744,13 +1753,19 @@ static int arm7_9_restart_core(struct target *target)
 {
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
+	int retval;
 
 	/* set RESTART instruction */
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
-		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+
+		retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+		if (retval != ERROR_OK)
+			return retval;
 	}
-	arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	jtag_add_runtest(1, TAP_IDLE);
 	return jtag_execute_queue();
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 541adc8ed..8befe2bf9 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -68,7 +68,9 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
 		{
 			return retval;
 		}
-		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+		retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+		if (retval != ERROR_OK)
+			return retval;
 
 		jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -117,8 +119,11 @@ static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_
 static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
 		uint32_t out, uint32_t *deprecated, int breakpoint)
 {
+	int retval;
 	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
 }
@@ -133,7 +138,9 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = NULL;
@@ -217,7 +224,9 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = NULL;
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 7627b25e8..c5064c112 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -89,11 +89,14 @@ static int arm920t_read_cp15_physical(struct target *target,
 	uint8_t access_type_buf = 1;
 	uint8_t reg_addr_buf = reg_addr & 0x3f;
 	uint8_t nr_w_buf = 0;
+	int retval;
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
 	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
@@ -137,13 +140,16 @@ static int arm920t_write_cp15_physical(struct target *target,
 	uint8_t reg_addr_buf = reg_addr & 0x3f;
 	uint8_t nr_w_buf = 1;
 	uint8_t value_buf[4];
+	int retval;
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
 	buf_set_u32(value_buf, 0, 32, value);
 
 	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
@@ -192,7 +198,9 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
 	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index aa38d27f8..3765f2313 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -67,7 +67,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -120,7 +122,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
 
-	arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	return ERROR_OK;
 }
@@ -155,7 +159,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
@@ -205,7 +211,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-	arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index b4207c8c1..170e3cc58 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -88,7 +88,9 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	/* REVISIT: table 7-2 shows that bits 31-31 need to be
@@ -142,7 +144,9 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 0749a56ed..fd5070314 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -103,7 +103,9 @@ int arm9tdmi_examine_debug_reason(struct target *target)
 		{
 			return retval;
 		}
-		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+		retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
+		if (retval != ERROR_OK)
+			return retval;
 
 		jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -157,7 +159,9 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
 		return retval;
 	}
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;
@@ -215,7 +219,9 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 		return retval;
 	}
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -281,7 +287,9 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 		return retval;
 	}
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 7ef4ac421..965260ca3 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -344,10 +344,13 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	struct scan_field fields[3];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
 	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* bits 31:0 -- data (ignored here) */
 	fields[0].num_bits = 32;
@@ -405,9 +408,12 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 	struct scan_field fields[3];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
 	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -487,12 +493,13 @@ static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
 void embeddedice_write_reg(struct reg *reg, uint32_t value)
 {
 	struct embeddedice_reg *ice_reg = reg->arch_info;
+	int retval;
 
 	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
 	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	uint8_t reg_addr = ice_reg->addr & 0x1f;
 	embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
@@ -521,9 +528,12 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 	uint8_t field0_out[4];
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
+	int retval;
 
 	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = field0_out;
@@ -575,7 +585,9 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 		return ERROR_INVALID_ARGUMENTS;
 
 	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
diff --git a/src/target/etm.c b/src/target/etm.c
index 61ee99a04..5c42fb59a 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -496,6 +496,7 @@ static int etm_read_reg_w_check(struct reg *reg,
 	const struct etm_reg_info *r = etm_reg->reg_info;
 	uint8_t reg_addr = r->addr & 0x7f;
 	struct scan_field fields[3];
+	int retval;
 
 	if (etm_reg->reg_info->mode == WO) {
 		LOG_ERROR("BUG: can't read write-only register %s", r->name);
@@ -505,7 +506,9 @@ static int etm_read_reg_w_check(struct reg *reg,
 	LOG_DEBUG("%s (%u)", r->name, reg_addr);
 
 	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
-	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
@@ -577,6 +580,7 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 	const struct etm_reg_info *r = etm_reg->reg_info;
 	uint8_t reg_addr = r->addr & 0x7f;
 	struct scan_field fields[3];
+	int retval;
 
 	if (etm_reg->reg_info->mode == RO) {
 		LOG_ERROR("BUG: can't write read--only register %s", r->name);
@@ -586,7 +590,9 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 
 	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
-	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	uint8_t tmp1[4];
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index ea22ca00d..6ca432a8c 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -78,6 +78,7 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 	uint8_t out_buf[4];
 	uint8_t instr_buf[4];
 	uint8_t sysspeed_buf = 0x0;
+	int retval;
 
 	/* prepare buffer */
 	buf_set_u32(out_buf, 0, 32, 0);
@@ -86,7 +87,9 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 
 	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;
-- 
2.11.4.GIT


From 441ea95f693316052f04486b927abb2b152ca547 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 14:42:54 +0200
Subject: [PATCH 12/16] adi_jtag_ error propagation
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/adi_v5_jtag.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 185bd5437..8731a1a09 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -211,8 +211,10 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 	/* Post CTRL/STAT read; discard any previous posted read value
 	 * but collect its ACK status.
 	 */
-	adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+	retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+	if (retval != ERROR_OK)
+		return retval;
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 		return retval;
 
@@ -246,8 +248,10 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 				return ERROR_JTAG_DEVICE_ERROR;
 			}
 
-			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+			if (retval != ERROR_OK)
+				return retval;
 			if ((retval = dap_run(dap)) != ERROR_OK)
 				return retval;
 			dap->ack = dap->ack & 0x7;
@@ -292,12 +296,16 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 				LOG_ERROR("JTAG-DP STICKY ERROR");
 
 			/* Clear Sticky Error Bits */
-			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_WRITE,
 					dap->dp_ctrl_stat | SSTICKYORUN
 						| SSTICKYERR, NULL);
-			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			if (retval != ERROR_OK)
+				return retval;
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+			if (retval != ERROR_OK)
+				return retval;
 			if ((retval = dap_run(dap)) != ERROR_OK)
 				return retval;
 
-- 
2.11.4.GIT


From a9761c90931101d280b9443126db017f96d92e3d Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Mon, 19 Jul 2010 14:49:41 +0200
Subject: [PATCH 13/16] arm_dpm: error propagation fixes
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

found by inspection

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm_dpm.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 4fbe5e3b0..012316bf8 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -123,6 +123,8 @@ static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 		cpsr = mode;
 
 	retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (dpm->instr_cpsr_sync)
 		retval = dpm->instr_cpsr_sync(dpm);
@@ -211,6 +213,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 		retval = dpm->instr_write_data_r0(dpm,
 				ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
 				value);
+		if (retval != ERROR_OK)
+			return retval;
 
 		if (regnum == 16 && dpm->instr_cpsr_sync)
 			retval = dpm->instr_cpsr_sync(dpm);
@@ -364,6 +368,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
 			retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
 					bp ? &bp->set : NULL);
+			if (retval != ERROR_OK)
+				goto done;
 		}
 	}
 
@@ -374,6 +380,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
 		retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
 				wp ? &wp->set : NULL);
+		if (retval != ERROR_OK)
+			goto done;
 	}
 
 	/* NOTE:  writes to breakpoint and watchpoint registers might
@@ -433,7 +441,11 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
 				/* REVISIT error checks */
 				if (tmode != ARM_MODE_ANY)
+				{
 					retval = dpm_modeswitch(dpm, tmode);
+					if (retval != ERROR_OK)
+						goto done;
+				}
 			}
 			if (r->mode != mode)
 				continue;
@@ -441,7 +453,8 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 			retval = dpm_write_reg(dpm,
 					&cache->reg_list[i],
 					regnum);
-
+			if (retval != ERROR_OK)
+				goto done;
 		}
 
 	} while (did_write);
@@ -451,13 +464,19 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	 * defined, and must not write it before CPSR.
 	 */
 	retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
+	if (retval != ERROR_OK)
+		goto done;
 	arm->cpsr->dirty = false;
 
 	retval = dpm_write_reg(dpm, arm->pc, 15);
+	if (retval != ERROR_OK)
+		goto done;
 	arm->pc->dirty = false;
 
 	/* flush R0 -- it's *very* dirty by now */
 	retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
+	if (retval != ERROR_OK)
+		goto done;
 	cache->reg_list[0].dirty = false;
 
 	/* (void) */ dpm->finish(dpm);
@@ -540,6 +559,8 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
 	}
 
 	retval = dpm_read_reg(dpm, r, regnum);
+	if (retval != ERROR_OK)
+		goto fail;
 	/* always clean up, regardless of error */
 
 	if (mode != ARM_MODE_ANY)
@@ -636,6 +657,8 @@ static int arm_dpm_full_context(struct target *target)
 
 				/* REVISIT error checks */
 				retval = dpm_modeswitch(dpm, mode);
+				if (retval != ERROR_OK)
+					goto done;
 			}
 			if (r->mode != mode)
 				continue;
@@ -644,7 +667,8 @@ static int arm_dpm_full_context(struct target *target)
 			retval = dpm_read_reg(dpm,
 					&cache->reg_list[i],
 					(r->num == 16) ? 17 : r->num);
-
+			if (retval != ERROR_OK)
+				goto done;
 		}
 
 	} while (did_read);
-- 
2.11.4.GIT


From e0525cd182aee35549f13e786143ccc0a252aeab Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Tue, 20 Jul 2010 08:23:59 +0200
Subject: [PATCH 14/16] arm_jtag_scann error propagation fixes
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm7tdmi.c    |  4 +++-
 src/target/arm920t.c     | 12 +++++++++---
 src/target/embeddedice.c | 18 +++++++++++++-----
 src/target/etm.c         |  8 ++++++--
 src/target/feroceon.c    |  4 +++-
 5 files changed, 34 insertions(+), 12 deletions(-)

diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 8befe2bf9..f4ba44ac1 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -120,7 +120,9 @@ static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
 		uint32_t out, uint32_t *deprecated, int breakpoint)
 {
 	int retval;
-	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
+	retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index c5064c112..90f548f38 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -93,7 +93,9 @@ static int arm920t_read_cp15_physical(struct target *target,
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
@@ -146,7 +148,9 @@ static int arm920t_write_cp15_physical(struct target *target,
 
 	buf_set_u32(value_buf, 0, 32, value);
 
-	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
@@ -197,7 +201,9 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 965260ca3..abc49d7e6 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -346,7 +346,9 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	uint8_t field2_out[1];
 	int retval;
 
-	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+	retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
@@ -410,7 +412,9 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 	uint8_t field2_out[1];
 	int retval;
 
-	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
@@ -497,7 +501,7 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
 
 	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
-	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
+	retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
 	retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
@@ -530,7 +534,9 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 	uint8_t field2_out[1];
 	int retval;
 
-	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
@@ -584,7 +590,9 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 	else
 		return ERROR_INVALID_ARGUMENTS;
 
-	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/target/etm.c b/src/target/etm.c
index 5c42fb59a..9da695504 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -505,7 +505,9 @@ static int etm_read_reg_w_check(struct reg *reg,
 
 	LOG_DEBUG("%s (%u)", r->name, reg_addr);
 
-	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
+	retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
@@ -589,7 +591,9 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 
 	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 
-	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
+	retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 	retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 6ca432a8c..2152a2601 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -85,7 +85,9 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 
 	buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 
-	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
+	retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 	if (retval != ERROR_OK)
-- 
2.11.4.GIT


From 1143bbc0c88c20300106ce9d63b2b77c9c2f66c9 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Tue, 20 Jul 2010 08:42:52 +0200
Subject: [PATCH 15/16] arm11 error propagation fixes
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 src/target/arm11.c        | 46 +++++++++++++++++++++++-----------------------
 src/target/arm11_dbgtap.c | 11 +++++++----
 src/target/arm11_dbgtap.h |  4 ++--
 3 files changed, 32 insertions(+), 29 deletions(-)

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 67f0524e2..85d45b009 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -62,7 +62,7 @@ static int arm11_check_init(struct arm11_common *arm11)
 		LOG_DEBUG("Bringing target into debug mode");
 
 		arm11->dscr |= DSCR_HALT_DBG_MODE;
-		arm11_write_DSCR(arm11, arm11->dscr);
+		CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
 
 		/* add further reset initialization here */
 
@@ -85,7 +85,7 @@ static int arm11_check_init(struct arm11_common *arm11)
 			arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
 		}
 
-		arm11_sc7_clear_vbw(arm11);
+		CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 	}
 
 	return ERROR_OK;
@@ -133,7 +133,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 	 * but not to issue ITRs(?).  The ARMv7 arch spec says it's required
 	 * for executing instructions via ITR.
 	 */
-	arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
+	CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
 
 
 	/* From the spec:
@@ -291,14 +291,14 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 	/* restore CPSR, PC, and R0 ... after flushing any modified
 	 * registers.
 	 */
-	retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
+	CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
 
-	retval = arm11_bpwp_flush(arm11);
+	CHECK_RETVAL(arm11_bpwp_flush(arm11));
 
 	register_cache_invalidate(arm11->arm.core_cache);
 
 	/* restore DSCR */
-	arm11_write_DSCR(arm11, arm11->dscr);
+	CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
 
 	/* maybe restore rDTR */
 	if (arm11->is_rdtr_saved)
@@ -484,7 +484,7 @@ static int arm11_resume(struct target *target, int current,
 	LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
 
 	/* clear breakpoints/watchpoints and VCR*/
-	arm11_sc7_clear_vbw(arm11);
+	CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 
 	if (!debug_execution)
 		target_free_all_working_areas(target);
@@ -520,7 +520,7 @@ static int arm11_resume(struct target *target, int current,
 			brp[1].address	= ARM11_SC7_BCR0 + brp_num;
 			brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 
-			arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
+			CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 
 			LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
 					bp->address);
@@ -529,11 +529,11 @@ static int arm11_resume(struct target *target, int current,
 		}
 
 		if (arm11->vcr)
-			arm11_sc7_set_vcr(arm11, arm11->vcr);
+			CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
 	}
 
 	/* activate all watchpoints and breakpoints */
-	arm11_leave_debug_state(arm11, true);
+	CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
 
 	arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 
@@ -725,7 +725,7 @@ static int arm11_step(struct target *target, int current,
 		}
 
 		/* clear breakpoint */
-		arm11_sc7_clear_vbw(arm11);
+		CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 
 		/* save state */
 		CHECK_RETVAL(arm11_debug_entry(arm11));
@@ -748,7 +748,7 @@ static int arm11_assert_reset(struct target *target)
 
 	/* optionally catch reset vector */
 	if (target->reset_halt && !(arm11->vcr & 1))
-		arm11_sc7_set_vcr(arm11, arm11->vcr | 1);
+		CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
 
 	/* Issue some kind of warm reset. */
 	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
@@ -795,7 +795,7 @@ static int arm11_deassert_reset(struct target *target)
 	 */
 	jtag_add_tlr();
 
-	retval = arm11_poll(target);
+	CHECK_RETVAL(arm11_poll(target));
 
 	if (target->reset_halt) {
 		if (target->state != TARGET_HALTED) {
@@ -808,7 +808,7 @@ static int arm11_deassert_reset(struct target *target)
 
 	/* maybe restore vector catch config */
 	if (target->reset_halt && !(arm11->vcr & 1))
-		arm11_sc7_set_vcr(arm11, arm11->vcr);
+		CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
 
 	return ERROR_OK;
 }
@@ -863,12 +863,12 @@ static int arm11_read_memory_inner(struct target *target,
 		{
 			/* ldrb    r1, [r0], #1 */
 			/* ldrb    r1, [r0] */
-			arm11_run_instr_no_data1(arm11,
-					!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
+			CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+					!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
 
 			uint32_t res;
 			/* MCR p14,0,R1,c0,c5,0 */
-			arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
+			CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
 
 			*buffer++ = res;
 		}
@@ -882,13 +882,13 @@ static int arm11_read_memory_inner(struct target *target,
 			for (size_t i = 0; i < count; i++)
 			{
 				/* ldrh    r1, [r0], #2 */
-				arm11_run_instr_no_data1(arm11,
-					!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
+				CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+					!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
 
 				uint32_t res;
 
 				/* MCR p14,0,R1,c0,c5,0 */
-				arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
+				CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
 
 				uint16_t svalue = res;
 				memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
@@ -905,7 +905,7 @@ static int arm11_read_memory_inner(struct target *target,
 
 		/* LDC p14,c5,[R0],#4 */
 		/* LDC p14,c5,[R0] */
-		arm11_run_instr_data_from_core(arm11, instr, words, count);
+		CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
 		break;
 		}
 	}
@@ -1265,14 +1265,14 @@ static int arm11_examine(struct target *target)
 	 * want to know if this core supports Secure Monitor mode.
 	 */
 	if (!target_was_examined(target))
-		retval = arm11_dpm_init(arm11, didr);
+		CHECK_RETVAL(arm11_dpm_init(arm11, didr));
 
 	/* ETM on ARM11 still uses original scanchain 6 access mode */
 	if (arm11->arm.etm && !target_was_examined(target)) {
 		*register_get_last_cache_p(&target->reg_cache) =
 			etm_build_reg_cache(target, &arm11->jtag_info,
 					arm11->arm.etm);
-		retval = etm_setup(target);
+		CHECK_RETVAL(etm_setup(target));
 	}
 
 	target_set_examined(target);
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index b2c6287fe..4e90933d7 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -964,7 +964,7 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
  * \param arm11		Target state variable.
  *
  */
-void arm11_sc7_clear_vbw(struct arm11_common * arm11)
+int arm11_sc7_clear_vbw(struct arm11_common * arm11)
 {
 	size_t clear_bw_size = arm11->brp + 1;
 	struct arm11_sc7_action		*clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
@@ -981,9 +981,12 @@ void arm11_sc7_clear_vbw(struct arm11_common * arm11)
 
 	(pos++)->address = ARM11_SC7_VCR;
 
-	arm11_sc7_run(arm11, clear_bw, clear_bw_size);
+	int retval;
+	retval = arm11_sc7_run(arm11, clear_bw, clear_bw_size);
 
 	free (clear_bw);
+
+	return retval;
 }
 
 /** Write VCR register
@@ -991,7 +994,7 @@ void arm11_sc7_clear_vbw(struct arm11_common * arm11)
  * \param arm11		Target state variable.
  * \param value		Value to be written
  */
-void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
+int arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
 {
 	struct arm11_sc7_action		set_vcr;
 
@@ -999,7 +1002,7 @@ void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
 	set_vcr.address		= ARM11_SC7_VCR;
 	set_vcr.value		= value;
 
-	arm11_sc7_run(arm11, &set_vcr, 1);
+	return arm11_sc7_run(arm11, &set_vcr, 1);
 }
 
 
diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h
index 762c9bec6..e45bdc2d9 100644
--- a/src/target/arm11_dbgtap.h
+++ b/src/target/arm11_dbgtap.h
@@ -52,8 +52,8 @@ int arm11_sc7_run(struct arm11_common *arm11,
 		struct arm11_sc7_action *actions, size_t count);
 
 /* Mid-level helper functions */
-void arm11_sc7_clear_vbw(struct arm11_common *arm11);
-void arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value);
+int arm11_sc7_clear_vbw(struct arm11_common *arm11);
+int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value);
 
 int arm11_read_memory_word(struct arm11_common *arm11,
 		uint32_t address, uint32_t *result);
-- 
2.11.4.GIT


From 8f7e861d25c23e4ecf2c51fae286e249bb83abdb Mon Sep 17 00:00:00 2001
From: =?utf8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Tue, 20 Jul 2010 09:11:45 +0200
Subject: [PATCH 16/16] bdi helper tcl fn's
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Allows pretty much copying and pasting reset init sequence
from BDI scripts.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 tcl/helper/bdi.cfg | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 tcl/helper/bdi.cfg

diff --git a/tcl/helper/bdi.cfg b/tcl/helper/bdi.cfg
new file mode 100644
index 000000000..e63e4e75c
--- /dev/null
+++ b/tcl/helper/bdi.cfg
@@ -0,0 +1,45 @@
+# Some helper proc's to translate BDM syntax to OpenOCD speak
+#
+# NOTE!!! OpenOCD supports trailing '#' on base commands as a 
+# prefix to end of line comments. However, the proc's below do not.
+#
+# Tcl only accepts '#' as a start of line prefix to comments. 
+#
+# A ";" is not a prefix to end of line comments in Tcl, 
+# but signifies that a new command is following, so a
+# bdi comment will yield a syntax error.
+# 
+# The fix is to move the comment to the line before.
+#
+# WM32 0x53FC0000 0x00000040		; enable ipu
+#
+# Becomes:
+#
+# #enable ipu
+# WM32 0x53FC0000 0x00000040
+ 
+
+#Example:
+# WM32 0x53FC0000 0x00000040		; enable ipu
+proc WM32 {address val} {
+	mww [string tolower $address] [string tolower $val]
+}
+
+# Example:
+# WM8  0x80000033 0xDA			; dummy write only address matter
+proc WM8 {address val} {
+	mwb [string tolower $address] [string tolower $val]
+}
+ 
+# Example:
+# WREG CPSR 0x000000D3
+proc WREG {regname val} {
+	reg [string tolower $regname] [string tolower $val]
+}
+
+# Example:
+# WCP15  0x0001 0x00050078		; CP15 control register
+proc WCP15 {regs value} {
+	arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
+}
+
-- 
2.11.4.GIT