src/target/cortex_m3.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef CORTEX_M3_H
  27 #define CORTEX_M3_H
  28
  29 #include "armv7m.h"
  30
  31
  32 #define CORTEX_M3_COMMON_MAGIC 0x1A451A45
  33
  34 #define SYSTEM_CONTROL_BASE 0x400FE000
  35
  36 #define CPUID           0xE000ED00
  37 /* Debug Control Block */
  38 #define DCB_DHCSR       0xE000EDF0
  39 #define DCB_DCRSR       0xE000EDF4
  40 #define DCB_DCRDR       0xE000EDF8
  41 #define DCB_DEMCR       0xE000EDFC
  42
  43 #define DCRSR_WnR       (1 << 16)
  44
  45 #define DWT_CTRL        0xE0001000
  46 #define DWT_CYCCNT      0xE0001004
  47 #define DWT_COMP0       0xE0001020
  48 #define DWT_MASK0       0xE0001024
  49 #define DWT_FUNCTION0   0xE0001028
  50
  51 #define FP_CTRL         0xE0002000
  52 #define FP_REMAP        0xE0002004
  53 #define FP_COMP0        0xE0002008
  54 #define FP_COMP1        0xE000200C
  55 #define FP_COMP2        0xE0002010
  56 #define FP_COMP3        0xE0002014
  57 #define FP_COMP4        0xE0002018
  58 #define FP_COMP5        0xE000201C
  59 #define FP_COMP6        0xE0002020
  60 #define FP_COMP7        0xE0002024
  61
  62 /* DCB_DHCSR bit and field definitions */
  63 #define DBGKEY          (0xA05F << 16)
  64 #define C_DEBUGEN       (1 << 0)
  65 #define C_HALT          (1 << 1)
  66 #define C_STEP          (1 << 2)
  67 #define C_MASKINTS      (1 << 3)
  68 #define S_REGRDY        (1 << 16)
  69 #define S_HALT          (1 << 17)
  70 #define S_SLEEP         (1 << 18)
  71 #define S_LOCKUP        (1 << 19)
  72 #define S_RETIRE_ST     (1 << 24)
  73 #define S_RESET_ST      (1 << 25)
  74
  75 /* DCB_DEMCR bit and field definitions */
  76 #define TRCENA                  (1 << 24)
  77 #define VC_HARDERR              (1 << 10)
  78 #define VC_INTERR               (1 << 9)
  79 #define VC_BUSERR               (1 << 8)
  80 #define VC_STATERR              (1 << 7)
  81 #define VC_CHKERR               (1 << 6)
  82 #define VC_NOCPERR              (1 << 5)
  83 #define VC_MMERR                (1 << 4)
  84 #define VC_CORERESET    (1 << 0)
  85
  86 #define NVIC_ICTR               0xE000E004
  87 #define NVIC_ISE0               0xE000E100
  88 #define NVIC_ICSR               0xE000ED04
  89 #define NVIC_AIRCR              0xE000ED0C
  90 #define NVIC_SHCSR              0xE000ED24
  91 #define NVIC_CFSR               0xE000ED28
  92 #define NVIC_MMFSRb             0xE000ED28
  93 #define NVIC_BFSRb              0xE000ED29
  94 #define NVIC_USFSRh             0xE000ED2A
  95 #define NVIC_HFSR               0xE000ED2C
  96 #define NVIC_DFSR               0xE000ED30
  97 #define NVIC_MMFAR              0xE000ED34
  98 #define NVIC_BFAR               0xE000ED38
  99
 100 /* NVIC_AIRCR bits */
 101 #define AIRCR_VECTKEY           (0x5FA << 16)
 102 #define AIRCR_SYSRESETREQ       (1 << 2)
 103 #define AIRCR_VECTCLRACTIVE     (1 << 1)
 104 #define AIRCR_VECTRESET         (1 << 0)
 105 /* NVIC_SHCSR bits */
 106 #define SHCSR_BUSFAULTENA       (1 << 17)
 107 /* NVIC_DFSR bits */
 108 #define DFSR_HALTED                     1
 109 #define DFSR_BKPT                       2
 110 #define DFSR_DWTTRAP            4
 111 #define DFSR_VCATCH                     8
 112
 113 #define FPCR_CODE 0
 114 #define FPCR_LITERAL 1
 115 #define FPCR_REPLACE_REMAP  (0 << 30)
 116 #define FPCR_REPLACE_BKPT_LOW  (1 << 30)
 117 #define FPCR_REPLACE_BKPT_HIGH  (2 << 30)
 118 #define FPCR_REPLACE_BKPT_BOTH  (3 << 30)
 119
 120 struct cortex_m3_fp_comparator
 121 {
 122         int used;
 123         int type;
 124         uint32_t fpcr_value;
 125         uint32_t fpcr_address;
 126 };
 127
 128 struct cortex_m3_dwt_comparator
 129 {
 130         int used;
 131         uint32_t comp;
 132         uint32_t mask;
 133         uint32_t function;
 134         uint32_t dwt_comparator_address;
 135 };
 136
 137 enum cortex_m3_soft_reset_config
 138 {
 139         CORTEX_M3_RESET_SYSRESETREQ,
 140         CORTEX_M3_RESET_VECTRESET,
 141 };
 142
 143 enum cortex_m3_isrmasking_mode
 144 {
 145         CORTEX_M3_ISRMASK_AUTO,
 146         CORTEX_M3_ISRMASK_OFF,
 147         CORTEX_M3_ISRMASK_ON,
 148 };
 149
 150 struct cortex_m3_common
 151 {
 152         int common_magic;
 153         struct arm_jtag jtag_info;
 154
 155         /* Context information */
 156         uint32_t dcb_dhcsr;
 157         uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 158         uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 159
 160         /* Flash Patch and Breakpoint (FPB) */
 161         int fp_num_lit;
 162         int fp_num_code;
 163         int fp_code_available;
 164         int fpb_enabled;
 165         int auto_bp_type;
 166         struct cortex_m3_fp_comparator *fp_comparator_list;
 167
 168         /* Data Watchpoint and Trace (DWT) */
 169         int dwt_num_comp;
 170         int dwt_comp_available;
 171         struct cortex_m3_dwt_comparator *dwt_comparator_list;
 172         struct reg_cache *dwt_cache;
 173
 174         enum cortex_m3_soft_reset_config soft_reset_config;
 175
 176         enum cortex_m3_isrmasking_mode isrmasking_mode;
 177
 178         struct armv7m_common armv7m;
 179 };
 180
 181 static inline struct cortex_m3_common *
 182 target_to_cm3(struct target *target)
 183 {
 184         return container_of(target->arch_info,
 185                         struct cortex_m3_common, armv7m);
 186 }
 187
 188 #endif /* CORTEX_M3_H */