src/jtag/drivers/OpenULINK/include/reg_ezusb.h

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Martin Schmoelzer                               *
   3  *   <martin.schmoelzer@student.tuwien.ac.at>                              *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifndef REG_EZUSB_H
  22 #define REG_EZUSB_H
  23
  24 /**
  25  * @file
  26  * All information in this file was taken from the EZ-USB Technical
  27  * Reference Manual, Cypress Semiconductor, 3901 North First Street
  28  * San Jose, CA 95134 (www.cypress.com).
  29  *
  30  * The EZ-USB Technical Reference Manual is called "EZ-USB TRM" hereafter.
  31  *
  32  * The following bit name  definitions differ from those in the EZ-USB TRM:
  33  * - All lowercase characters in the EZ-USB TRM bit names have been converted
  34  *   to capitals (e. g. "WakeSRC" converted to "WAKESRC").
  35  * - CPUCS:  8051RES is named "RES8051".
  36  * - ISOCTL: Two MBZ ("Must Be Zero") bits are named "MBZ0" and "MBZ1".
  37  * - I2CS: STOP and START bits are preceded by "I2C_"
  38  * - INxCS, OUTxCS: the busy and stall bits are named "EPBSY" and "EPSTALL".
  39  * - TOGCTL: EZ-USB TRM bit names are preceded by "TOG_".
  40  */
  41
  42 /* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
  43 #include <mcs51/compiler.h>
  44
  45 /* Bit vectors */
  46 #define bmBit0      0x01
  47 #define bmBit1      0x02
  48 #define bmBit2      0x04
  49 #define bmBit3      0x08
  50 #define bmBit4      0x10
  51 #define bmBit5      0x20
  52 #define bmBit6      0x40
  53 #define bmBit7      0x80
  54
  55 /**************************************************************************
  56  ************************ Special Function Registers **********************
  57  ***************************************************************************/
  58
  59 /* See EZ-USB TRM, pp. A-9 - A-10 */
  60
  61 SFR(SP,             0x81);
  62 SFR(DPL0,           0x82);
  63 SFR(DPH0,           0x83);
  64 SFR(DPL1,           0x84);
  65 SFR(DPL2,           0x85);
  66
  67 SFR(DPS,            0x86);
  68 #define SEL         bmBit0
  69 /* Bit 1 read-only, always reads '0' */
  70 /* Bit 2 read-only, always reads '0' */
  71 /* Bit 3 read-only, always reads '0' */
  72 /* Bit 4 read-only, always reads '0' */
  73 /* Bit 5 read-only, always reads '0' */
  74 /* Bit 6 read-only, always reads '0' */
  75 /* Bit 7 read-only, always reads '0' */
  76
  77 SFR(PCON,           0x87);
  78 #define IDLE        bmBit0
  79 #define STOP        bmBit1
  80 #define GF0         bmBit2
  81 #define GF1         bmBit3
  82 /* Bit 4 read-only, always reads '1' */
  83 /* Bit 5 read-only, always reads '1' */
  84 /* Bit 6 unused */
  85 #define SMOD0     bmBit7
  86
  87 SFR(TCON,           0x88);
  88 SBIT(IT0,           0x88, 0);
  89 SBIT(IE0,           0x88, 1);
  90 SBIT(IT1,           0x88, 2);
  91 SBIT(IE1,           0x88, 3);
  92 SBIT(TR0,           0x88, 4);
  93 SBIT(TF0,           0x88, 5);
  94 SBIT(TR1,           0x88, 6);
  95 SBIT(TF1,           0x88, 7);
  96
  97 SFR(TMOD,           0x89);
  98 /* Some bits in this register share the same name in the EZ-USB TRM. Therefore,
  99  * we add a '0'/'1' to distinguish them */
 100 #define M00         bmBit0
 101 #define M01         bmBit1
 102 #define CT0         bmBit2
 103 #define GATE0       bmBit3
 104 #define M10         bmBit4
 105 #define M11         bmBit5
 106 #define CT1         bmBit6
 107 #define GATE1       bmBit7
 108
 109 SFR(TL0,            0x8A);
 110 SFR(TL1,            0x8B);
 111 SFR(TH0,            0x8C);
 112 SFR(TH1,            0x8D);
 113
 114 SFR(CKCON,          0x8E);
 115 #define MD0         bmBit0
 116 #define MD1         bmBit1
 117 #define MD2         bmBit2
 118 #define T0M         bmBit3
 119 #define T1M         bmBit4
 120 #define T2M         bmBit5
 121 /* Bit 6 unused */
 122 /* Bit 7 unused */
 123
 124 SFR(SPC_FNC,        0x8D);
 125 #define bmWRS       bmBit0
 126 /* Bit 1 read-only, always reads '0' */
 127 /* Bit 2 read-only, always reads '0' */
 128 /* Bit 3 read-only, always reads '0' */
 129 /* Bit 4 read-only, always reads '0' */
 130 /* Bit 5 read-only, always reads '0' */
 131 /* Bit 6 read-only, always reads '0' */
 132 /* Bit 7 read-only, always reads '0' */
 133
 134 SFR(EXIF,           0x91);
 135 /* Bit 0 read-only, always reads '0' */
 136 /* Bit 1 read-only, always reads '0' */
 137 /* Bit 2 read-only, always reads '0' */
 138 /* Bit 3 read-only, always reads '1' */
 139 #define USBINT      bmBit4
 140 #define I2CINT      bmBit5
 141 #define IE4         bmBit6
 142 #define IE5         bmBit7
 143
 144 /* Definition of the _XPAGE register, according to SDCC Compiler User Guide,
 145  * Version 3.0.1, Chapter 4, p. 61. Also see EZ-USB TRM, p. 2-4. */
 146 SFR(MPAGE,          0x92);
 147 SFR(_XPAGE,         0x92);
 148
 149 SFR(SCON0,          0x98);
 150 SBIT(RI_0,          0x98, 0);
 151 SBIT(TI_0,          0x98, 1);
 152 SBIT(RB8_0,         0x98, 2);
 153 SBIT(TB8_0,         0x98, 3);
 154 SBIT(REN_0,         0x98, 4);
 155 SBIT(SM2_0,         0x98, 5);
 156 SBIT(SM1_0,         0x98, 6);
 157 SBIT(SM0_0,         0x98, 7);
 158
 159 SFR(SBUF0,          0x99);
 160
 161 SFR(IE,             0xA8);
 162 SBIT(EX0,           0xA8, 0);
 163 SBIT(ET0,           0xA8, 1);
 164 SBIT(EX1,           0xA8, 2);
 165 SBIT(ET1,           0xA8, 3);
 166 SBIT(ES0,           0xA8, 4);
 167 SBIT(ET2,           0xA8, 5);
 168 SBIT(ES1,           0xA8, 6);
 169 SBIT(EA,            0xA8, 7);
 170
 171 SFR(IP,             0xB8);
 172 SBIT(PX0,           0xB8, 0);
 173 SBIT(PT0,           0xB8, 1);
 174 SBIT(PX1,           0xB8, 2);
 175 SBIT(PT1,           0xB8, 3);
 176 SBIT(PS0,           0xB8, 4);
 177 SBIT(PT2,           0xB8, 5);
 178 SBIT(PS1,           0xB8, 6);
 179 /* Bit 7 read-only, always reads '1' */
 180
 181 SFR(SCON1,          0xC0);
 182 SBIT(RI_1,          0xC0, 0);
 183 SBIT(TI_1,          0xC0, 1);
 184 SBIT(RB8_1,         0xC0, 2);
 185 SBIT(TB8_1,         0xC0, 3);
 186 SBIT(REN_1,         0xC0, 4);
 187 SBIT(SM2_1,         0xC0, 5);
 188 SBIT(SM1_1,         0xC0, 6);
 189 SBIT(SM0_1,         0xC0, 7);
 190
 191 SFR(SBUF1,          0xC1);
 192
 193 SFR(T2CON,          0xC8);
 194 SBIT(CPRL2,         0xC8, 0);
 195 SBIT(CT2,           0xC8, 1);
 196 SBIT(TR2,           0xC8, 2);
 197 SBIT(EXEN2,         0xC8, 3);
 198 SBIT(TCLK,          0xC8, 4);
 199 SBIT(RCLK,          0xC8, 5);
 200 SBIT(EXF2,          0xC8, 6);
 201 SBIT(TF2,           0xC8, 7);
 202
 203 SFR(RCAP2L,         0xCA);
 204 SFR(RCAP2H,         0xCB);
 205 SFR(TL2,            0xCC);
 206 SFR(TH2,            0xCD);
 207
 208 SFR(PSW,            0xD0);
 209 SBIT(P,             0xD0, 0);
 210 SBIT(F1,            0xD0, 1);
 211 SBIT(OV,            0xD0, 2);
 212 SBIT(RS0,           0xD0, 3);
 213 SBIT(RS1,           0xD0, 4);
 214 SBIT(F0,            0xD0, 5);
 215 SBIT(AC,            0xD0, 6);
 216 SBIT(CY,            0xD0, 7);
 217
 218 SFR(EICON,          0xD8);
 219 /* Bit 0 read-only, always reads '0' */
 220 /* Bit 1 read-only, always reads '0' */
 221 /* Bit 2 read-only, always reads '0' */
 222 SBIT(INT6,          0xD8, 3);
 223 SBIT(RESI,          0xD8, 4);
 224 SBIT(ERESI,         0xD8, 5);
 225 /* Bit 6 read-only, always reads '1' */
 226 SBIT(SMOD1,         0xD8, 7);
 227
 228 SFR(ACC,            0xE0);
 229
 230 SFR(EIE,            0xE8);
 231 SBIT(EUSB,          0xE8, 0);
 232 SBIT(EI2C,          0xE8, 1);
 233 SBIT(EX4,           0xE8, 2);
 234 SBIT(EX5,           0xE8, 3);
 235 SBIT(EWDI,          0xE8, 4);
 236 /* Bit 5 read-only, always reads '1' */
 237 /* Bit 6 read-only, always reads '1' */
 238 /* Bit 7 read-only, always reads '1' */
 239
 240 SFR(B,              0xF0);
 241
 242 SFR(EIP,            0xF8);
 243 SBIT(PUSB,          0xF8, 0);
 244 SBIT(PI2C,          0xF8, 1);
 245 SBIT(PX4,           0xF8, 2);
 246 SBIT(PX5,           0xF8, 3);
 247 SBIT(PX6,           0xF8, 4);
 248 /* Bit 5 read-only, always reads '1' */
 249 /* Bit 6 read-only, always reads '1' */
 250 /* Bit 7 read-only, always reads '1' */
 251
 252 /**************************************************************************
 253  ***************************** XDATA Registers ****************************
 254  ***************************************************************************/
 255
 256 /************************ Endpoint 0-7 Data Buffers ************************/
 257 SFRX(OUT7BUF[64],   0x7B40);
 258 SFRX(IN7BUF[64],    0x7B80);
 259 SFRX(OUT6BUF[64],   0x7BC0);
 260 SFRX(IN6BUF[64],    0x7C00);
 261 SFRX(OUT5BUF[64],   0x7C40);
 262 SFRX(IN5BUF[64],    0x7C80);
 263 SFRX(OUT4BUF[64],   0x7CC0);
 264 SFRX(IN4BUF[64],    0x7D00);
 265 SFRX(OUT3BUF[64],   0x7D40);
 266 SFRX(IN3BUF[64],    0x7D80);
 267 SFRX(OUT2BUF[64],   0x7DC0);
 268 SFRX(IN2BUF[64],    0x7E00);
 269 SFRX(OUT1BUF[64],   0x7E40);
 270 SFRX(IN1BUF[64],    0x7E80);
 271 SFRX(OUT0BUF[64],   0x7EC0);
 272 SFRX(IN0BUF[64],    0x7F00);
 273 /* 0x7F40 - 0x7F5F reserved */
 274
 275 /**************************** Isochronous Data *****************************/
 276 SFRX(OUT8DATA,      0x7F60);
 277 SFRX(OUT9DATA,      0x7F61);
 278 SFRX(OUT10DATA,     0x7F62);
 279 SFRX(OUT11DATA,     0x7F63);
 280 SFRX(OUT12DATA,     0x7F64);
 281 SFRX(OUT13DATA,     0x7F65);
 282 SFRX(OUT14DATA,     0x7F66);
 283 SFRX(OUT15DATA,     0x7F67);
 284
 285 SFRX(IN8DATA,       0x7F68);
 286 SFRX(IN9DATA,       0x7F69);
 287 SFRX(IN10DATA,      0x7F6A);
 288 SFRX(IN11DATA,      0x7F6B);
 289 SFRX(IN12DATA,      0x7F6C);
 290 SFRX(IN13DATA,      0x7F6D);
 291 SFRX(IN14DATA,      0x7F6E);
 292 SFRX(IN15DATA,      0x7F6F);
 293
 294 /************************* Isochronous Byte Counts *************************/
 295 SFRX(OUT8BCH,       0x7F70);
 296 SFRX(OUT8BCL,       0x7F71);
 297 SFRX(OUT9BCH,       0x7F72);
 298 SFRX(OUT9BCL,       0x7F73);
 299 SFRX(OUT10BCH,      0x7F74);
 300 SFRX(OUT10BCL,      0x7F75);
 301 SFRX(OUT11BCH,      0x7F76);
 302 SFRX(OUT11BCL,      0x7F77);
 303 SFRX(OUT12BCH,      0x7F78);
 304 SFRX(OUT12BCL,      0x7F79);
 305 SFRX(OUT13BCH,      0x7F7A);
 306 SFRX(OUT13BCL,      0x7F7B);
 307 SFRX(OUT14BCH,      0x7F7C);
 308 SFRX(OUT14BCL,      0x7F7D);
 309 SFRX(OUT15BCH,      0x7F7E);
 310 SFRX(OUT16BCL,      0x7F7F);
 311
 312 /****************************** CPU Registers ******************************/
 313 SFRX(CPUCS,         0x7F92);
 314 #define RES8051     bmBit0
 315 #define CLK24OE     bmBit1
 316 /* Bit 2 read-only, always reads '0' */
 317 /* Bit 3 read-only, always reads '0' */
 318 /* Bits 4...7: Chip Revision */
 319
 320 SFRX(PORTACFG,      0x7F93);
 321 #define T0OUT       bmBit0
 322 #define T1OUT       bmBit1
 323 #define OE          bmBit2
 324 #define CS          bmBit3
 325 #define FWR         bmBit4
 326 #define FRD         bmBit5
 327 #define RXD0OUT     bmBit6
 328 #define RXD1OUT     bmBit7
 329
 330 SFRX(PORTBCFG,      0x7F94);
 331 #define T2          bmBit0
 332 #define T2EX        bmBit1
 333 #define RXD1        bmBit2
 334 #define TXD1        bmBit3
 335 #define INT4        bmBit4
 336 #define INT5        bmBit5
 337 #define INT6        bmBit6
 338 #define T2OUT       bmBit7
 339
 340 SFRX(PORTCCFG,      0x7F95);
 341 #define RXD0        bmBit0
 342 #define TXD0        bmBit1
 343 #define INT0        bmBit2
 344 #define INT1        bmBit3
 345 #define T0          bmBit4
 346 #define T1          bmBit5
 347 #define WR          bmBit6
 348 #define RD          bmBit7
 349
 350 /*********************** Input-Output Port Registers ***********************/
 351 SFRX(OUTA,          0x7F96);
 352 #define OUTA0       bmBit0
 353 #define OUTA1       bmBit1
 354 #define OUTA2       bmBit2
 355 #define OUTA3       bmBit3
 356 #define OUTA4       bmBit4
 357 #define OUTA5       bmBit5
 358 #define OUTA6       bmBit6
 359 #define OUTA7       bmBit7
 360
 361 SFRX(OUTB,          0x7F97);
 362 #define OUTB0       bmBit0
 363 #define OUTB1       bmBit1
 364 #define OUTB2       bmBit2
 365 #define OUTB3       bmBit3
 366 #define OUTB4       bmBit4
 367 #define OUTB5       bmBit5
 368 #define OUTB6       bmBit6
 369 #define OUTB7       bmBit7
 370
 371 SFRX(OUTC,          0x7F98);
 372 #define OUTC0       bmBit0
 373 #define OUTC1       bmBit1
 374 #define OUTC2       bmBit2
 375 #define OUTC3       bmBit3
 376 #define OUTC4       bmBit4
 377 #define OUTC5       bmBit5
 378 #define OUTC6       bmBit6
 379 #define OUTC7       bmBit7
 380
 381 SFRX(PINSA,         0x7F99);
 382 #define PINA0       bmBit0
 383 #define PINA1       bmBit1
 384 #define PINA2       bmBit2
 385 #define PINA3       bmBit3
 386 #define PINA4       bmBit4
 387 #define PINA5       bmBit5
 388 #define PINA6       bmBit6
 389 #define PINA7       bmBit7
 390
 391 SFRX(PINSB,         0x7F9A);
 392 #define PINB0       bmBit0
 393 #define PINB1       bmBit1
 394 #define PINB2       bmBit2
 395 #define PINB3       bmBit3
 396 #define PINB4       bmBit4
 397 #define PINB5       bmBit5
 398 #define PINB6       bmBit6
 399 #define PINB7       bmBit7
 400
 401 SFRX(PINSC,         0x7F9B);
 402 #define PINC0       bmBit0
 403 #define PINC1       bmBit1
 404 #define PINC2       bmBit2
 405 #define PINC3       bmBit3
 406 #define PINC4       bmBit4
 407 #define PINC5       bmBit5
 408 #define PINC6      bmBit6
 409 #define PINC7       bmBit7
 410
 411 SFRX(OEA,           0x7F9C);
 412 #define OEA0        bmBit0
 413 #define OEA1        bmBit1
 414 #define OEA2        bmBit2
 415 #define OEA3        bmBit3
 416 #define OEA4        bmBit4
 417 #define OEA5        bmBit5
 418 #define OEA6        bmBit6
 419 #define OEA7        bmBit7
 420
 421 SFRX(OEB,           0x7F9D);
 422 #define OEB0        bmBit0
 423 #define OEB1        bmBit1
 424 #define OEB2        bmBit2
 425 #define OEB3        bmBit3
 426 #define OEB4        bmBit4
 427 #define OEB5        bmBit5
 428 #define OEB6        bmBit6
 429 #define OEB7        bmBit7
 430
 431 SFRX(OEC,           0x7F9E);
 432 #define OEC0        bmBit0
 433 #define OEC1        bmBit1
 434 #define OEC2        bmBit2
 435 #define OEC3        bmBit3
 436 #define OEC4        bmBit4
 437 #define OEC5        bmBit5
 438 #define OEC6        bmBit6
 439 #define OEC7        bmBit7
 440
 441 /* 0x7F9F reserved */
 442
 443 /****************** Isochronous Control/Status Registers *******************/
 444 SFRX(ISOERR,        0x7FA0);
 445 #define ISO8ERR     bmBit0
 446 #define ISO9ERR     bmBit1
 447 #define ISO10ERR    bmBit2
 448 #define ISO11ERR    bmBit3
 449 #define ISO12ERR    bmBit4
 450 #define ISO13ERR    bmBit5
 451 #define ISO14ERR    bmBit6
 452 #define ISO15ERR    bmBit7
 453
 454 SFRX(ISOCTL,        0x7FA1);
 455 #define ISODISAB    bmBit0
 456 #define MBZ0        bmBit1
 457 #define MBZ1        bmBit2
 458 #define PPSTAT      bmBit3
 459 /* Bit 4 unused */
 460 /* Bit 5 unused */
 461 /* Bit 6 unused */
 462 /* Bit 7 unused */
 463
 464 SFRX(ZBCOUT,        0x7FA2);
 465 #define EP8         bmBit0
 466 #define EP9         bmBit1
 467 #define EP10        bmBit2
 468 #define EP11        bmBit3
 469 #define EP12        bmBit4
 470 #define EP13        bmBit5
 471 #define EP14        bmBit6
 472 #define EP15        bmBit7
 473
 474 /* 0x7FA3 reserved */
 475 /* 0x7FA4 reserved */
 476
 477 /****************************** I2C Registers ******************************/
 478 SFRX(I2CS,          0x7FA5);
 479 #define DONE        bmBit0
 480 #define ACK         bmBit1
 481 #define BERR        bmBit2
 482 #define ID0         bmBit3
 483 #define ID1         bmBit4
 484 #define LASTRD      bmBit5
 485 #define I2C_STOP    bmBit6
 486 #define I2C_START   bmBit7
 487
 488 SFRX(I2DAT,         0x7FA6);
 489 /* 0x7FA7 reserved */
 490
 491 /******************************* Interrupts ********************************/
 492 SFRX(IVEC,          0x7FA8);
 493 /* Bit 0 read-only, always reads '0' */
 494 /* Bit 1 read-only, always reads '0' */
 495 #define IV0         bmBit2
 496 #define IV1         bmBit3
 497 #define IV2         bmBit4
 498 #define IV3         bmBit5
 499 #define IV4         bmBit6
 500 /* Bit 7 read-only, always reads '0' */
 501
 502 SFRX(IN07IRQ,       0x7FA9);
 503 #define IN0IR       bmBit0
 504 #define IN1IR       bmBit1
 505 #define IN2IR       bmBit2
 506 #define IN3IR       bmBit3
 507 #define IN4IR       bmBit4
 508 #define IN5IR       bmBit5
 509 #define IN6IR       bmBit6
 510 #define IN7IR       bmBit7
 511
 512 SFRX(OUT07IRQ,      0x7FAA);
 513 #define OUT0IR      bmBit0
 514 #define OUT1IR      bmBit1
 515 #define OUT2IR      bmBit2
 516 #define OUT3IR      bmBit3
 517 #define OUT4IR      bmBit4
 518 #define OUT5IR      bmBit5
 519 #define OUT6IR      bmBit6
 520 #define OUT7IR      bmBit7
 521
 522 SFRX(USBIRQ,        0x7FAB);
 523 #define SUDAVIR     bmBit0
 524 #define SOFIR       bmBit1
 525 #define SUTOKIR     bmBit2
 526 #define SUSPIR      bmBit3
 527 #define URESIR      bmBit4
 528 /* Bit 5 unused */
 529 /* Bit 6 unused */
 530 /* Bit 7 unused */
 531
 532 SFRX(IN07IEN,       0x7FAC);
 533 #define IN0IEN      bmBit0
 534 #define IN1IEN      bmBit1
 535 #define IN2IEN      bmBit2
 536 #define IN3IEN      bmBit3
 537 #define IN4IEN      bmBit4
 538 #define IN5IEN      bmBit5
 539 #define IN6IEN      bmBit6
 540 #define IN7IEN      bmBit7
 541
 542 SFRX(OUT07IEN,      0x7FAD);
 543 #define OUT0IEN     bmBit0
 544 #define OUT1IEN     bmBit1
 545 #define OUT2IEN     bmBit2
 546 #define OUT3IEN     bmBit3
 547 #define OUT4IEN     bmBit4
 548 #define OUT5IEN     bmBit5
 549 #define OUT6IEN     bmBit6
 550 #define OUT7IEN     bmBit7
 551
 552 SFRX(USBIEN,        0x7FAE);
 553 #define SUDAVIE     bmBit0
 554 #define SOFIE       bmBit1
 555 #define SUTOKIE     bmBit2
 556 #define SUSPIE      bmBit3
 557 #define URESIE      bmBit4
 558 /* Bit 5 unused */
 559 /* Bit 6 unused */
 560 /* Bit 7 unused */
 561
 562 SFRX(USBBAV,        0x7FAF);
 563 #define AVEN        bmBit0
 564 #define BPEN        bmBit1
 565 #define BPPULSE     bmBit2
 566 #define BREAK       bmBit3
 567 /* Bit 4 unused */
 568 /* Bit 5 unused */
 569 /* Bit 6 unused */
 570 /* Bit 7 unused */
 571
 572 /* 0x7FB0 reserved */
 573 /* 0x7FB1 reserved */
 574 SFRX(BPADDRH,       0x7FB2);
 575 SFRX(BPADDRL,       0x7FB3);
 576
 577 /****************************** Endpoints 0-7 ******************************/
 578 SFRX(EP0CS,         0x7FB4);
 579 #define EP0STALL    bmBit0
 580 #define HSNAK       bmBit1
 581 #define IN0BSY      bmBit2
 582 #define OUT0BSY     bmBit3
 583 /* Bit 4 unused */
 584 /* Bit 5 unused */
 585 /* Bit 6 unused */
 586 /* Bit 7 unused */
 587
 588 SFRX(IN0BC,         0x7FB5);
 589 SFRX(IN1CS,         0x7FB6);
 590 SFRX(IN1BC,         0x7FB7);
 591 SFRX(IN2CS,         0x7FB8);
 592 SFRX(IN2BC,         0x7FB9);
 593 SFRX(IN3CS,         0x7FBA);
 594 SFRX(IN3BC,         0x7FBB);
 595 SFRX(IN4CS,         0x7FBC);
 596 SFRX(IN4BC,         0x7FBD);
 597 SFRX(IN5CS,         0x7FBE);
 598 SFRX(IN5BC,         0x7FBF);
 599 SFRX(IN6CS,         0x7FC0);
 600 SFRX(IN6BC,         0x7FC1);
 601 SFRX(IN7CS,         0x7FC2);
 602 SFRX(IN7BC,         0x7FC3);
 603 /* 0x7FC4 reserved */
 604 SFRX(OUT0BC,        0x7FC5);
 605 SFRX(OUT1CS,        0x7FC6);
 606 SFRX(OUT1BC,        0x7FC7);
 607 SFRX(OUT2CS,        0x7FC8);
 608 SFRX(OUT2BC,        0x7FC9);
 609 SFRX(OUT3CS,        0x7FCA);
 610 SFRX(OUT3BC,        0x7FCB);
 611 SFRX(OUT4CS,        0x7FCC);
 612 SFRX(OUT4BC,        0x7FCD);
 613 SFRX(OUT5CS,        0x7FCE);
 614 SFRX(OUT5BC,        0x7FCF);
 615 SFRX(OUT6CS,        0x7FD0);
 616 SFRX(OUT6BC,        0x7FD1);
 617 SFRX(OUT7CS,        0x7FD2);
 618 SFRX(OUT7BC,        0x7FD3);
 619
 620 /* The INxSTALL, OUTxSTALL, INxBSY and OUTxBSY bits are the same for all
 621  * INxCS/OUTxCS registers. For better readability, we define them only once */
 622 #define EPSTALL     bmBit0
 623 #define EPBSY       bmBit1
 624
 625 /************************** Global USB Registers ***************************/
 626 SFRX(SUDPTRH,       0x7FD4);
 627 SFRX(SUDPTRL,       0x7FD5);
 628
 629 SFRX(USBCS,         0x7FD6);
 630 #define SIGRSUME    bmBit0
 631 #define RENUM       bmBit1
 632 #define DISCOE      bmBit2
 633 #define DISCON      bmBit3
 634 /* Bit 4 unused */
 635 /* Bit 5 unused */
 636 /* Bit 6 unused */
 637 #define WAKESRC     bmBit7
 638
 639 SFRX(TOGCTL,        0x7FD7);
 640 #define TOG_EP0     bmBit0
 641 #define TOG_EP1     bmBit1
 642 #define TOG_EP2     bmBit2
 643 /* Bit 3 is read-only, always reads '0' */
 644 #define TOG_IO      bmBit4
 645 #define TOG_R       bmBit5
 646 #define TOG_S       bmBit6
 647 #define TOG_Q       bmBit7
 648
 649 SFRX(USBFRAMEL,     0x7FD8);
 650 SFRX(USBFRAMEH,     0x7FD9);
 651 /* 0x7FDA reserved */
 652 SFRX(FNADDR,        0x7FDB);
 653 /* 0x7FDC reserved */
 654
 655 SFRX(USBPAIR,       0x7FDD);
 656 #define PR2IN       bmBit0
 657 #define PR4IN       bmBit1
 658 #define PR6IN       bmBit2
 659 #define PR2OUT      bmBit3
 660 #define PR4OUT      bmBit4
 661 #define PR6OUT      bmBit5
 662 /* Bit 6 unused */
 663 #define ISOSEND0    bmBit7
 664
 665 SFRX(IN07VAL,       0x7FDE);
 666 /* Bit 0 is read-only, always reads '1' */
 667 #define IN1VAL      bmBit1
 668 #define IN2VAL      bmBit2
 669 #define IN3VAL      bmBit3
 670 #define IN4VAL      bmBit4
 671 #define IN5VAL      bmBit5
 672 #define IN6VAL      bmBit6
 673 #define IN7VAL      bmBit7
 674
 675 SFRX(OUT07VAL,      0x7FDF);
 676 /* Bit 0 is read-only, always reads '1' */
 677 #define OUT1VAL     bmBit1
 678 #define OUT2VAL     bmBit2
 679 #define OUT3VAL     bmBit3
 680 #define OUT4VAL     bmBit4
 681 #define OUT5VAL     bmBit5
 682 #define OUT6VAL     bmBit6
 683 #define OUT7VAL     bmBit7
 684
 685 SFRX(INISOVAL,      0x7FE0);
 686 #define IN8VAL      bmBit0
 687 #define IN9VAL      bmBit1
 688 #define IN10VAL     bmBit2
 689 #define IN11VAL     bmBit3
 690 #define IN12VAL     bmBit4
 691 #define IN13VAL     bmBit5
 692 #define IN14VAL     bmBit6
 693 #define IN15VAL     bmBit7
 694
 695 SFRX(OUTISOVAL,     0x7FE1);
 696 #define OUT8VAL     bmBit0
 697 #define OUT9VAL     bmBit1
 698 #define OUT10VAL    bmBit2
 699 #define OUT11VAL    bmBit3
 700 #define OUT12VAL    bmBit4
 701 #define OUT13VAL    bmBit5
 702 #define OUT14VAL    bmBit6
 703 #define OUT15VAL    bmBit7
 704
 705 SFRX(FASTXFR,       0x7FE2);
 706 #define WMOD0       bmBit0
 707 #define WMOD1       bmBit1
 708 #define WPOL        bmBit2
 709 #define RMOD0       bmBit3
 710 #define RMOD1       bmBit4
 711 #define RPOL        bmBit5
 712 #define FBLK        bmBit6
 713 #define FISO        bmBit7
 714
 715 SFRX(AUTOPTRH,      0x7FE3);
 716 SFRX(AUTOPTRL,      0x7FE4);
 717 SFRX(AUTODATA,      0x7FE5);
 718 /* 0x7FE6 reserved */
 719 /* 0x7FE7 reserved */
 720
 721 /******************************* Setup Data ********************************/
 722 SFRX(SETUPDAT[8],   0x7FE8);
 723
 724 /************************* Isochronous FIFO sizes **************************/
 725 SFRX(OUT8ADDR,      0x7FF0);
 726 SFRX(OUT9ADDR,      0x7FF1);
 727 SFRX(OUT10ADDR,     0x7FF2);
 728 SFRX(OUT11ADDR,     0x7FF3);
 729 SFRX(OUT12ADDR,     0x7FF4);
 730 SFRX(OUT13ADDR,     0x7FF5);
 731 SFRX(OUT14ADDR,     0x7FF6);
 732 SFRX(OUT15ADDR,     0x7FF7);
 733
 734 SFRX(IN8ADDR,       0x7FF8);
 735 SFRX(IN9ADDR,       0x7FF9);
 736 SFRX(IN10ADDR,      0x7FFA);
 737 SFRX(IN11ADDR,      0x7FFB);
 738 SFRX(IN12ADDR,      0x7FFC);
 739 SFRX(IN13ADDR,      0x7FFD);
 740 SFRX(IN14ADDR,      0x7FFE);
 741 SFRX(IN15ADDR,      0x7FFF);
 742
 743 #endif