From ffbf763fc1f192fc31b0f86398bbf8263907eafa Mon Sep 17 00:00:00 2001 From: wilson Date: Thu, 20 May 2010 06:53:43 +0000 Subject: [PATCH] * config/mips/mips-dsp.md (add3, mips_add_s_): Add ISA_HAS_DSP condition. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159619 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 3 +++ gcc/config/mips/mips-dsp.md | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ecadc0204a7..4dce40331e4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -6,6 +6,9 @@ 2010-05-19 James E. Wilson + * config/mips/mips-dsp.md (add3, + mips_add_s_): Add ISA_HAS_DSP condition. + PR target/43764 * mips.c (mips_call_expr_from_insn): New arg second_call. Set it. (mips_annotate_pic_calls): Pass new arg to mips_call_expr_from_insn. diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md index dd2459ebcaf..9e02f7214f9 100644 --- a/gcc/config/mips/mips-dsp.md +++ b/gcc/config/mips/mips-dsp.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc. +;; Copyright (C) 2005, 2006, 2007, 2008, 2010 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -60,7 +60,7 @@ (match_operand:DSPV 2 "register_operand" "d"))) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])] - "" + "ISA_HAS_DSP" "add.\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -73,7 +73,7 @@ UNSPEC_ADDQ_S)) (set (reg:CCDSP CCDSP_OU_REGNUM) (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] - "" + "ISA_HAS_DSP" "add_s.\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) -- 2.11.4.GIT