From f4474f8cf55401f988412f2a30e8581d69fea307 Mon Sep 17 00:00:00 2001
From: jasonwucj <jasonwucj@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Sun, 4 Mar 2018 16:27:34 +0000
Subject: [PATCH] [NDS32] Refine load_multiple and store_multiple.

gcc/
	* config/nds32/nds32-protos.h
	(nds32_expand_load_multiple): New arguments.
	(nds32_expand_store_multiple): Ditto.
	(nds32_valid_multiple_load_store): Rename ...
	(nds32_valid_multiple_load_store_p): ... to this.
	* config/nds32/nds32-memory-manipulation.c
	(nds32_expand_load_multiple): Refine implementation.
	(nds32_expand_store_multiple): Ditto.
	* config/nds32/nds32-multiple.md
	(load_multiple): Update nds32_expand_load_multiple interface.
	(store_multiple): Update nds32_expand_store_multiple interface.
	* config/nds32/nds32-predicates.c
	(nds32_valid_multiple_load_store): Rename ...
	(nds32_valid_multiple_load_store_p): ... to this and refine
	implementation.
	* config/nds32/predicates.md
	(nds32_load_multiple_and_update_address_operation): New predicate.
	(nds32_store_multiple_and_update_address_operation): New predicate.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@258234 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog                                |   23 +
 gcc/config/nds32/nds32-memory-manipulation.c |   87 +-
 gcc/config/nds32/nds32-multiple.md           | 3580 +++++++++++++++++++++++++-
 gcc/config/nds32/nds32-predicates.c          |   44 +-
 gcc/config/nds32/nds32-protos.h              |    6 +-
 gcc/config/nds32/predicates.md               |   22 +-
 6 files changed, 3613 insertions(+), 149 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3b9fb4a292d..c5dffdaf882 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,4 +1,27 @@
 2018-03-04  Kito Cheng  <kito.cheng@gmail.com>
+	    Monk Chiang  <sh.chiang04@gmail.com>
+	    Chung-Ju Wu  <jasonwucj@gmail.com>
+
+	* config/nds32/nds32-protos.h
+	(nds32_expand_load_multiple): New arguments.
+	(nds32_expand_store_multiple): Ditto.
+	(nds32_valid_multiple_load_store): Rename ...
+	(nds32_valid_multiple_load_store_p): ... to this.
+	* config/nds32/nds32-memory-manipulation.c
+	(nds32_expand_load_multiple): Refine implementation.
+	(nds32_expand_store_multiple): Ditto.
+	* config/nds32/nds32-multiple.md
+	(load_multiple): Update nds32_expand_load_multiple interface.
+	(store_multiple): Update nds32_expand_store_multiple interface.
+	* config/nds32/nds32-predicates.c
+	(nds32_valid_multiple_load_store): Rename ...
+	(nds32_valid_multiple_load_store_p): ... to this and refine
+	implementation.
+	* config/nds32/predicates.md
+	(nds32_load_multiple_and_update_address_operation): New predicate.
+	(nds32_store_multiple_and_update_address_operation): New predicate.
+
+2018-03-04  Kito Cheng  <kito.cheng@gmail.com>
 	    Chung-Ju Wu  <jasonwucj@gmail.com>
 
 	* config/nds32/nds32.md (type): Add load_multiple and store_multiple.
diff --git a/gcc/config/nds32/nds32-memory-manipulation.c b/gcc/config/nds32/nds32-memory-manipulation.c
index 912a3e3dbb1..da01fc60c21 100644
--- a/gcc/config/nds32/nds32-memory-manipulation.c
+++ b/gcc/config/nds32/nds32-memory-manipulation.c
@@ -40,16 +40,50 @@
    Check nds32-multiple.md file for the patterns.  */
 rtx
 nds32_expand_load_multiple (int base_regno, int count,
-			    rtx base_addr, rtx basemem)
+			    rtx base_addr, rtx basemem,
+			    bool update_base_reg_p,
+			    rtx *update_base_reg)
 {
   int par_index;
   int offset;
+  int start_idx;
   rtx result;
   rtx new_addr, mem, reg;
 
+  /* Generate a unaligned load to prevent load instruction pull out from
+     parallel, and then it will generate lwi, and lose unaligned acces */
+  if (count == 1)
+    {
+      reg = gen_rtx_REG (SImode, base_regno);
+      if (update_base_reg_p)
+	{
+	  *update_base_reg = gen_reg_rtx (SImode);
+	  return gen_unaligned_load_update_base_w (*update_base_reg, reg, base_addr);
+	}
+      else
+	return gen_unaligned_load_w (reg, gen_rtx_MEM (SImode, base_addr));
+    }
+
   /* Create the pattern that is presented in nds32-multiple.md.  */
+  if (update_base_reg_p)
+    {
+      result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
+      start_idx = 1;
+    }
+  else
+    {
+      result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+      start_idx = 0;
+    }
+
+  if (update_base_reg_p)
+    {
+      offset           = count * 4;
+      new_addr         = plus_constant (Pmode, base_addr, offset);
+      *update_base_reg = gen_reg_rtx (SImode);
 
-  result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+      XVECEXP (result, 0, 0) = gen_rtx_SET (*update_base_reg, new_addr);
+    }
 
   for (par_index = 0; par_index < count; par_index++)
     {
@@ -60,7 +94,7 @@ nds32_expand_load_multiple (int base_regno, int count,
 					       new_addr, offset);
       reg      = gen_rtx_REG (SImode, base_regno + par_index);
 
-      XVECEXP (result, 0, par_index) = gen_rtx_SET (reg, mem);
+      XVECEXP (result, 0, (par_index + start_idx)) = gen_rtx_SET (reg, mem);
     }
 
   return result;
@@ -68,16 +102,49 @@ nds32_expand_load_multiple (int base_regno, int count,
 
 rtx
 nds32_expand_store_multiple (int base_regno, int count,
-			     rtx base_addr, rtx basemem)
+			     rtx base_addr, rtx basemem,
+			     bool update_base_reg_p,
+			     rtx *update_base_reg)
 {
   int par_index;
   int offset;
+  int start_idx;
   rtx result;
   rtx new_addr, mem, reg;
 
+  if (count == 1)
+    {
+      reg = gen_rtx_REG (SImode, base_regno);
+      if (update_base_reg_p)
+	{
+	  *update_base_reg = gen_reg_rtx (SImode);
+	  return gen_unaligned_store_update_base_w (*update_base_reg, base_addr, reg);
+	}
+      else
+	return gen_unaligned_store_w (gen_rtx_MEM (SImode, base_addr), reg);
+    }
+
   /* Create the pattern that is presented in nds32-multiple.md.  */
 
-  result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+  if (update_base_reg_p)
+    {
+      result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
+      start_idx = 1;
+    }
+  else
+    {
+      result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+      start_idx = 0;
+    }
+
+  if (update_base_reg_p)
+    {
+      offset           = count * 4;
+      new_addr         = plus_constant (Pmode, base_addr, offset);
+      *update_base_reg = gen_reg_rtx (SImode);
+
+      XVECEXP (result, 0, 0) = gen_rtx_SET (*update_base_reg, new_addr);
+    }
 
   for (par_index = 0; par_index < count; par_index++)
     {
@@ -88,7 +155,7 @@ nds32_expand_store_multiple (int base_regno, int count,
 					       new_addr, offset);
       reg      = gen_rtx_REG (SImode, base_regno + par_index);
 
-      XVECEXP (result, 0, par_index) = gen_rtx_SET (mem, reg);
+      XVECEXP (result, 0, par_index + start_idx) = gen_rtx_SET (mem, reg);
     }
 
   return result;
@@ -135,8 +202,12 @@ nds32_expand_movmemqi (rtx dstmem, rtx srcmem, rtx total_bytes, rtx alignment)
 
   out_words = in_words = INTVAL (total_bytes) / UNITS_PER_WORD;
 
-  emit_insn (nds32_expand_load_multiple (0, in_words, src_base_reg, srcmem));
-  emit_insn (nds32_expand_store_multiple (0, out_words, dst_base_reg, dstmem));
+  emit_insn (
+    nds32_expand_load_multiple (0, in_words, src_base_reg,
+				srcmem, false, NULL));
+  emit_insn (
+    nds32_expand_store_multiple (0, out_words, dst_base_reg,
+				 dstmem, false, NULL));
 
   /* Successfully create patterns, return 1.  */
   return 1;
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
index a16709f3f91..c0265914ec8 100644
--- a/gcc/config/nds32/nds32-multiple.md
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -71,201 +71,3523 @@
 					    INTVAL (operands[2]),
 					    force_reg (SImode,
 						       XEXP (operands[1], 0)),
-					    operands[1]);
+					    operands[1],
+					    false, NULL);
 })
 
 ;; Ordinary Load Multiple.
+(define_insn "*lmw_bim_si25"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 100)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 72))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 76))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 80))))
+     (set (match_operand:SI 24 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 84))))
+     (set (match_operand:SI 25 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 88))))
+     (set (match_operand:SI 26 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 92))))
+     (set (match_operand:SI 27 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 96))))])]
+  "(XVECLEN (operands[0], 0) == 26)"
+  "lmw.bim\t%3, [%1], %27, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "25")
+   (set_attr "length"             "4")]
+)
 
-(define_insn "*lmwsi8"
-  [(match_parallel 0 "nds32_load_multiple_operation"
-    [(set (match_operand:SI 2 "register_operand" "")
-	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+(define_insn "*lmw_bim_si24"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 96)))
      (set (match_operand:SI 3 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+	  (mem:SI (match_dup 2)))
      (set (match_operand:SI 4 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
      (set (match_operand:SI 5 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
      (set (match_operand:SI 6 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
      (set (match_operand:SI 7 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
      (set (match_operand:SI 8 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
      (set (match_operand:SI 9 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
-  "(XVECLEN (operands[0], 0) == 8)"
-  "lmw.bi\t%2, [%1], %9, 0x0"
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 72))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 76))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 80))))
+     (set (match_operand:SI 24 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 84))))
+     (set (match_operand:SI 25 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 88))))
+     (set (match_operand:SI 26 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 92))))])]
+  "(XVECLEN (operands[0], 0) == 25)"
+  "lmw.bim\t%3, [%1], %26, 0x0"
   [(set_attr "type"   "load_multiple")
-   (set_attr "combo"              "8")
+   (set_attr "combo"             "24")
    (set_attr "length"             "4")]
 )
 
-(define_insn "*lmwsi7"
-  [(match_parallel 0 "nds32_load_multiple_operation"
-    [(set (match_operand:SI 2 "register_operand" "")
-	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+(define_insn "*lmw_bim_si23"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 92)))
      (set (match_operand:SI 3 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+	  (mem:SI (match_dup 2)))
      (set (match_operand:SI 4 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
      (set (match_operand:SI 5 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
      (set (match_operand:SI 6 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
      (set (match_operand:SI 7 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
      (set (match_operand:SI 8 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
-  "(XVECLEN (operands[0], 0) == 7)"
-  "lmw.bi\t%2, [%1], %8, 0x0"
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 72))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 76))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 80))))
+     (set (match_operand:SI 24 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 84))))
+     (set (match_operand:SI 25 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 88))))])]
+  "(XVECLEN (operands[0], 0) == 24)"
+  "lmw.bim\t%3, [%1], %25, 0x0"
   [(set_attr "type"   "load_multiple")
-   (set_attr "combo"              "7")
+   (set_attr "combo"             "23")
    (set_attr "length"             "4")]
 )
 
-(define_insn "*lmwsi6"
-  [(match_parallel 0 "nds32_load_multiple_operation"
-    [(set (match_operand:SI 2 "register_operand" "")
-	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+(define_insn "*lmw_bim_si22"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 88)))
      (set (match_operand:SI 3 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+	  (mem:SI (match_dup 2)))
      (set (match_operand:SI 4 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
      (set (match_operand:SI 5 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
      (set (match_operand:SI 6 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
      (set (match_operand:SI 7 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
-  "(XVECLEN (operands[0], 0) == 6)"
-  "lmw.bi\t%2, [%1], %7, 0x0"
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 72))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 76))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 80))))
+     (set (match_operand:SI 24 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 84))))])]
+  "(XVECLEN (operands[0], 0) == 23)"
+  "lmw.bim\t%3, [%1], %24, 0x0"
   [(set_attr "type"   "load_multiple")
-   (set_attr "combo"              "6")
+   (set_attr "combo"             "22")
    (set_attr "length"             "4")]
 )
 
-(define_insn "*lmwsi5"
-  [(match_parallel 0 "nds32_load_multiple_operation"
-    [(set (match_operand:SI 2 "register_operand" "")
-	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+(define_insn "*lmw_bim_si21"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 84)))
      (set (match_operand:SI 3 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+	  (mem:SI (match_dup 2)))
      (set (match_operand:SI 4 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
      (set (match_operand:SI 5 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
      (set (match_operand:SI 6 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
-  "(XVECLEN (operands[0], 0) == 5)"
-  "lmw.bi\t%2, [%1], %6, 0x0"
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 72))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 76))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 80))))])]
+  "(XVECLEN (operands[0], 0) == 22)"
+  "lmw.bim\t%3, [%1], %23, 0x0"
   [(set_attr "type"   "load_multiple")
-   (set_attr "combo"              "5")
+   (set_attr "combo"             "21")
    (set_attr "length"             "4")]
 )
 
-(define_insn "*lmwsi4"
-  [(match_parallel 0 "nds32_load_multiple_operation"
-    [(set (match_operand:SI 2 "register_operand" "")
-	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+(define_insn "*lmw_bim_si20"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 80)))
      (set (match_operand:SI 3 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+	  (mem:SI (match_dup 2)))
      (set (match_operand:SI 4 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
      (set (match_operand:SI 5 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
-  "(XVECLEN (operands[0], 0) == 4)"
-  "lmw.bi\t%2, [%1], %5, 0x0"
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 72))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 76))))])]
+  "(XVECLEN (operands[0], 0) == 21)"
+  "lmw.bim\t%3, [%1], %22, 0x0"
   [(set_attr "type"   "load_multiple")
-   (set_attr "combo"              "4")
+   (set_attr "combo"             "20")
    (set_attr "length"             "4")]
 )
 
-(define_insn "*lmwsi3"
-  [(match_parallel 0 "nds32_load_multiple_operation"
-    [(set (match_operand:SI 2 "register_operand" "")
-	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+(define_insn "*lmw_bim_si19"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 76)))
      (set (match_operand:SI 3 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+	  (mem:SI (match_dup 2)))
      (set (match_operand:SI 4 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
-  "(XVECLEN (operands[0], 0) == 3)"
-  "lmw.bi\t%2, [%1], %4, 0x0"
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 72))))])]
+  "(XVECLEN (operands[0], 0) == 20)"
+  "lmw.bim\t%3, [%1], %21, 0x0"
   [(set_attr "type"   "load_multiple")
-   (set_attr "combo"              "3")
+   (set_attr "combo"             "19")
    (set_attr "length"             "4")]
 )
 
-(define_insn "*lmwsi2"
-  [(match_parallel 0 "nds32_load_multiple_operation"
-    [(set (match_operand:SI 2 "register_operand" "")
-	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+(define_insn "*lmw_bim_si18"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 72)))
      (set (match_operand:SI 3 "register_operand" "")
-	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
-  "(XVECLEN (operands[0], 0) == 2)"
-  "lmw.bi\t%2, [%1], %3, 0x0"
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 68))))])]
+  "(XVECLEN (operands[0], 0) == 19)"
+  "lmw.bim\t%3, [%1], %20, 0x0"
   [(set_attr "type"   "load_multiple")
-   (set_attr "combo"              "2")
+   (set_attr "combo"             "18")
    (set_attr "length"             "4")]
 )
 
+(define_insn "*lmw_bim_si17"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 68)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 64))))])]
+  "(XVECLEN (operands[0], 0) == 18)"
+  "lmw.bim\t%3, [%1], %19, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "17")
+   (set_attr "length"             "4")]
+)
 
-;; Store Multiple Insns.
-;;
-;; operands[0] is the first memory location.
-;; opernads[1] is the first of the consecutive registers.
-;; operands[2] is the number of consecutive registers.
+(define_insn "*lmw_bim_si16"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 64)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 60))))])]
+  "(XVECLEN (operands[0], 0) == 17)"
+  "lmw.bim\t%3, [%1], %18, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "16")
+   (set_attr "length"             "4")]
+)
 
-(define_expand "store_multiple"
-  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
-			  (match_operand:SI 1 "" ""))
-		     (use (match_operand:SI 2 "" ""))])]
-  ""
-{
-  int maximum;
+(define_insn "*lmw_bim_si15"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 60)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 56))))])]
+  "(XVECLEN (operands[0], 0) == 16)"
+  "lmw.bim\t%3, [%1], %17, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "15")
+   (set_attr "length"             "4")]
+)
 
-  /* Because reduced-set regsiters has few registers
-     (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
-     be used for register allocation),
-     using 8 registers for store_multiple may easily consume all of them.
-     It makes register allocation/spilling hard to work.
-     So we only allow maximum=4 registers for store_multiple
-     under reduced-set registers.  */
-  if (TARGET_REDUCED_REGS)
-    maximum = 4;
-  else
-    maximum = 8;
+(define_insn "*lmw_bim_si14"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 56)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 52))))])]
+  "(XVECLEN (operands[0], 0) == 15)"
+  "lmw.bim\t%3, [%1], %16, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "14")
+   (set_attr "length"             "4")]
+)
 
-  /* Here are the conditions that must be all passed,
-     otherwise we have to FAIL this rtx generation:
-       1. The number of consecutive registers must be integer.
-       2. Maximum 4 or 8 registers for smw.bi instruction
-	  (based on this nds32-multiple.md design).
-       3. Minimum 2 registers for smw.bi instruction
-	  (based on this nds32-multiple.md design).
-       4. operands[0] must be memory for sure.
-       5. operands[1] must be register for sure.
-       6. operands[0] is not volatile memory access.
-       7. Do not cross $r15 register because it is not allocatable.  */
-  if (GET_CODE (operands[2]) != CONST_INT
-      || INTVAL (operands[2]) > maximum
-      || INTVAL (operands[2]) < 2
-      || GET_CODE (operands[0]) != MEM
-      || GET_CODE (operands[1]) != REG
-      || MEM_VOLATILE_P (operands[0])
-      || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
-    FAIL;
+(define_insn "*lmw_bim_si13"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 52)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 48))))])]
+  "(XVECLEN (operands[0], 0) == 14)"
+  "lmw.bim\t%3, [%1], %15, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "13")
+   (set_attr "length"             "4")]
+)
 
-  /* For (mem addr), we force_reg on addr here,
-     so that nds32_expand_store_multiple can easily use it.  */
-  operands[3] = nds32_expand_store_multiple (REGNO (operands[1]),
-					     INTVAL (operands[2]),
-					     force_reg (SImode,
-							XEXP (operands[0], 0)),
-					     operands[0]);
-})
+(define_insn "*lmw_bim_si12"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 48)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 44))))])]
+  "(XVECLEN (operands[0], 0) == 13)"
+  "lmw.bim\t%3, [%1], %14, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "12")
+   (set_attr "length"             "4")]
+)
 
-;; Ordinary Store Multiple.
+(define_insn "*lmw_bim_si11"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 44)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 40))))])]
+  "(XVECLEN (operands[0], 0) == 12)"
+  "lmw.bim\t%3, [%1], %13, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "11")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si10"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 40)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 36))))])]
+  "(XVECLEN (operands[0], 0) == 11)"
+  "lmw.bim\t%3, [%1], %12, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "10")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si9"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 36)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 32))))])]
+  "(XVECLEN (operands[0], 0) == 10)"
+  "lmw.bim\t%3, [%1], %11, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "9")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si8"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 32)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 28))))])]
+  "(XVECLEN (operands[0], 0) == 9)"
+  "lmw.bim\t%3, [%1], %10, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "8")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si7"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 28)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 24))))])]
+  "(XVECLEN (operands[0], 0) == 8)"
+  "lmw.bim\t%3, [%1], %9, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "7")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si6"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 24)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 20))))])]
+  "(XVECLEN (operands[0], 0) == 7)"
+  "lmw.bim\t%3, [%1], %8, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "6")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si5"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 20)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 16))))])]
+  "(XVECLEN (operands[0], 0) == 6)"
+  "lmw.bim\t%3, [%1], %7, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "5")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si4"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 16)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 12))))])]
+  "(XVECLEN (operands[0], 0) == 5)"
+  "lmw.bim\t%3, [%1], %6, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "4")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si3"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 12)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 8))))])]
+  "(XVECLEN (operands[0], 0) == 4)"
+  "lmw.bim\t%3, [%1], %5, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "3")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmw_bim_si2"
+  [(match_parallel 0 "nds32_load_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 8)))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (match_dup 2)))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 2) (const_int 4))))])]
+  "(XVECLEN (operands[0], 0) == 3)"
+  "lmw.bim\t%3, [%1], %4, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "2")
+   (set_attr "length"             "4")]
+)
+
+(define_expand "unaligned_load_update_base_w"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "")
+		   (plus:SI (match_operand:SI 2 "register_operand" "") (const_int 4)))
+	      (set (match_operand:SI 1 "register_operand" "")
+		   (unspec:SI [(mem:SI (match_dup 2))] UNSPEC_UALOAD_W))])]
+  ""
+{
+  emit_insn (gen_unaligned_load_w (operands[1], gen_rtx_MEM (SImode, operands[2])));
+  emit_insn (gen_addsi3 (operands[0], operands[2], gen_int_mode (4, Pmode)));
+  DONE;
+}
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "1")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi25"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 72))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 76))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 80))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 84))))
+     (set (match_operand:SI 24 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 88))))
+     (set (match_operand:SI 25 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 92))))
+     (set (match_operand:SI 26 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 96))))])]
+  "(XVECLEN (operands[0], 0) == 25)"
+  "lmw.bi\t%2, [%1], %26, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "25")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi24"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 72))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 76))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 80))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 84))))
+     (set (match_operand:SI 24 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 88))))
+     (set (match_operand:SI 25 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 92))))])]
+  "(XVECLEN (operands[0], 0) == 24)"
+  "lmw.bi\t%2, [%1], %25, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "24")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi23"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 72))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 76))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 80))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 84))))
+     (set (match_operand:SI 24 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 88))))])]
+  "(XVECLEN (operands[0], 0) == 23)"
+  "lmw.bi\t%2, [%1], %24, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "23")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi22"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 72))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 76))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 80))))
+     (set (match_operand:SI 23 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 84))))])]
+  "(XVECLEN (operands[0], 0) == 22)"
+  "lmw.bi\t%2, [%1], %23, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "22")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi21"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 72))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 76))))
+     (set (match_operand:SI 22 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 80))))])]
+  "(XVECLEN (operands[0], 0) == 21)"
+  "lmw.bi\t%2, [%1], %22, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "21")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi20"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 72))))
+     (set (match_operand:SI 21 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 76))))])]
+  "(XVECLEN (operands[0], 0) == 20)"
+  "lmw.bi\t%2, [%1], %21, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "20")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi19"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))
+     (set (match_operand:SI 20 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 72))))])]
+  "(XVECLEN (operands[0], 0) == 19)"
+  "lmw.bi\t%2, [%1], %20, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "19")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi18"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))
+     (set (match_operand:SI 19 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 68))))])]
+  "(XVECLEN (operands[0], 0) == 18)"
+  "lmw.bi\t%2, [%1], %19, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "18")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi17"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))
+     (set (match_operand:SI 18 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 64))))])]
+  "(XVECLEN (operands[0], 0) == 17)"
+  "lmw.bi\t%2, [%1], %18, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "17")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi16"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))
+     (set (match_operand:SI 17 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 60))))])]
+  "(XVECLEN (operands[0], 0) == 16)"
+  "lmw.bi\t%2, [%1], %17, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "16")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi15"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))
+     (set (match_operand:SI 16 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 56))))])]
+  "(XVECLEN (operands[0], 0) == 15)"
+  "lmw.bi\t%2, [%1], %16, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "15")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi14"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))
+     (set (match_operand:SI 15 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 52))))])]
+  "(XVECLEN (operands[0], 0) == 14)"
+  "lmw.bi\t%2, [%1], %15, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "14")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi13"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))
+     (set (match_operand:SI 14 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 48))))])]
+  "(XVECLEN (operands[0], 0) == 13)"
+  "lmw.bi\t%2, [%1], %14, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "13")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi12"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))
+     (set (match_operand:SI 13 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 44))))])]
+  "(XVECLEN (operands[0], 0) == 12)"
+  "lmw.bi\t%2, [%1], %13, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "12")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi11"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))
+     (set (match_operand:SI 12 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 40))))])]
+  "(XVECLEN (operands[0], 0) == 11)"
+  "lmw.bi\t%2, [%1], %12, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "11")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi10"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))
+     (set (match_operand:SI 11 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 36))))])]
+  "(XVECLEN (operands[0], 0) == 10)"
+  "lmw.bi\t%2, [%1], %11, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"             "10")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi9"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))
+     (set (match_operand:SI 10 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 32))))])]
+  "(XVECLEN (operands[0], 0) == 9)"
+  "lmw.bi\t%2, [%1], %10, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "9")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi8"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))
+     (set (match_operand:SI 9 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
+  "(XVECLEN (operands[0], 0) == 8)"
+  "lmw.bi\t%2, [%1], %9, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "8")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi7"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))
+     (set (match_operand:SI 8 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
+  "(XVECLEN (operands[0], 0) == 7)"
+  "lmw.bi\t%2, [%1], %8, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "7")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi6"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))
+     (set (match_operand:SI 7 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
+  "(XVECLEN (operands[0], 0) == 6)"
+  "lmw.bi\t%2, [%1], %7, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "6")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi5"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))
+     (set (match_operand:SI 6 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
+  "(XVECLEN (operands[0], 0) == 5)"
+  "lmw.bi\t%2, [%1], %6, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "5")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi4"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))
+     (set (match_operand:SI 5 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
+  "(XVECLEN (operands[0], 0) == 4)"
+  "lmw.bi\t%2, [%1], %5, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "4")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi3"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))
+     (set (match_operand:SI 4 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
+  "(XVECLEN (operands[0], 0) == 3)"
+  "lmw.bi\t%2, [%1], %4, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "3")
+   (set_attr "length"             "4")]
+)
+
+(define_insn "*lmwsi2"
+  [(match_parallel 0 "nds32_load_multiple_operation"
+    [(set (match_operand:SI 2 "register_operand" "")
+	  (mem:SI (match_operand:SI 1 "register_operand" "r")))
+     (set (match_operand:SI 3 "register_operand" "")
+	  (mem:SI (plus:SI (match_dup 1) (const_int 4))))])]
+  "(XVECLEN (operands[0], 0) == 2)"
+  "lmw.bi\t%2, [%1], %3, 0x0"
+  [(set_attr "type"   "load_multiple")
+   (set_attr "combo"              "2")
+   (set_attr "length"             "4")]
+)
+
+;; Store Multiple Insns.
+;;
+;; operands[0] is the first memory location.
+;; opernads[1] is the first of the consecutive registers.
+;; operands[2] is the number of consecutive registers.
+
+(define_expand "store_multiple"
+  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))
+		     (use (match_operand:SI 2 "" ""))])]
+  ""
+{
+  int maximum;
+
+  /* Because reduced-set regsiters has few registers
+     (r0~r5, r6~10, r15, r28~r31, where 'r15' and 'r28~r31' cannot
+     be used for register allocation),
+     using 8 registers for store_multiple may easily consume all of them.
+     It makes register allocation/spilling hard to work.
+     So we only allow maximum=4 registers for store_multiple
+     under reduced-set registers.  */
+  if (TARGET_REDUCED_REGS)
+    maximum = 4;
+  else
+    maximum = 8;
+
+  /* Here are the conditions that must be all passed,
+     otherwise we have to FAIL this rtx generation:
+       1. The number of consecutive registers must be integer.
+       2. Maximum 4 or 8 registers for smw.bi instruction
+	  (based on this nds32-multiple.md design).
+       3. Minimum 2 registers for smw.bi instruction
+	  (based on this nds32-multiple.md design).
+       4. operands[0] must be memory for sure.
+       5. operands[1] must be register for sure.
+       6. operands[0] is not volatile memory access.
+       7. Do not cross $r15 register because it is not allocatable.  */
+  if (GET_CODE (operands[2]) != CONST_INT
+      || INTVAL (operands[2]) > maximum
+      || INTVAL (operands[2]) < 2
+      || GET_CODE (operands[0]) != MEM
+      || GET_CODE (operands[1]) != REG
+      || MEM_VOLATILE_P (operands[0])
+      || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
+    FAIL;
+
+  /* For (mem addr), we force_reg on addr here,
+     so that nds32_expand_store_multiple can easily use it.  */
+  operands[3] = nds32_expand_store_multiple (REGNO (operands[1]),
+					     INTVAL (operands[2]),
+					     force_reg (SImode,
+							XEXP (operands[0], 0)),
+					     operands[0],
+					     false, NULL);
+})
+
+;; Ordinary Store Multiple.
+(define_insn "*stm_bim_si25"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 100)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 72)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 76)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 80)))
+	  (match_operand:SI 23 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 84)))
+	  (match_operand:SI 24 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 88)))
+	  (match_operand:SI 25 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 92)))
+	  (match_operand:SI 26 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 96)))
+	  (match_operand:SI 27 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 26)"
+  "smw.bim\t%3, [%1], %27, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "25")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si24"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 96)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 72)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 76)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 80)))
+	  (match_operand:SI 23 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 84)))
+	  (match_operand:SI 24 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 88)))
+	  (match_operand:SI 25 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 92)))
+	  (match_operand:SI 26 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 25)"
+  "smw.bim\t%3, [%1], %26, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "24")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si23"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 92)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 72)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 76)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 80)))
+	  (match_operand:SI 23 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 84)))
+	  (match_operand:SI 24 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 88)))
+	  (match_operand:SI 25 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 24)"
+  "smw.bim\t%3, [%1], %25, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "23")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si22"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 88)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 72)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 76)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 80)))
+	  (match_operand:SI 23 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 84)))
+	  (match_operand:SI 24 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 23)"
+  "smw.bim\t%3, [%1], %24, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "22")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si21"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 84)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 72)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 76)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 80)))
+	  (match_operand:SI 23 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 22)"
+  "smw.bim\t%3, [%1], %23, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "21")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si20"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 80)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 72)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 76)))
+	  (match_operand:SI 22 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 21)"
+  "smw.bim\t%3, [%1], %22, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "20")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si19"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 76)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 72)))
+	  (match_operand:SI 21 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 20)"
+  "smw.bim\t%3, [%1], %21, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "19")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si18"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 72)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 68)))
+	  (match_operand:SI 20 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 19)"
+  "smw.bim\t%3, [%1], %20, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "18")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si17"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 68)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 64)))
+	  (match_operand:SI 19 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 18)"
+  "smw.bim\t%3, [%1], %19, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "17")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si16"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 64)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 60)))
+	  (match_operand:SI 18 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 17)"
+  "smw.bim\t%3, [%1], %18, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "16")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si15"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 60)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 56)))
+	  (match_operand:SI 17 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 16)"
+  "smw.bim\t%3, [%1], %17, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "15")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si14"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 56)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 52)))
+	  (match_operand:SI 16 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 15)"
+  "smw.bim\t%3, [%1], %16, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "14")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si13"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 52)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 48)))
+	  (match_operand:SI 15 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 14)"
+  "smw.bim\t%3, [%1], %15, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "13")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si12"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 48)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 44)))
+	  (match_operand:SI 14 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 13)"
+  "smw.bim\t%3, [%1], %14, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "12")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si11"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 44)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 40)))
+	  (match_operand:SI 13 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 12)"
+  "smw.bim\t%3, [%1], %13, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "11")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si10"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 40)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 36)))
+	  (match_operand:SI 12 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 11)"
+  "smw.bim\t%3, [%1], %12, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "10")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si9"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 36)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 32)))
+	  (match_operand:SI 11 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 10)"
+  "smw.bim\t%3, [%1], %11, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "9")
+   (set_attr "length"              "4")]
+)
+
+
+(define_insn "*stm_bim_si8"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 32)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 28)))
+	  (match_operand:SI 10 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 9)"
+  "smw.bim\t%3, [%1], %10, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "8")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si7"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 28)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 24)))
+	  (match_operand:SI 9 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 8)"
+  "smw.bim\t%3, [%1], %9, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "7")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si6"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 24)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 20)))
+	  (match_operand:SI 8 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 7)"
+  "smw.bim\t%3, [%1], %8, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "6")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si5"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 20)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 16)))
+	  (match_operand:SI 7 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 6)"
+  "smw.bim\t%3, [%1], %7, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "5")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si4"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 16)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 12)))
+	  (match_operand:SI 6 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 5)"
+  "smw.bim\t%3, [%1], %6, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "4")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si3"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 12)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 8)))
+	  (match_operand:SI 5 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 4)"
+  "smw.bim\t%3, [%1], %5, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "3")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stm_bim_si2"
+  [(match_parallel 0 "nds32_store_multiple_and_update_address_operation"
+    [(set (match_operand:SI 1 "register_operand" "=r")
+	  (plus:SI (match_operand:SI 2 "register_operand" "1") (const_int 8)))
+     (set (mem:SI (match_dup 2))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 2) (const_int 4)))
+	  (match_operand:SI 4 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 3)"
+  "smw.bim\t%3, [%1], %4, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "2")
+   (set_attr "length"              "4")]
+)
+
+(define_expand "unaligned_store_update_base_w"
+  [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
+		   (plus:SI (match_operand:SI 1 "register_operand" "0") (const_int 4)))
+	      (set (mem:SI (match_dup 1))
+		   (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_UASTORE_W))])]
+  ""
+{
+  emit_insn (gen_unaligned_store_w (gen_rtx_MEM (SImode, operands[1]), operands[2]));
+  emit_insn (gen_addsi3 (operands[0], operands[1], gen_int_mode (4, Pmode)));
+  DONE;
+}
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "1")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi25"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 72)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 76)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 80)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 84)))
+	  (match_operand:SI 23 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 88)))
+	  (match_operand:SI 24 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 92)))
+	  (match_operand:SI 25 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 96)))
+	  (match_operand:SI 26 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 25)"
+  "smw.bi\t%2, [%1], %26, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "25")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi24"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 72)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 76)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 80)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 84)))
+	  (match_operand:SI 23 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 88)))
+	  (match_operand:SI 24 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 92)))
+	  (match_operand:SI 25 "register_operand" ""))
+])]
+  "(XVECLEN (operands[0], 0) == 24)"
+  "smw.bi\t%2, [%1], %25, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "24")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi23"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 72)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 76)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 80)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 84)))
+	  (match_operand:SI 23 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 88)))
+	  (match_operand:SI 24 "register_operand" ""))
+])]
+  "(XVECLEN (operands[0], 0) == 23)"
+  "smw.bi\t%2, [%1], %24, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "23")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi22"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 72)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 76)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 80)))
+	  (match_operand:SI 22 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 84)))
+	  (match_operand:SI 23 "register_operand" ""))
+])]
+  "(XVECLEN (operands[0], 0) == 22)"
+  "smw.bi\t%2, [%1], %23, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "22")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi21"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 72)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 76)))
+	  (match_operand:SI 21 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 80)))
+	  (match_operand:SI 22 "register_operand" ""))
+])]
+  "(XVECLEN (operands[0], 0) == 21)"
+  "smw.bi\t%2, [%1], %22, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "21")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi20"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 72)))
+	  (match_operand:SI 20 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 76)))
+	  (match_operand:SI 21 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 20)"
+  "smw.bi\t%2, [%1], %21, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "20")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi19"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 72)))
+	  (match_operand:SI 20 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 19)"
+  "smw.bi\t%2, [%1], %20, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "19")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi18"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 68)))
+	  (match_operand:SI 19 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 18)"
+  "smw.bi\t%2, [%1], %19, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "18")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi17"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 64)))
+	  (match_operand:SI 18 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 17)"
+  "smw.bi\t%2, [%1], %18, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "17")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi16"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 60)))
+	  (match_operand:SI 17 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 16)"
+  "smw.bi\t%2, [%1], %17, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "16")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi15"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 56)))
+	  (match_operand:SI 16 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 15)"
+  "smw.bi\t%2, [%1], %16, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "15")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi14"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 52)))
+	  (match_operand:SI 15 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 14)"
+  "smw.bi\t%2, [%1], %15, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "14")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi13"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 48)))
+	  (match_operand:SI 14 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 13)"
+  "smw.bi\t%2, [%1], %14, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "13")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi12"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 44)))
+	  (match_operand:SI 13 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 12)"
+  "smw.bi\t%2, [%1], %13, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "12")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi11"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 40)))
+	  (match_operand:SI 12 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 11)"
+  "smw.bi\t%2, [%1], %12, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "11")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi10"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 36)))
+	  (match_operand:SI 11 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 10)"
+  "smw.bi\t%2, [%1], %11, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"              "10")
+   (set_attr "length"              "4")]
+)
+
+(define_insn "*stmsi9"
+  [(match_parallel 0 "nds32_store_multiple_operation"
+    [(set (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	  (match_operand:SI 2  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
+	  (match_operand:SI 3  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
+	  (match_operand:SI 4  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
+	  (match_operand:SI 5  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
+	  (match_operand:SI 6  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
+	  (match_operand:SI 7  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
+	  (match_operand:SI 8  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
+	  (match_operand:SI 9  "register_operand" ""))
+     (set (mem:SI (plus:SI (match_dup 1) (const_int 32)))
+	  (match_operand:SI 10 "register_operand" ""))])]
+  "(XVECLEN (operands[0], 0) == 9)"
+  "smw.bi\t%2, [%1], %10, 0x0"
+  [(set_attr "type"   "store_multiple")
+   (set_attr "combo"               "9")
+   (set_attr "length"              "4")]
+)
 
 (define_insn "*stmsi8"
   [(match_parallel 0 "nds32_store_multiple_operation"
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index 341f8b6f1cd..c54eefba027 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -101,21 +101,33 @@ nds32_consecutive_registers_load_store_p (rtx op,
    We have to extract reg and mem of every element and
    check if the information is valid for multiple load/store operation.  */
 bool
-nds32_valid_multiple_load_store (rtx op, bool load_p)
+nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
 {
   int count;
   int first_elt_regno;
+  int update_base_elt_idx;
+  int offset;
   rtx elt;
+  rtx update_base;
 
-  /* Get the counts of elements in the parallel rtx.  */
-  count = XVECLEN (op, 0);
-  /* Pick up the first element.  */
-  elt = XVECEXP (op, 0, 0);
+  /* Get the counts of elements in the parallel rtx.
+     Last one is update base register if bim_p.
+     and pick up the first element.  */
+  if (bim_p)
+    {
+      count = XVECLEN (op, 0) - 1;
+      elt = XVECEXP (op, 0, 1);
+    }
+  else
+    {
+      count = XVECLEN (op, 0);
+      elt = XVECEXP (op, 0, 0);
+    }
 
   /* Perform some quick check for the first element in the parallel rtx.  */
   if (GET_CODE (elt) != SET
       || count <= 1
-      || count > 8)
+      || count > 25)
     return false;
 
   /* Pick up regno of first element for further detail checking.
@@ -141,11 +153,29 @@ nds32_valid_multiple_load_store (rtx op, bool load_p)
      Refer to nds32-multiple.md for more information
      about following checking.
      The starting element of parallel rtx is index 0.  */
-  if (!nds32_consecutive_registers_load_store_p (op, load_p, 0,
+  if (!nds32_consecutive_registers_load_store_p (op, load_p, bim_p ? 1 : 0,
 						 first_elt_regno,
 						 count))
     return false;
 
+  if (bim_p)
+    {
+      update_base_elt_idx = 0;
+      update_base = XVECEXP (op, 0, update_base_elt_idx);
+      if (!REG_P (SET_DEST (update_base)))
+	return false;
+      if (GET_CODE (SET_SRC (update_base)) != PLUS)
+	return false;
+      else
+	{
+	  offset = count * UNITS_PER_WORD;
+	  elt = XEXP (SET_SRC (update_base), 1);
+	  if (GET_CODE (elt) != CONST_INT
+	      || (INTVAL (elt) != offset))
+	    return false;
+	}
+    }
+
   /* Pass all test, this is a valid rtx.  */
   return true;
 }
diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h
index a8ffb8c9770..d51d55949ab 100644
--- a/gcc/config/nds32/nds32-protos.h
+++ b/gcc/config/nds32/nds32-protos.h
@@ -66,8 +66,8 @@ extern bool nds32_valid_smw_lwm_base_p (rtx);
 
 /* Auxiliary functions for expanding rtl used in nds32-multiple.md.  */
 
-extern rtx nds32_expand_load_multiple (int, int, rtx, rtx);
-extern rtx nds32_expand_store_multiple (int, int, rtx, rtx);
+extern rtx nds32_expand_load_multiple (int, int, rtx, rtx, bool, rtx *);
+extern rtx nds32_expand_store_multiple (int, int, rtx, rtx, bool, rtx *);
 extern int nds32_expand_movmemqi (rtx, rtx, rtx, rtx);
 
 /* Auxiliary functions for expand unalign load instruction.  */
@@ -80,7 +80,7 @@ extern void nds32_expand_unaligned_store (rtx *, enum machine_mode);
 
 /* Auxiliary functions for multiple load/store predicate checking.  */
 
-extern bool nds32_valid_multiple_load_store (rtx, bool);
+extern bool nds32_valid_multiple_load_store_p (rtx, bool, bool);
 
 /* Auxiliary functions for stack operation predicate checking.  */
 
diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md
index 98db74a8e62..bff37c71c4a 100644
--- a/gcc/config/nds32/predicates.md
+++ b/gcc/config/nds32/predicates.md
@@ -66,7 +66,16 @@
 {
   /* To verify 'load' operation, pass 'true' for the second argument.
      See the implementation in nds32.c for details.  */
-  return nds32_valid_multiple_load_store (op, true);
+  return nds32_valid_multiple_load_store_p (op, true, false);
+})
+
+(define_special_predicate "nds32_load_multiple_and_update_address_operation"
+  (match_code "parallel")
+{
+  /* To verify 'load' operation, pass 'true' for the second argument.
+     to verify 'update address' operation, pass 'true' for the third argument
+     See the implementation in nds32.c for details.  */
+  return nds32_valid_multiple_load_store_p (op, true, true);
 })
 
 (define_special_predicate "nds32_store_multiple_operation"
@@ -74,7 +83,16 @@
 {
   /* To verify 'store' operation, pass 'false' for the second argument.
      See the implementation in nds32.c for details.  */
-  return nds32_valid_multiple_load_store (op, false);
+  return nds32_valid_multiple_load_store_p (op, false, false);
+})
+
+(define_special_predicate "nds32_store_multiple_and_update_address_operation"
+  (match_code "parallel")
+{
+  /* To verify 'store' operation, pass 'false' for the second argument,
+     to verify 'update address' operation, pass 'true' for the third argument
+     See the implementation in nds32.c for details.  */
+  return nds32_valid_multiple_load_store_p (op, false, true);
 })
 
 (define_special_predicate "nds32_stack_push_operation"
-- 
2.11.4.GIT