From d08b1d22dd38398949fb3ae86e7db96e9519f2ef Mon Sep 17 00:00:00 2001 From: jasonwucj Date: Sun, 12 Aug 2018 07:38:40 +0000 Subject: [PATCH] [NDS32] Implement more C ISR extension. gcc/ * config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in extra_headers. * common/config/nds32/nds32-common.c (nds32_handle_option): Handle OPT_misr_secure_ case. * config/nds32/nds32-isr.c: Implementation of backward compatibility. * config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New. * config/nds32/nds32.c (nds32_attribute_table): Add critical and secure attribute. * config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL. (nds32_isr_info): New field security_level. (TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro. * config/nds32/nds32.md (return_internal): Consider critical attribute. * config/nds32/nds32.opt (misr-secure): New option. * config/nds32/nds32_init.inc: New file. * config/nds32/nds32_isr.h: New file. libgcc/ * config/nds32/t-nds32-isr: Rearrange object dependency. * config/nds32/initfini.c: Add dwarf2 unwinding support. * config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions and registers usage. * config/nds32/isr-library/excp_isr.S: Ditto. * config/nds32/isr-library/intr_isr.S: Ditto. * config/nds32/isr-library/reset.S: Ditto. * config/nds32/isr-library/restore_all.inc: Ditto. * config/nds32/isr-library/restore_mac_regs.inc: Ditto. * config/nds32/isr-library/restore_partial.inc: Ditto. * config/nds32/isr-library/restore_usr_regs.inc: Ditto. * config/nds32/isr-library/save_all.inc: Ditto. * config/nds32/isr-library/save_mac_regs.inc: Ditto. * config/nds32/isr-library/save_partial.inc: Ditto. * config/nds32/isr-library/save_usr_regs.inc: Ditto. * config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@263493 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 18 + gcc/common/config/nds32/nds32-common.c | 10 + gcc/config.gcc | 2 +- gcc/config/nds32/nds32-isr.c | 470 +++++++++++++++++- gcc/config/nds32/nds32-protos.h | 1 + gcc/config/nds32/nds32.c | 58 ++- gcc/config/nds32/nds32.h | 14 +- gcc/config/nds32/nds32.md | 11 +- gcc/config/nds32/nds32.opt | 4 + gcc/config/nds32/nds32_init.inc | 43 ++ gcc/config/nds32/nds32_isr.h | 526 +++++++++++++++++++++ libgcc/ChangeLog | 19 + libgcc/config/nds32/initfini.c | 84 +++- libgcc/config/nds32/isr-library/adj_intr_lvl.inc | 13 + libgcc/config/nds32/isr-library/excp_isr.S | 55 ++- libgcc/config/nds32/isr-library/intr_isr.S | 67 ++- libgcc/config/nds32/isr-library/reset.S | 81 ++-- libgcc/config/nds32/isr-library/restore_all.inc | 10 +- .../config/nds32/isr-library/restore_mac_regs.inc | 2 +- .../config/nds32/isr-library/restore_partial.inc | 12 +- .../{adj_intr_lvl.inc => restore_usr_regs.inc} | 26 +- libgcc/config/nds32/isr-library/save_all.inc | 43 +- libgcc/config/nds32/isr-library/save_mac_regs.inc | 2 +- libgcc/config/nds32/isr-library/save_partial.inc | 46 +- .../{adj_intr_lvl.inc => save_usr_regs.inc} | 28 +- libgcc/config/nds32/isr-library/vec_vid00.S | 7 + libgcc/config/nds32/isr-library/vec_vid01.S | 7 + libgcc/config/nds32/isr-library/vec_vid02.S | 7 + libgcc/config/nds32/isr-library/vec_vid03.S | 7 + libgcc/config/nds32/isr-library/vec_vid04.S | 7 + libgcc/config/nds32/isr-library/vec_vid05.S | 7 + libgcc/config/nds32/isr-library/vec_vid06.S | 7 + libgcc/config/nds32/isr-library/vec_vid07.S | 7 + libgcc/config/nds32/isr-library/vec_vid08.S | 7 + libgcc/config/nds32/isr-library/vec_vid09.S | 7 + libgcc/config/nds32/isr-library/vec_vid10.S | 7 + libgcc/config/nds32/isr-library/vec_vid11.S | 7 + libgcc/config/nds32/isr-library/vec_vid12.S | 7 + libgcc/config/nds32/isr-library/vec_vid13.S | 7 + libgcc/config/nds32/isr-library/vec_vid14.S | 7 + libgcc/config/nds32/isr-library/vec_vid15.S | 7 + libgcc/config/nds32/isr-library/vec_vid16.S | 7 + libgcc/config/nds32/isr-library/vec_vid17.S | 7 + libgcc/config/nds32/isr-library/vec_vid18.S | 7 + libgcc/config/nds32/isr-library/vec_vid19.S | 7 + libgcc/config/nds32/isr-library/vec_vid20.S | 7 + libgcc/config/nds32/isr-library/vec_vid21.S | 7 + libgcc/config/nds32/isr-library/vec_vid22.S | 7 + libgcc/config/nds32/isr-library/vec_vid23.S | 7 + libgcc/config/nds32/isr-library/vec_vid24.S | 7 + libgcc/config/nds32/isr-library/vec_vid25.S | 7 + libgcc/config/nds32/isr-library/vec_vid26.S | 7 + libgcc/config/nds32/isr-library/vec_vid27.S | 7 + libgcc/config/nds32/isr-library/vec_vid28.S | 7 + libgcc/config/nds32/isr-library/vec_vid29.S | 7 + libgcc/config/nds32/isr-library/vec_vid30.S | 7 + libgcc/config/nds32/isr-library/vec_vid31.S | 7 + libgcc/config/nds32/isr-library/vec_vid32.S | 7 + libgcc/config/nds32/isr-library/vec_vid33.S | 7 + libgcc/config/nds32/isr-library/vec_vid34.S | 7 + libgcc/config/nds32/isr-library/vec_vid35.S | 7 + libgcc/config/nds32/isr-library/vec_vid36.S | 7 + libgcc/config/nds32/isr-library/vec_vid37.S | 7 + libgcc/config/nds32/isr-library/vec_vid38.S | 7 + libgcc/config/nds32/isr-library/vec_vid39.S | 7 + libgcc/config/nds32/isr-library/vec_vid40.S | 7 + libgcc/config/nds32/isr-library/vec_vid41.S | 7 + libgcc/config/nds32/isr-library/vec_vid42.S | 7 + libgcc/config/nds32/isr-library/vec_vid43.S | 7 + libgcc/config/nds32/isr-library/vec_vid44.S | 7 + libgcc/config/nds32/isr-library/vec_vid45.S | 7 + libgcc/config/nds32/isr-library/vec_vid46.S | 7 + libgcc/config/nds32/isr-library/vec_vid47.S | 7 + libgcc/config/nds32/isr-library/vec_vid48.S | 7 + libgcc/config/nds32/isr-library/vec_vid49.S | 7 + libgcc/config/nds32/isr-library/vec_vid50.S | 7 + libgcc/config/nds32/isr-library/vec_vid51.S | 7 + libgcc/config/nds32/isr-library/vec_vid52.S | 7 + libgcc/config/nds32/isr-library/vec_vid53.S | 7 + libgcc/config/nds32/isr-library/vec_vid54.S | 7 + libgcc/config/nds32/isr-library/vec_vid55.S | 7 + libgcc/config/nds32/isr-library/vec_vid56.S | 7 + libgcc/config/nds32/isr-library/vec_vid57.S | 7 + libgcc/config/nds32/isr-library/vec_vid58.S | 7 + libgcc/config/nds32/isr-library/vec_vid59.S | 7 + libgcc/config/nds32/isr-library/vec_vid60.S | 7 + libgcc/config/nds32/isr-library/vec_vid61.S | 7 + libgcc/config/nds32/isr-library/vec_vid62.S | 7 + libgcc/config/nds32/isr-library/vec_vid63.S | 7 + libgcc/config/nds32/isr-library/vec_vid64.S | 7 + libgcc/config/nds32/isr-library/vec_vid65.S | 7 + libgcc/config/nds32/isr-library/vec_vid66.S | 7 + libgcc/config/nds32/isr-library/vec_vid67.S | 7 + libgcc/config/nds32/isr-library/vec_vid68.S | 7 + libgcc/config/nds32/isr-library/vec_vid69.S | 7 + libgcc/config/nds32/isr-library/vec_vid70.S | 7 + libgcc/config/nds32/isr-library/vec_vid71.S | 7 + libgcc/config/nds32/isr-library/vec_vid72.S | 7 + libgcc/config/nds32/t-nds32-isr | 112 +---- 99 files changed, 1969 insertions(+), 299 deletions(-) create mode 100644 gcc/config/nds32/nds32_init.inc create mode 100644 gcc/config/nds32/nds32_isr.h copy libgcc/config/nds32/isr-library/{adj_intr_lvl.inc => restore_usr_regs.inc} (73%) copy libgcc/config/nds32/isr-library/{adj_intr_lvl.inc => save_usr_regs.inc} (62%) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c669cadfec5..09ec7e4f7fd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2018-08-12 Chung-Ju Wu + + * config.gcc (nds32*): Add nds32_isr.h and nds32_init.inc in + extra_headers. + * common/config/nds32/nds32-common.c (nds32_handle_option): Handle + OPT_misr_secure_ case. + * config/nds32/nds32-isr.c: Implementation of backward compatibility. + * config/nds32/nds32-protos.h (nds32_isr_function_critical_p): New. + * config/nds32/nds32.c (nds32_attribute_table): Add critical and + secure attribute. + * config/nds32/nds32.h (nds32_isr_nested_type): Add NDS32_CRITICAL. + (nds32_isr_info): New field security_level. + (TARGET_ISR_VECTOR_SIZE_4_BYTE): New macro. + * config/nds32/nds32.md (return_internal): Consider critical attribute. + * config/nds32/nds32.opt (misr-secure): New option. + * config/nds32/nds32_init.inc: New file. + * config/nds32/nds32_isr.h: New file. + 2018-08-11 John David Anglin * config/pa/pa.md (UNSPEC_MEMORY_BARRIER): New unspec enum. diff --git a/gcc/common/config/nds32/nds32-common.c b/gcc/common/config/nds32/nds32-common.c index 197f06c8b90..efe2e9d43d7 100644 --- a/gcc/common/config/nds32/nds32-common.c +++ b/gcc/common/config/nds32/nds32-common.c @@ -53,6 +53,16 @@ nds32_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED, return true; + case OPT_misr_secure_: + /* Check the valid security level: 0 1 2 3. */ + if (value < 0 || value > 3) + { + error_at (loc, "for the option -misr-secure=X, the valid X " + "must be: 0, 1, 2, or 3"); + return false; + } + return true; + case OPT_mcache_block_size_: /* Check valid value: 4 8 16 32 64 128 256 512. */ if (exact_log2 (value) < 2 || exact_log2 (value) > 9) diff --git a/gcc/config.gcc b/gcc/config.gcc index f777a28e3ad..ea6715afc4f 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -447,7 +447,7 @@ mips*-*-*) ;; nds32*) cpu_type=nds32 - extra_headers="nds32_intrinsic.h" + extra_headers="nds32_intrinsic.h nds32_isr.h nds32_init.inc" case ${target} in nds32*-*-linux*) extra_options="${extra_options} nds32/nds32-linux.opt" diff --git a/gcc/config/nds32/nds32-isr.c b/gcc/config/nds32/nds32-isr.c index 2c3aac7a256..db67a0e3666 100644 --- a/gcc/config/nds32/nds32-isr.c +++ b/gcc/config/nds32/nds32-isr.c @@ -43,7 +43,260 @@ We use an array to record essential information for each vector. */ static struct nds32_isr_info nds32_isr_vectors[NDS32_N_ISR_VECTORS]; -/* ------------------------------------------------------------------------ */ +/* ------------------------------------------------------------- */ +/* FIXME: + FOR BACKWARD COMPATIBILITY, we need to support following patterns: + + __attribute__((interrupt("XXX;YYY;id=ZZZ"))) + __attribute__((exception("XXX;YYY;id=ZZZ"))) + __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) + + We provide several functions to parse the strings. */ + +static void +nds32_interrupt_attribute_parse_string (const char *original_str, + const char *func_name, + unsigned int s_level) +{ + char target_str[100]; + enum nds32_isr_save_reg save_reg; + enum nds32_isr_nested_type nested_type; + + char *save_all_regs_str, *save_caller_regs_str; + char *nested_str, *not_nested_str, *ready_nested_str, *critical_str; + char *id_str, *value_str; + + /* Copy original string into a character array so that + the string APIs can handle it. */ + strcpy (target_str, original_str); + + /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL + 'save_caller_regs' : NDS32_PARTIAL_SAVE */ + save_all_regs_str = strstr (target_str, "save_all_regs"); + save_caller_regs_str = strstr (target_str, "save_caller_regs"); + + /* Note that if no argument is found, + use NDS32_PARTIAL_SAVE by default. */ + if (save_all_regs_str) + save_reg = NDS32_SAVE_ALL; + else if (save_caller_regs_str) + save_reg = NDS32_PARTIAL_SAVE; + else + save_reg = NDS32_PARTIAL_SAVE; + + /* 2. Detect 'nested' : NDS32_NESTED + 'not_nested' : NDS32_NOT_NESTED + 'ready_nested' : NDS32_NESTED_READY + 'critical' : NDS32_CRITICAL */ + nested_str = strstr (target_str, "nested"); + not_nested_str = strstr (target_str, "not_nested"); + ready_nested_str = strstr (target_str, "ready_nested"); + critical_str = strstr (target_str, "critical"); + + /* Note that if no argument is found, + use NDS32_NOT_NESTED by default. + Also, since 'not_nested' and 'ready_nested' both contains + 'nested' string, we check 'nested' with lowest priority. */ + if (not_nested_str) + nested_type = NDS32_NOT_NESTED; + else if (ready_nested_str) + nested_type = NDS32_NESTED_READY; + else if (nested_str) + nested_type = NDS32_NESTED; + else if (critical_str) + nested_type = NDS32_CRITICAL; + else + nested_type = NDS32_NOT_NESTED; + + /* 3. Traverse each id value and set corresponding information. */ + id_str = strstr (target_str, "id="); + + /* If user forgets to assign 'id', issue an error message. */ + if (id_str == NULL) + error ("require id argument in the string"); + /* Extract the value_str first. */ + id_str = strtok (id_str, "="); + value_str = strtok (NULL, ";"); + + /* Pick up the first id value token. */ + value_str = strtok (value_str, ","); + while (value_str != NULL) + { + int i; + i = atoi (value_str); + + /* For interrupt(0..63), the actual vector number is (9..72). */ + i = i + 9; + if (i < 9 || i > 72) + error ("invalid id value for interrupt attribute"); + + /* Setup nds32_isr_vectors[] array. */ + nds32_isr_vectors[i].category = NDS32_ISR_INTERRUPT; + strcpy (nds32_isr_vectors[i].func_name, func_name); + nds32_isr_vectors[i].save_reg = save_reg; + nds32_isr_vectors[i].nested_type = nested_type; + nds32_isr_vectors[i].security_level = s_level; + + /* Fetch next token. */ + value_str = strtok (NULL, ","); + } + + return; +} + +static void +nds32_exception_attribute_parse_string (const char *original_str, + const char *func_name, + unsigned int s_level) +{ + char target_str[100]; + enum nds32_isr_save_reg save_reg; + enum nds32_isr_nested_type nested_type; + + char *save_all_regs_str, *save_caller_regs_str; + char *nested_str, *not_nested_str, *ready_nested_str, *critical_str; + char *id_str, *value_str; + + /* Copy original string into a character array so that + the string APIs can handle it. */ + strcpy (target_str, original_str); + + /* 1. Detect 'save_all_regs' : NDS32_SAVE_ALL + 'save_caller_regs' : NDS32_PARTIAL_SAVE */ + save_all_regs_str = strstr (target_str, "save_all_regs"); + save_caller_regs_str = strstr (target_str, "save_caller_regs"); + + /* Note that if no argument is found, + use NDS32_PARTIAL_SAVE by default. */ + if (save_all_regs_str) + save_reg = NDS32_SAVE_ALL; + else if (save_caller_regs_str) + save_reg = NDS32_PARTIAL_SAVE; + else + save_reg = NDS32_PARTIAL_SAVE; + + /* 2. Detect 'nested' : NDS32_NESTED + 'not_nested' : NDS32_NOT_NESTED + 'ready_nested' : NDS32_NESTED_READY + 'critical' : NDS32_CRITICAL */ + nested_str = strstr (target_str, "nested"); + not_nested_str = strstr (target_str, "not_nested"); + ready_nested_str = strstr (target_str, "ready_nested"); + critical_str = strstr (target_str, "critical"); + + /* Note that if no argument is found, + use NDS32_NOT_NESTED by default. + Also, since 'not_nested' and 'ready_nested' both contains + 'nested' string, we check 'nested' with lowest priority. */ + if (not_nested_str) + nested_type = NDS32_NOT_NESTED; + else if (ready_nested_str) + nested_type = NDS32_NESTED_READY; + else if (nested_str) + nested_type = NDS32_NESTED; + else if (critical_str) + nested_type = NDS32_CRITICAL; + else + nested_type = NDS32_NOT_NESTED; + + /* 3. Traverse each id value and set corresponding information. */ + id_str = strstr (target_str, "id="); + + /* If user forgets to assign 'id', issue an error message. */ + if (id_str == NULL) + error ("require id argument in the string"); + /* Extract the value_str first. */ + id_str = strtok (id_str, "="); + value_str = strtok (NULL, ";"); + + /* Pick up the first id value token. */ + value_str = strtok (value_str, ","); + while (value_str != NULL) + { + int i; + i = atoi (value_str); + + /* For exception(1..8), the actual vector number is (1..8). */ + if (i < 1 || i > 8) + error ("invalid id value for exception attribute"); + + /* Setup nds32_isr_vectors[] array. */ + nds32_isr_vectors[i].category = NDS32_ISR_EXCEPTION; + strcpy (nds32_isr_vectors[i].func_name, func_name); + nds32_isr_vectors[i].save_reg = save_reg; + nds32_isr_vectors[i].nested_type = nested_type; + nds32_isr_vectors[i].security_level = s_level; + + /* Fetch next token. */ + value_str = strtok (NULL, ","); + } + + return; +} + +static void +nds32_reset_attribute_parse_string (const char *original_str, + const char *func_name) +{ + char target_str[100]; + char *vectors_str, *nmi_str, *warm_str, *value_str; + + /* Deal with reset attribute. Its vector number is always 0. */ + nds32_isr_vectors[0].category = NDS32_ISR_RESET; + + + /* 1. Parse 'vectors=XXXX'. */ + + /* Copy original string into a character array so that + the string APIs can handle it. */ + strcpy (target_str, original_str); + vectors_str = strstr (target_str, "vectors="); + /* The total vectors = interrupt + exception numbers + reset. + There are 8 exception and 1 reset in nds32 architecture. + If user forgets to assign 'vectors', user default 16 interrupts. */ + if (vectors_str != NULL) + { + /* Extract the value_str. */ + vectors_str = strtok (vectors_str, "="); + value_str = strtok (NULL, ";"); + nds32_isr_vectors[0].total_n_vectors = atoi (value_str) + 8 + 1; + } + else + nds32_isr_vectors[0].total_n_vectors = 16 + 8 + 1; + strcpy (nds32_isr_vectors[0].func_name, func_name); + + + /* 2. Parse 'nmi_func=YYYY'. */ + + /* Copy original string into a character array so that + the string APIs can handle it. */ + strcpy (target_str, original_str); + nmi_str = strstr (target_str, "nmi_func="); + if (nmi_str != NULL) + { + /* Extract the value_str. */ + nmi_str = strtok (nmi_str, "="); + value_str = strtok (NULL, ";"); + strcpy (nds32_isr_vectors[0].nmi_name, value_str); + } + + /* 3. Parse 'warm_func=ZZZZ'. */ + + /* Copy original string into a character array so that + the string APIs can handle it. */ + strcpy (target_str, original_str); + warm_str = strstr (target_str, "warm_func="); + if (warm_str != NULL) + { + /* Extract the value_str. */ + warm_str = strtok (warm_str, "="); + value_str = strtok (NULL, ";"); + strcpy (nds32_isr_vectors[0].warm_name, value_str); + } + + return; +} +/* ------------------------------------------------------------- */ /* A helper function to emit section head template. */ static void @@ -79,6 +332,15 @@ nds32_emit_isr_jmptbl_section (int vector_id) char section_name[100]; char symbol_name[100]; + /* A critical isr does not need jump table section because + its behavior is not performed by two-level handler. */ + if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL) + { + fprintf (asm_out_file, "\t! The vector %02d is a critical isr !\n", + vector_id); + return; + } + /* Prepare jmptbl section and symbol name. */ snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.%02d", vector_id); @@ -99,7 +361,6 @@ nds32_emit_isr_vector_section (int vector_id) const char *c_str = "CATEGORY"; const char *sr_str = "SR"; const char *nt_str = "NT"; - const char *vs_str = "VS"; char first_level_handler_name[100]; char section_name[100]; char symbol_name[100]; @@ -147,30 +408,47 @@ nds32_emit_isr_vector_section (int vector_id) case NDS32_NESTED_READY: nt_str = "nr"; break; + case NDS32_CRITICAL: + /* The critical isr is not performed by two-level handler. */ + nt_str = ""; + break; } - /* Currently we have 4-byte or 16-byte size for each vector. - If it is 4-byte, the first level handler name has suffix string "_4b". */ - vs_str = (nds32_isr_vector_size == 4) ? "_4b" : ""; - /* Now we can create first level handler name. */ - snprintf (first_level_handler_name, sizeof (first_level_handler_name), - "_nds32_%s_%s_%s%s", c_str, sr_str, nt_str, vs_str); + if (nds32_isr_vectors[vector_id].security_level == 0) + { + /* For security level 0, use normal first level handler name. */ + snprintf (first_level_handler_name, sizeof (first_level_handler_name), + "_nds32_%s_%s_%s", c_str, sr_str, nt_str); + } + else + { + /* For security level 1-3, use corresponding spl_1, spl_2, or spl_3. */ + snprintf (first_level_handler_name, sizeof (first_level_handler_name), + "_nds32_spl_%d", nds32_isr_vectors[vector_id].security_level); + } /* Prepare vector section and symbol name. */ snprintf (section_name, sizeof (section_name), ".nds32_vector.%02d", vector_id); snprintf (symbol_name, sizeof (symbol_name), - "_nds32_vector_%02d%s", vector_id, vs_str); + "_nds32_vector_%02d", vector_id); /* Everything is ready. We can start emit vector section content. */ nds32_emit_section_head_template (section_name, symbol_name, floor_log2 (nds32_isr_vector_size), false); - /* According to the vector size, the instructions in the - vector section may be different. */ - if (nds32_isr_vector_size == 4) + /* First we check if it is a critical isr. + If so, jump to user handler directly; otherwise, the instructions + in the vector section may be different according to the vector size. */ + if (nds32_isr_vectors[vector_id].nested_type == NDS32_CRITICAL) + { + /* This block is for critical isr. Jump to user handler directly. */ + fprintf (asm_out_file, "\tj\t%s ! jump to user handler directly\n", + nds32_isr_vectors[vector_id].func_name); + } + else if (nds32_isr_vector_size == 4) { /* This block is for 4-byte vector size. Hardware $VID support is necessary and only one instruction @@ -239,13 +517,11 @@ nds32_emit_isr_reset_content (void) { unsigned int i; unsigned int total_n_vectors; - const char *vs_str; char reset_handler_name[100]; char section_name[100]; char symbol_name[100]; total_n_vectors = nds32_isr_vectors[0].total_n_vectors; - vs_str = (nds32_isr_vector_size == 4) ? "_4b" : ""; fprintf (asm_out_file, "\t! RESET HANDLER CONTENT - BEGIN !\n"); @@ -261,7 +537,7 @@ nds32_emit_isr_reset_content (void) /* Emit vector references. */ fprintf (asm_out_file, "\t ! references to vector section entries\n"); for (i = 0; i < total_n_vectors; i++) - fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d%s\n", i, vs_str); + fprintf (asm_out_file, "\t.word\t_nds32_vector_%02d\n", i); /* Emit jmptbl_00 section. */ snprintf (section_name, sizeof (section_name), ".nds32_jmptbl.00"); @@ -275,9 +551,9 @@ nds32_emit_isr_reset_content (void) /* Emit vector_00 section. */ snprintf (section_name, sizeof (section_name), ".nds32_vector.00"); - snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00%s", vs_str); + snprintf (symbol_name, sizeof (symbol_name), "_nds32_vector_00"); snprintf (reset_handler_name, sizeof (reset_handler_name), - "_nds32_reset%s", vs_str); + "_nds32_reset"); fprintf (asm_out_file, "\t! ....................................\n"); nds32_emit_section_head_template (section_name, symbol_name, @@ -323,12 +599,12 @@ void nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs) { int save_all_p, partial_save_p; - int nested_p, not_nested_p, nested_ready_p; + int nested_p, not_nested_p, nested_ready_p, critical_p; int intr_p, excp_p, reset_p; /* Initialize variables. */ save_all_p = partial_save_p = 0; - nested_p = not_nested_p = nested_ready_p = 0; + nested_p = not_nested_p = nested_ready_p = critical_p = 0; intr_p = excp_p = reset_p = 0; /* We must check at MOST one attribute to set save-reg. */ @@ -347,8 +623,10 @@ nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs) not_nested_p = 1; if (lookup_attribute ("nested_ready", func_attrs)) nested_ready_p = 1; + if (lookup_attribute ("critical", func_attrs)) + critical_p = 1; - if ((nested_p + not_nested_p + nested_ready_p) > 1) + if ((nested_p + not_nested_p + nested_ready_p + critical_p) > 1) error ("multiple nested types attributes to function %qD", func_decl); /* We must check at MOST one attribute to @@ -362,6 +640,17 @@ nds32_check_isr_attrs_conflict (tree func_decl, tree func_attrs) if ((intr_p + excp_p + reset_p) > 1) error ("multiple interrupt attributes to function %qD", func_decl); + + /* Do not allow isr attributes under linux toolchain. */ + if (TARGET_LINUX_ABI && intr_p) + error ("cannot use interrupt attributes to function %qD " + "under linux toolchain", func_decl); + if (TARGET_LINUX_ABI && excp_p) + error ("cannot use exception attributes to function %qD " + "under linux toolchain", func_decl); + if (TARGET_LINUX_ABI && reset_p) + error ("cannot use reset attributes to function %qD " + "under linux toolchain", func_decl); } /* Function to construct isr vectors information array. @@ -373,15 +662,21 @@ nds32_construct_isr_vectors_information (tree func_attrs, const char *func_name) { tree save_all, partial_save; - tree nested, not_nested, nested_ready; + tree nested, not_nested, nested_ready, critical; tree intr, excp, reset; + tree secure; + tree security_level_list; + tree security_level; + unsigned int s_level; + save_all = lookup_attribute ("save_all", func_attrs); partial_save = lookup_attribute ("partial_save", func_attrs); nested = lookup_attribute ("nested", func_attrs); not_nested = lookup_attribute ("not_nested", func_attrs); nested_ready = lookup_attribute ("nested_ready", func_attrs); + critical = lookup_attribute ("critical", func_attrs); intr = lookup_attribute ("interrupt", func_attrs); excp = lookup_attribute ("exception", func_attrs); @@ -391,6 +686,63 @@ nds32_construct_isr_vectors_information (tree func_attrs, if (!intr && !excp && !reset) return; + /* At first, we need to retrieve security level. */ + secure = lookup_attribute ("secure", func_attrs); + if (secure != NULL) + { + security_level_list = TREE_VALUE (secure); + security_level = TREE_VALUE (security_level_list); + s_level = TREE_INT_CST_LOW (security_level); + } + else + { + /* If there is no secure attribute, the security level is set by + nds32_isr_secure_level, which is controlled by -misr-secure=X option. + By default nds32_isr_secure_level should be 0. */ + s_level = nds32_isr_secure_level; + } + + /* ------------------------------------------------------------- */ + /* FIXME: + FOR BACKWARD COMPATIBILITY, we need to support following patterns: + + __attribute__((interrupt("XXX;YYY;id=ZZZ"))) + __attribute__((exception("XXX;YYY;id=ZZZ"))) + __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) + + If interrupt/exception/reset appears and its argument is a + STRING_CST, we will parse string with some auxiliary functions + which set necessary isr information in the nds32_isr_vectors[] array. + After that, we can return immediately to avoid new-syntax isr + information construction. */ + if (intr != NULL_TREE + && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) + { + tree string_arg = TREE_VALUE (TREE_VALUE (intr)); + nds32_interrupt_attribute_parse_string (TREE_STRING_POINTER (string_arg), + func_name, + s_level); + return; + } + if (excp != NULL_TREE + && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) + { + tree string_arg = TREE_VALUE (TREE_VALUE (excp)); + nds32_exception_attribute_parse_string (TREE_STRING_POINTER (string_arg), + func_name, + s_level); + return; + } + if (reset != NULL_TREE + && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) + { + tree string_arg = TREE_VALUE (TREE_VALUE (reset)); + nds32_reset_attribute_parse_string (TREE_STRING_POINTER (string_arg), + func_name); + return; + } + /* ------------------------------------------------------------- */ + /* If we are here, either we have interrupt/exception, or reset attribute. */ if (intr || excp) @@ -417,6 +769,9 @@ nds32_construct_isr_vectors_information (tree func_attrs, /* Add vector_number_offset to get actual vector number. */ vector_id = TREE_INT_CST_LOW (id) + vector_number_offset; + /* Set security level. */ + nds32_isr_vectors[vector_id].security_level = s_level; + /* Enable corresponding vector and set function name. */ nds32_isr_vectors[vector_id].category = (intr) ? (NDS32_ISR_INTERRUPT) @@ -436,6 +791,8 @@ nds32_construct_isr_vectors_information (tree func_attrs, nds32_isr_vectors[vector_id].nested_type = NDS32_NOT_NESTED; else if (nested_ready) nds32_isr_vectors[vector_id].nested_type = NDS32_NESTED_READY; + else if (critical) + nds32_isr_vectors[vector_id].nested_type = NDS32_CRITICAL; /* Advance to next id. */ id_list = TREE_CHAIN (id_list); @@ -492,7 +849,6 @@ nds32_construct_isr_vectors_information (tree func_attrs, } } -/* A helper function to handle isr stuff at the beginning of asm file. */ void nds32_asm_file_start_for_isr (void) { @@ -505,15 +861,14 @@ nds32_asm_file_start_for_isr (void) strcpy (nds32_isr_vectors[i].func_name, ""); nds32_isr_vectors[i].save_reg = NDS32_PARTIAL_SAVE; nds32_isr_vectors[i].nested_type = NDS32_NOT_NESTED; + nds32_isr_vectors[i].security_level = 0; nds32_isr_vectors[i].total_n_vectors = 0; strcpy (nds32_isr_vectors[i].nmi_name, ""); strcpy (nds32_isr_vectors[i].warm_name, ""); } } -/* A helper function to handle isr stuff at the end of asm file. */ -void -nds32_asm_file_end_for_isr (void) +void nds32_asm_file_end_for_isr (void) { int i; @@ -547,6 +902,8 @@ nds32_asm_file_end_for_isr (void) /* Found one vector which is interupt or exception. Output its jmptbl and vector section content. */ fprintf (asm_out_file, "\t! interrupt/exception vector %02d\n", i); + fprintf (asm_out_file, "\t! security level: %d\n", + nds32_isr_vectors[i].security_level); fprintf (asm_out_file, "\t! ------------------------------------\n"); nds32_emit_isr_jmptbl_section (i); fprintf (asm_out_file, "\t! ....................................\n"); @@ -580,4 +937,65 @@ nds32_isr_function_p (tree func) || (t_reset != NULL_TREE)); } -/* ------------------------------------------------------------------------ */ +/* Return true if FUNC is a isr function with critical attribute. */ +bool +nds32_isr_function_critical_p (tree func) +{ + tree t_intr; + tree t_excp; + tree t_critical; + + tree attrs; + + if (TREE_CODE (func) != FUNCTION_DECL) + abort (); + + attrs = DECL_ATTRIBUTES (func); + + t_intr = lookup_attribute ("interrupt", attrs); + t_excp = lookup_attribute ("exception", attrs); + + t_critical = lookup_attribute ("critical", attrs); + + /* If both interrupt and exception attribute does not appear, + we can return false immediately. */ + if ((t_intr == NULL_TREE) && (t_excp == NULL_TREE)) + return false; + + /* Here we can guarantee either interrupt or ecxception attribute + does exist, so further check critical attribute. + If it also appears, we can return true. */ + if (t_critical != NULL_TREE) + return true; + + /* ------------------------------------------------------------- */ + /* FIXME: + FOR BACKWARD COMPATIBILITY, we need to handle string type. + If the string 'critical' appears in the interrupt/exception + string argument, we can return true. */ + if (t_intr != NULL_TREE || t_excp != NULL_TREE) + { + char target_str[100]; + char *critical_str; + tree t_check; + tree string_arg; + + t_check = t_intr ? t_intr : t_excp; + if (TREE_CODE (TREE_VALUE (TREE_VALUE (t_check))) == STRING_CST) + { + string_arg = TREE_VALUE (TREE_VALUE (t_check)); + strcpy (target_str, TREE_STRING_POINTER (string_arg)); + critical_str = strstr (target_str, "critical"); + + /* Found 'critical' string, so return true. */ + if (critical_str) + return true; + } + } + /* ------------------------------------------------------------- */ + + /* Other cases, this isr function is not critical type. */ + return false; +} + +/* ------------------------------------------------------------- */ diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h index 3fa8ae175f2..5c4d233b4b9 100644 --- a/gcc/config/nds32/nds32-protos.h +++ b/gcc/config/nds32/nds32-protos.h @@ -307,6 +307,7 @@ extern void nds32_construct_isr_vectors_information (tree, const char *); extern void nds32_asm_file_start_for_isr (void); extern void nds32_asm_file_end_for_isr (void); extern bool nds32_isr_function_p (tree); +extern bool nds32_isr_function_critical_p (tree); /* Auxiliary functions for cost calculation. */ diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index 721135e6ba1..f68341e1fcd 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -305,6 +305,7 @@ static const struct attribute_spec nds32_attribute_table[] = { "nested", 0, 0, false, false, false, false, NULL, NULL }, { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, + { "critical", 0, 0, false, false, false, false, NULL, NULL }, /* The attributes describing isr register save scheme. */ { "save_all", 0, 0, false, false, false, false, NULL, NULL }, @@ -314,6 +315,9 @@ static const struct attribute_spec nds32_attribute_table[] = { "nmi", 1, 1, false, false, false, false, NULL, NULL }, { "warm", 1, 1, false, false, false, false, NULL, NULL }, + /* The attributes describing isr security level. */ + { "secure", 1, 1, false, false, false, false, NULL, NULL }, + /* The attribute telling no prologue/epilogue. */ { "naked", 0, 0, false, false, false, false, NULL, NULL }, @@ -518,7 +522,7 @@ nds32_compute_stack_frame (void) } /* Check if this function can omit prologue/epilogue code fragment. - If there is 'no_prologue'/'naked' attribute in this function, + If there is 'no_prologue'/'naked'/'secure' attribute in this function, we can set 'naked_p' flag to indicate that we do not have to generate prologue/epilogue. Or, if all the following conditions succeed, @@ -533,6 +537,7 @@ nds32_compute_stack_frame (void) we do not need to adjust $sp. */ if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) + || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl)) || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM @@ -2307,14 +2312,17 @@ nds32_function_ok_for_sibcall (tree decl, /* 1. Do not apply sibling call if -mv3push is enabled, because pop25 instruction also represents return behavior. - 2. If this function is a variadic function, do not apply sibling call + 2. If this function is a isr function, do not apply sibling call + because it may perform the behavior that user does not expect. + 3. If this function is a variadic function, do not apply sibling call because the stack layout may be a mess. - 3. We don't want to apply sibling call optimization for indirect + 4. We don't want to apply sibling call optimization for indirect sibcall because the pop behavior in epilogue may pollute the content of caller-saved regsiter when the register is used for indirect sibcall. - 4. In pic mode, it may use some registers for PLT call. */ + 5. In pic mode, it may use some registers for PLT call. */ return (!TARGET_V3PUSH + && !nds32_isr_function_p (current_function_decl) && (cfun->machine->va_args_size == 0) && decl && !flag_pic); @@ -3968,6 +3976,38 @@ nds32_insert_attributes (tree decl, tree *attributes) excp = lookup_attribute ("exception", func_attrs); reset = lookup_attribute ("reset", func_attrs); + /* The following code may use attribute arguments. If there is no + argument from source code, it will cause segmentation fault. + Therefore, return dircetly and report error message later. */ + if ((intr && TREE_VALUE (intr) == NULL) + || (excp && TREE_VALUE (excp) == NULL) + || (reset && TREE_VALUE (reset) == NULL)) + return; + + /* ------------------------------------------------------------- */ + /* FIXME: + FOR BACKWARD COMPATIBILITY, we need to support following patterns: + + __attribute__((interrupt("XXX;YYY;id=ZZZ"))) + __attribute__((exception("XXX;YYY;id=ZZZ"))) + __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) + + If interrupt/exception/reset appears and its argument is a + STRING_CST, we will use other functions to parse string in the + nds32_construct_isr_vectors_information() and then set necessary + isr information in the nds32_isr_vectors[] array. Here we can + just return immediately to avoid new-syntax checking. */ + if (intr != NULL_TREE + && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) + return; + if (excp != NULL_TREE + && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) + return; + if (reset != NULL_TREE + && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) + return; + /* ------------------------------------------------------------- */ + if (intr || excp) { /* Deal with interrupt/exception. */ @@ -4211,6 +4251,16 @@ nds32_cpu_cpp_builtins(struct cpp_reader *pfile) builtin_define ("__nds32__"); builtin_define ("__NDS32__"); + /* We need to provide builtin macro to describe the size of + each vector for interrupt handler under elf toolchain. */ + if (!TARGET_LINUX_ABI) + { + if (TARGET_ISR_VECTOR_SIZE_4_BYTE) + builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__"); + else + builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__"); + } + if (TARGET_HARD_FLOAT) builtin_define ("__NDS32_ABI_2FP_PLUS__"); else diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h index 3aac6a21bb8..cec15bed8ca 100644 --- a/gcc/config/nds32/nds32.h +++ b/gcc/config/nds32/nds32.h @@ -367,7 +367,8 @@ enum nds32_isr_nested_type { NDS32_NESTED, NDS32_NOT_NESTED, - NDS32_NESTED_READY + NDS32_NESTED_READY, + NDS32_CRITICAL }; /* Define structure to record isr information. @@ -395,6 +396,13 @@ struct nds32_isr_info unless user specifies attribute to change it. */ enum nds32_isr_nested_type nested_type; + /* Secure isr level. + Currently we have 0-3 security level. + It should be set to 0 by default. + For security processors, this is determined by secure + attribute or compiler options. */ + unsigned int security_level; + /* Total vectors. The total vectors = interrupt + exception numbers + reset. It should be set to 0 by default. @@ -849,8 +857,10 @@ enum nds32_builtins /* ------------------------------------------------------------------------ */ -#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) +#define TARGET_ISR_VECTOR_SIZE_4_BYTE \ + (nds32_isr_vector_size == 4) +#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) #define TARGET_ISA_V3 \ (nds32_arch_option == ARCH_V3 \ || nds32_arch_option == ARCH_V3J \ diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 92e90dda1af..f5349d7cc76 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -1993,6 +1993,9 @@ [(simple_return)] "" { + if (nds32_isr_function_critical_p (current_function_decl)) + return "iret"; + if (TARGET_16_BIT) return "ret5"; else @@ -2001,9 +2004,11 @@ [(set_attr "type" "branch") (set_attr "enabled" "yes") (set (attr "length") - (if_then_else (match_test "TARGET_16_BIT") - (const_int 2) - (const_int 4)))]) + (if_then_else (match_test "nds32_isr_function_critical_p (current_function_decl)") + (const_int 4) + (if_then_else (match_test "TARGET_16_BIT") + (const_int 2) + (const_int 4))))]) ;; ---------------------------------------------------------------------------- diff --git a/gcc/config/nds32/nds32.opt b/gcc/config/nds32/nds32.opt index a9ffae1ea6c..d73f5af9dbc 100644 --- a/gcc/config/nds32/nds32.opt +++ b/gcc/config/nds32/nds32.opt @@ -158,6 +158,10 @@ misr-vector-size= Target RejectNegative Joined UInteger Var(nds32_isr_vector_size) Init(NDS32_DEFAULT_ISR_VECTOR_SIZE) Specify the size of each interrupt vector, which must be 4 or 16. +misr-secure= +Target RejectNegative Joined UInteger Var(nds32_isr_secure_level) Init(0) +Specify the security level of c-isr for the whole file. + mcache-block-size= Target RejectNegative Joined UInteger Var(nds32_cache_block_size) Init(NDS32_DEFAULT_CACHE_BLOCK_SIZE) Specify the size of each cache block, which must be a power of 2 between 4 and 512. diff --git a/gcc/config/nds32/nds32_init.inc b/gcc/config/nds32/nds32_init.inc new file mode 100644 index 00000000000..1084ad0e471 --- /dev/null +++ b/gcc/config/nds32/nds32_init.inc @@ -0,0 +1,43 @@ +/* + * nds32_init.inc + * + * NDS32 architecture startup assembler header file + * + */ + +.macro nds32_init + + ! Initialize GP for data access + la $gp, _SDA_BASE_ + +#if defined(__NDS32_EXT_EX9__) + ! Check HW for EX9 + mfsr $r0, $MSC_CFG + li $r1, (1 << 24) + and $r2, $r0, $r1 + beqz $r2, 1f + + ! Initialize the table base of EX9 instruction + la $r0, _ITB_BASE_ + mtusr $r0, $ITB +1: +#endif + +#if defined(__NDS32_EXT_FPU_DP__) || defined(__NDS32_EXT_FPU_SP__) + ! Enable FPU + mfsr $r0, $FUCOP_CTL + ori $r0, $r0, #0x1 + mtsr $r0, $FUCOP_CTL + dsb + + ! Enable denormalized flush-to-Zero mode + fmfcsr $r0 + ori $r0,$r0,#0x1000 + fmtcsr $r0 + dsb +#endif + + ! Initialize default stack pointer + la $sp, _stack + +.endm diff --git a/gcc/config/nds32/nds32_isr.h b/gcc/config/nds32/nds32_isr.h new file mode 100644 index 00000000000..8ea58f951e1 --- /dev/null +++ b/gcc/config/nds32/nds32_isr.h @@ -0,0 +1,526 @@ +/* Intrinsic definitions of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2018 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _NDS32_ISR_H +#define _NDS32_ISR_H + +/* Attribute of a interrupt or exception handler: + + NDS32_READY_NESTED: This handler is interruptible if user re-enable GIE bit. + NDS32_NESTED : This handler is interruptible. This is not suitable + exception handler. + NDS32_NOT_NESTED : This handler is NOT interruptible. Users have to do + some work if nested is wanted + NDS32_CRITICAL : This handler is critical ISR, which means it is small + and efficient. */ +#define NDS32_READY_NESTED 0 +#define NDS32_NESTED 1 +#define NDS32_NOT_NESTED 2 +#define NDS32_CRITICAL 3 + +/* Attribute of a interrupt or exception handler: + + NDS32_SAVE_ALL_REGS : Save all registers in a table. + NDS32_SAVE_PARTIAL_REGS: Save partial registers. */ +#define NDS32_SAVE_CALLER_REGS 0 +#define NDS32_SAVE_ALL_REGS 1 + +/* There are two version of Register table for interrupt and exception handler, + one for 16-register CPU the other for 32-register CPU. These structures are + used for context switching or system call handling. The address of this + data can be get from the input argument of the handler functions. + + For system call handling, r0 to r5 are used to pass arguments. If more + arguments are used they are put into the stack and its starting address is + in sp. Return value of system call can be put into r0 and r1 upon exit from + system call handler. System call ID is in a system register and it can be + fetched via intrinsic function. For more information please read ABI and + other related documents. + + For context switching, at least 2 values need to saved in kernel. One is + IPC and the other is the stack address of current task. Use intrinsic + function to get IPC and the input argument of the handler functions + 8 to + get stack address of current task. To do context switching, you replace + new_sp with the stack address of new task and replace IPC system register + with IPC of new task, then, just return from handler. The context switching + will happen. */ + +/* Register table for exception handler; 32-register version. */ +typedef struct +{ + int r0; + int r1; + int r2; + int r3; + int r4; + int r5; + int r6; + int r7; + int r8; + int r9; + int r10; + int r11; + int r12; + int r13; + int r14; + int r15; + int r16; + int r17; + int r18; + int r19; + int r20; + int r21; + int r22; + int r23; + int r24; + int r25; + int r26; + int r27; + int fp; + int gp; + int lp; + int sp; +} NDS32_GPR32; + +/* Register table for exception handler; 16-register version. */ +typedef struct +{ + int r0; + int r1; + int r2; + int r3; + int r4; + int r5; + int r6; + int r7; + int r8; + int r9; + int r10; + int r15; + int fp; + int gp; + int lp; + int sp; +} NDS32_GPR16; + + +/* Use NDS32_REG32_TAB or NDS32_REG16_TAB in your program to + access register table. */ +typedef struct +{ + union + { + int reg_a[32] ; + NDS32_GPR32 reg_s ; + } u ; +} NDS32_REG32_TAB; + +typedef struct +{ + union + { + int reg_a[16] ; + NDS32_GPR16 reg_s ; + } u ; +} NDS32_REG16_TAB; + +typedef struct +{ + int d0lo; + int d0hi; + int d1lo; + int d1hi; +} NDS32_DX_TAB; + +typedef struct +{ +#ifdef __NDS32_EB__ + float fsr0; + float fsr1; + float fsr2; + float fsr3; + float fsr4; + float fsr5; + float fsr6; + float fsr7; +#else + float fsr1; + float fsr0; + float fsr3; + float fsr2; + float fsr5; + float fsr4; + float fsr7; + float fsr6; +#endif +} NDS32_FSR8; + +typedef struct +{ + double dsr0; + double dsr1; + double dsr2; + double dsr3; +} NDS32_DSR4; + +typedef struct +{ +#ifdef __NDS32_EB__ + float fsr0; + float fsr1; + float fsr2; + float fsr3; + float fsr4; + float fsr5; + float fsr6; + float fsr7; + float fsr8; + float fsr9; + float fsr10; + float fsr11; + float fsr12; + float fsr13; + float fsr14; + float fsr15; +#else + float fsr1; + float fsr0; + float fsr3; + float fsr2; + float fsr5; + float fsr4; + float fsr7; + float fsr6; + float fsr9; + float fsr8; + float fsr11; + float fsr10; + float fsr13; + float fsr12; + float fsr15; + float fsr14; +#endif +} NDS32_FSR16; + +typedef struct +{ + double dsr0; + double dsr1; + double dsr2; + double dsr3; + double dsr4; + double dsr5; + double dsr6; + double dsr7; +} NDS32_DSR8; + +typedef struct +{ +#ifdef __NDS32_EB__ + float fsr0; + float fsr1; + float fsr2; + float fsr3; + float fsr4; + float fsr5; + float fsr6; + float fsr7; + float fsr8; + float fsr9; + float fsr10; + float fsr11; + float fsr12; + float fsr13; + float fsr14; + float fsr15; + float fsr16; + float fsr17; + float fsr18; + float fsr19; + float fsr20; + float fsr21; + float fsr22; + float fsr23; + float fsr24; + float fsr25; + float fsr26; + float fsr27; + float fsr28; + float fsr29; + float fsr30; + float fsr31; +#else + float fsr1; + float fsr0; + float fsr3; + float fsr2; + float fsr5; + float fsr4; + float fsr7; + float fsr6; + float fsr9; + float fsr8; + float fsr11; + float fsr10; + float fsr13; + float fsr12; + float fsr15; + float fsr14; + float fsr17; + float fsr16; + float fsr19; + float fsr18; + float fsr21; + float fsr20; + float fsr23; + float fsr22; + float fsr25; + float fsr24; + float fsr27; + float fsr26; + float fsr29; + float fsr28; + float fsr31; + float fsr30; +#endif +} NDS32_FSR32; + +typedef struct +{ + double dsr0; + double dsr1; + double dsr2; + double dsr3; + double dsr4; + double dsr5; + double dsr6; + double dsr7; + double dsr8; + double dsr9; + double dsr10; + double dsr11; + double dsr12; + double dsr13; + double dsr14; + double dsr15; +} NDS32_DSR16; + +typedef struct +{ + double dsr0; + double dsr1; + double dsr2; + double dsr3; + double dsr4; + double dsr5; + double dsr6; + double dsr7; + double dsr8; + double dsr9; + double dsr10; + double dsr11; + double dsr12; + double dsr13; + double dsr14; + double dsr15; + double dsr16; + double dsr17; + double dsr18; + double dsr19; + double dsr20; + double dsr21; + double dsr22; + double dsr23; + double dsr24; + double dsr25; + double dsr26; + double dsr27; + double dsr28; + double dsr29; + double dsr30; + double dsr31; +} NDS32_DSR32; + +typedef struct +{ + union + { + NDS32_FSR8 fsr_s ; + NDS32_DSR4 dsr_s ; + } u ; +} NDS32_FPU8_TAB; + +typedef struct +{ + union + { + NDS32_FSR16 fsr_s ; + NDS32_DSR8 dsr_s ; + } u ; +} NDS32_FPU16_TAB; + +typedef struct +{ + union + { + NDS32_FSR32 fsr_s ; + NDS32_DSR16 dsr_s ; + } u ; +} NDS32_FPU32_TAB; + +typedef struct +{ + union + { + NDS32_FSR32 fsr_s ; + NDS32_DSR32 dsr_s ; + } u ; +} NDS32_FPU64_TAB; + +typedef struct +{ + int ipc; + int ipsw; +#if defined(NDS32_EXT_FPU_CONFIG_0) + NDS32_FPU8_TAB fpr; +#elif defined(NDS32_EXT_FPU_CONFIG_1) + NDS32_FPU16_TAB fpr; +#elif defined(NDS32_EXT_FPU_CONFIG_2) + NDS32_FPU32_TAB fpr; +#elif defined(NDS32_EXT_FPU_CONFIG_3) + NDS32_FPU64_TAB fpr; +#endif +#if __NDS32_DX_REGS__ + NDS32_DX_TAB dxr; +#endif +#if __NDS32_EXT_IFC__ + int ifc_lp; + int filler; +#endif +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS + NDS32_REG16_TAB gpr; +#else + NDS32_REG32_TAB gpr; +#endif +} NDS32_CONTEXT; + +/* Predefined Vector Definition. + + For IVIC Mode: 9 to 14 are for hardware interrupt + and 15 is for software interrupt. + For EVIC Mode: 9 to 72 are for hardware interrupt + and software interrupt can be routed to any one of them. + + You may want to define your hardware interrupts in the following way + for easy maintainance. + + IVIC mode: + #define MY_HW_IVIC_TIMER NDS32_VECTOR_INTERRUPT_HW0 + 1 + #define MY_HW_IVIC_USB NDS32_VECTOR_INTERRUPT_HW0 + 3 + EVIC mode: + #define MY_HW_EVIC_DMA NDS32_VECTOR_INTERRUPT_HW0 + 2 + #define MY_HW_EVIC_SWI NDS32_VECTOR_INTERRUPT_HW0 + 10 */ +#define NDS32_VECTOR_RESET 0 +#define NDS32_VECTOR_TLB_FILL 1 +#define NDS32_VECTOR_PTE_NOT_PRESENT 2 +#define NDS32_VECTOR_TLB_MISC 3 +#define NDS32_VECTOR_TLB_VLPT_MISS 4 +#define NDS32_VECTOR_MACHINE_ERROR 5 +#define NDS32_VECTOR_DEBUG_RELATED 6 +#define NDS32_VECTOR_GENERAL_EXCEPTION 7 +#define NDS32_VECTOR_SYSCALL 8 +#define NDS32_VECTOR_INTERRUPT_HW0 9 +#define NDS32_VECTOR_INTERRUPT_HW1 10 +#define NDS32_VECTOR_INTERRUPT_HW2 11 +#define NDS32_VECTOR_INTERRUPT_HW3 12 +#define NDS32_VECTOR_INTERRUPT_HW4 13 +#define NDS32_VECTOR_INTERRUPT_HW5 14 +#define NDS32_VECTOR_INTERRUPT_HW6 15 +#define NDS32_VECTOR_SWI 15 /* THIS IS FOR IVIC MODE ONLY */ +#define NDS32_VECTOR_INTERRUPT_HW7 16 +#define NDS32_VECTOR_INTERRUPT_HW8 17 +#define NDS32_VECTOR_INTERRUPT_HW9 18 +#define NDS32_VECTOR_INTERRUPT_HW10 19 +#define NDS32_VECTOR_INTERRUPT_HW11 20 +#define NDS32_VECTOR_INTERRUPT_HW12 21 +#define NDS32_VECTOR_INTERRUPT_HW13 22 +#define NDS32_VECTOR_INTERRUPT_HW14 23 +#define NDS32_VECTOR_INTERRUPT_HW15 24 +#define NDS32_VECTOR_INTERRUPT_HW16 25 +#define NDS32_VECTOR_INTERRUPT_HW17 26 +#define NDS32_VECTOR_INTERRUPT_HW18 27 +#define NDS32_VECTOR_INTERRUPT_HW19 28 +#define NDS32_VECTOR_INTERRUPT_HW20 29 +#define NDS32_VECTOR_INTERRUPT_HW21 30 +#define NDS32_VECTOR_INTERRUPT_HW22 31 +#define NDS32_VECTOR_INTERRUPT_HW23 32 +#define NDS32_VECTOR_INTERRUPT_HW24 33 +#define NDS32_VECTOR_INTERRUPT_HW25 34 +#define NDS32_VECTOR_INTERRUPT_HW26 35 +#define NDS32_VECTOR_INTERRUPT_HW27 36 +#define NDS32_VECTOR_INTERRUPT_HW28 37 +#define NDS32_VECTOR_INTERRUPT_HW29 38 +#define NDS32_VECTOR_INTERRUPT_HW30 39 +#define NDS32_VECTOR_INTERRUPT_HW31 40 +#define NDS32_VECTOR_INTERRUPT_HW32 41 +#define NDS32_VECTOR_INTERRUPT_HW33 42 +#define NDS32_VECTOR_INTERRUPT_HW34 43 +#define NDS32_VECTOR_INTERRUPT_HW35 44 +#define NDS32_VECTOR_INTERRUPT_HW36 45 +#define NDS32_VECTOR_INTERRUPT_HW37 46 +#define NDS32_VECTOR_INTERRUPT_HW38 47 +#define NDS32_VECTOR_INTERRUPT_HW39 48 +#define NDS32_VECTOR_INTERRUPT_HW40 49 +#define NDS32_VECTOR_INTERRUPT_HW41 50 +#define NDS32_VECTOR_INTERRUPT_HW42 51 +#define NDS32_VECTOR_INTERRUPT_HW43 52 +#define NDS32_VECTOR_INTERRUPT_HW44 53 +#define NDS32_VECTOR_INTERRUPT_HW45 54 +#define NDS32_VECTOR_INTERRUPT_HW46 55 +#define NDS32_VECTOR_INTERRUPT_HW47 56 +#define NDS32_VECTOR_INTERRUPT_HW48 57 +#define NDS32_VECTOR_INTERRUPT_HW49 58 +#define NDS32_VECTOR_INTERRUPT_HW50 59 +#define NDS32_VECTOR_INTERRUPT_HW51 60 +#define NDS32_VECTOR_INTERRUPT_HW52 61 +#define NDS32_VECTOR_INTERRUPT_HW53 62 +#define NDS32_VECTOR_INTERRUPT_HW54 63 +#define NDS32_VECTOR_INTERRUPT_HW55 64 +#define NDS32_VECTOR_INTERRUPT_HW56 65 +#define NDS32_VECTOR_INTERRUPT_HW57 66 +#define NDS32_VECTOR_INTERRUPT_HW58 67 +#define NDS32_VECTOR_INTERRUPT_HW59 68 +#define NDS32_VECTOR_INTERRUPT_HW60 69 +#define NDS32_VECTOR_INTERRUPT_HW61 70 +#define NDS32_VECTOR_INTERRUPT_HW62 71 +#define NDS32_VECTOR_INTERRUPT_HW63 72 + +#define NDS32ATTR_RESET(option) __attribute__((reset(option))) +#define NDS32ATTR_EXCEPT(type) __attribute__((exception(type))) +#define NDS32ATTR_EXCEPTION(type) __attribute__((exception(type))) +#define NDS32ATTR_INTERRUPT(type) __attribute__((interrupt(type))) +#define NDS32ATTR_ISR(type) __attribute__((interrupt(type))) + +#endif /* nds32_isr.h */ diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 084131abd04..d499020f91f 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,22 @@ +2018-08-12 Chung-Ju Wu + + * config/nds32/t-nds32-isr: Rearrange object dependency. + * config/nds32/initfini.c: Add dwarf2 unwinding support. + * config/nds32/isr-library/adj_intr_lvl.inc: Consider new extensions + and registers usage. + * config/nds32/isr-library/excp_isr.S: Ditto. + * config/nds32/isr-library/intr_isr.S: Ditto. + * config/nds32/isr-library/reset.S: Ditto. + * config/nds32/isr-library/restore_all.inc: Ditto. + * config/nds32/isr-library/restore_mac_regs.inc: Ditto. + * config/nds32/isr-library/restore_partial.inc: Ditto. + * config/nds32/isr-library/restore_usr_regs.inc: Ditto. + * config/nds32/isr-library/save_all.inc: Ditto. + * config/nds32/isr-library/save_mac_regs.inc: Ditto. + * config/nds32/isr-library/save_partial.inc: Ditto. + * config/nds32/isr-library/save_usr_regs.inc: Ditto. + * config/nds32/isr-library/vec_vid*.S: Consider 4-byte vector size. + 2018-08-11 John David Anglin * config/pa/linux-atomic.c: Update comment. diff --git a/libgcc/config/nds32/initfini.c b/libgcc/config/nds32/initfini.c index 49ca44fa659..dfbcc43f776 100644 --- a/libgcc/config/nds32/initfini.c +++ b/libgcc/config/nds32/initfini.c @@ -25,6 +25,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ +#include +/* Need header file for `struct object' type. */ +#include "../libgcc/unwind-dw2-fde.h" + /* Declare a pointer to void function type. */ typedef void (*func_ptr) (void); @@ -42,11 +46,59 @@ typedef void (*func_ptr) (void); refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__ symbol in crtinit.o, where they are defined. */ -static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"))) - = { (func_ptr) (-1) }; +static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"), used)) + = { (func_ptr) 0 }; + +static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"), used)) + = { (func_ptr) 0 }; + + +#ifdef SUPPORT_UNWINDING_DWARF2 +/* Preparation of exception handling with dwar2 mechanism registration. */ -static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"))) - = { (func_ptr) (-1) }; +asm ("\n\ + .section .eh_frame,\"aw\",@progbits\n\ + .global __EH_FRAME_BEGIN__\n\ + .type __EH_FRAME_BEGIN__, @object\n\ + .align 2\n\ +__EH_FRAME_BEGIN__:\n\ + ! Beginning location of eh_frame section\n\ + .previous\n\ +"); + +extern func_ptr __EH_FRAME_BEGIN__[]; + + +/* Note that the following two functions are going to be chained into + constructor and destructor list, repectively. So these two declarations + must be placed after __CTOR_LIST__ and __DTOR_LIST. */ +extern void __nds32_register_eh(void) __attribute__((constructor, used)); +extern void __nds32_deregister_eh(void) __attribute__((destructor, used)); + +/* Register the exception handling table as the first constructor. */ +void +__nds32_register_eh (void) +{ + static struct object object; + if (__register_frame_info) + __register_frame_info (__EH_FRAME_BEGIN__, &object); +} + +/* Unregister the exception handling table as a deconstructor. */ +void +__nds32_deregister_eh (void) +{ + static int completed = 0; + + if (completed) + return; + + if (__deregister_frame_info) + __deregister_frame_info (__EH_FRAME_BEGIN__); + + completed = 1; +} +#endif /* Run all the global destructors on exit from the program. */ @@ -63,7 +115,7 @@ static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"))) same particular root executable or shared library file. */ static void __do_global_dtors (void) -asm ("__do_global_dtors") __attribute__ ((section (".text"))); +asm ("__do_global_dtors") __attribute__ ((section (".text"), used)); static void __do_global_dtors (void) @@ -116,23 +168,37 @@ void *__dso_handle = 0; last, these words naturally end up at the very ends of the two lists contained in these two sections. */ -static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"))) +static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"), used)) = { (func_ptr) 0 }; -static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"))) +static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"), used)) = { (func_ptr) 0 }; +#ifdef SUPPORT_UNWINDING_DWARF2 +/* ZERO terminator in .eh_frame section. */ +asm ("\n\ + .section .eh_frame,\"aw\",@progbits\n\ + .global __EH_FRAME_END__\n\ + .type __EH_FRAME_END__, @object\n\ + .align 2\n\ +__EH_FRAME_END__:\n\ + ! End location of eh_frame section with ZERO terminator\n\ + .word 0\n\ + .previous\n\ +"); +#endif + /* Run all global constructors for the program. Note that they are run in reverse order. */ static void __do_global_ctors (void) -asm ("__do_global_ctors") __attribute__ ((section (".text"))); +asm ("__do_global_ctors") __attribute__ ((section (".text"), used)); static void __do_global_ctors (void) { func_ptr *p; - for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--) + for (p = __CTOR_END__ - 1; *p; p--) (*p) (); } diff --git a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc b/libgcc/config/nds32/isr-library/adj_intr_lvl.inc index 5cc1a6fc88a..275e5580ef3 100644 --- a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc +++ b/libgcc/config/nds32/isr-library/adj_intr_lvl.inc @@ -26,13 +26,26 @@ .macro ADJ_INTR_LVL #if defined(NDS32_NESTED) /* Nested handler. */ mfsr $r3, $PSW + /* By substracting 1 from $PSW, we can lower PSW.INTL + and enable GIE simultaneously. */ addi $r3, $r3, #-0x1 + #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ + ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ + #endif mtsr $r3, $PSW #elif defined(NDS32_NESTED_READY) /* Nested ready handler. */ /* Save ipc and ipsw and lower INT level. */ mfsr $r3, $PSW addi $r3, $r3, #-0x2 + #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ + ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ + #endif mtsr $r3, $PSW #else /* Not nested handler. */ + #if __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ + mfsr $r3, $PSW + ori $r3, $r3, 0x2000 /* Set PSW.AEN(b'13) */ + mtsr $r3, $PSW + #endif #endif .endm diff --git a/libgcc/config/nds32/isr-library/excp_isr.S b/libgcc/config/nds32/isr-library/excp_isr.S index f24f856e6ee..6e7de5f8fb5 100644 --- a/libgcc/config/nds32/isr-library/excp_isr.S +++ b/libgcc/config/nds32/isr-library/excp_isr.S @@ -23,6 +23,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ +#include "save_usr_regs.inc" #include "save_mac_regs.inc" #include "save_fpu_regs.inc" #include "save_fpu_regs_00.inc" @@ -32,35 +33,33 @@ #include "save_all.inc" #include "save_partial.inc" #include "adj_intr_lvl.inc" -#include "restore_mac_regs.inc" #include "restore_fpu_regs_00.inc" #include "restore_fpu_regs_01.inc" #include "restore_fpu_regs_02.inc" #include "restore_fpu_regs_03.inc" #include "restore_fpu_regs.inc" +#include "restore_mac_regs.inc" +#include "restore_usr_regs.inc" #include "restore_all.inc" #include "restore_partial.inc" + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ .align 1 -/* - First Level Handlers - 1. First Level Handlers are invokded in vector section via jump instruction - with specific names for different configurations. - 2. Naming Format: _nds32_e_SR_NT for exception handlers. - _nds32_i_SR_NT for interrupt handlers. - 2.1 All upper case letters are replaced with specific lower case letters encodings. - 2.2 SR: Saved Registers - sa: Save All regs (context) - ps: Partial Save (all caller-saved regs) - 2.3 NT: Nested Type - ns: nested - nn: not nested - nr: nested ready -*/ - -/* - This is original 16-byte vector size version. -*/ + +/* First Level Handlers + 1. First Level Handlers are invokded in vector section via jump instruction + with specific names for different configurations. + 2. Naming Format: _nds32_e_SR_NT for exception handlers. + _nds32_i_SR_NT for interrupt handlers. + 2.1 All upper case letters are replaced with specific lower case letters encodings. + 2.2 SR -- Saved Registers + sa: Save All regs (context) + ps: Partial Save (all caller-saved regs) + 2.3 NT -- Nested Type + ns: nested + nn: not nested + nr: nested ready */ + #ifdef NDS32_SAVE_ALL_REGS #if defined(NDS32_NESTED) .globl _nds32_e_sa_ns @@ -91,21 +90,26 @@ _nds32_e_ps_nn: #endif /* endif for Nest Type */ #endif /* not NDS32_SAVE_ALL_REGS */ -/* - This is 16-byte vector size version. - The vector id was restored into $r0 in vector by compiler. -*/ + +/* For 4-byte vector size version, the vector id is + extracted from $ITYPE and is set into $r0 by library. + For 16-byte vector size version, the vector id + is set into $r0 in vector section by compiler. */ + +/* Save used registers. */ #ifdef NDS32_SAVE_ALL_REGS SAVE_ALL #else SAVE_PARTIAL #endif + /* Prepare to call 2nd level handler. */ la $r2, _nds32_jmptbl_00 lw $r2, [$r2 + $r0 << #2] ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ jral $r2 - /* Restore used registers. */ + +/* Restore used registers. */ #ifdef NDS32_SAVE_ALL_REGS RESTORE_ALL #else @@ -113,6 +117,7 @@ _nds32_e_ps_nn: #endif iret + #ifdef NDS32_SAVE_ALL_REGS #if defined(NDS32_NESTED) .size _nds32_e_sa_ns, .-_nds32_e_sa_ns diff --git a/libgcc/config/nds32/isr-library/intr_isr.S b/libgcc/config/nds32/isr-library/intr_isr.S index 0431ac114fb..23ffa100206 100644 --- a/libgcc/config/nds32/isr-library/intr_isr.S +++ b/libgcc/config/nds32/isr-library/intr_isr.S @@ -23,6 +23,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ +#include "save_usr_regs.inc" #include "save_mac_regs.inc" #include "save_fpu_regs.inc" #include "save_fpu_regs_00.inc" @@ -32,35 +33,33 @@ #include "save_all.inc" #include "save_partial.inc" #include "adj_intr_lvl.inc" -#include "restore_mac_regs.inc" #include "restore_fpu_regs_00.inc" #include "restore_fpu_regs_01.inc" #include "restore_fpu_regs_02.inc" #include "restore_fpu_regs_03.inc" #include "restore_fpu_regs.inc" +#include "restore_mac_regs.inc" +#include "restore_usr_regs.inc" #include "restore_all.inc" #include "restore_partial.inc" + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ .align 1 -/* - First Level Handlers - 1. First Level Handlers are invokded in vector section via jump instruction - with specific names for different configurations. - 2. Naming Format: _nds32_e_SR_NT for exception handlers. - _nds32_i_SR_NT for interrupt handlers. - 2.1 All upper case letters are replaced with specific lower case letters encodings. - 2.2 SR: Saved Registers - sa: Save All regs (context) - ps: Partial Save (all caller-saved regs) - 2.3 NT: Nested Type - ns: nested - nn: not nested - nr: nested ready -*/ - -/* - This is original 16-byte vector size version. -*/ + +/* First Level Handlers + 1. First Level Handlers are invokded in vector section via jump instruction + with specific names for different configurations. + 2. Naming Format: _nds32_e_SR_NT for exception handlers. + _nds32_i_SR_NT for interrupt handlers. + 2.1 All upper case letters are replaced with specific lower case letters encodings. + 2.2 SR -- Saved Registers + sa: Save All regs (context) + ps: Partial Save (all caller-saved regs) + 2.3 NT -- Nested Type + ns: nested + nn: not nested + nr: nested ready */ + #ifdef NDS32_SAVE_ALL_REGS #if defined(NDS32_NESTED) .globl _nds32_i_sa_ns @@ -91,21 +90,36 @@ _nds32_i_ps_nn: #endif /* endif for Nest Type */ #endif /* not NDS32_SAVE_ALL_REGS */ -/* - This is 16-byte vector size version. - The vector id was restored into $r0 in vector by compiler. -*/ + +/* For 4-byte vector size version, the vector id is + extracted from $ITYPE and is set into $r0 by library. + For 16-byte vector size version, the vector id + is set into $r0 in vector section by compiler. */ + +/* Save used registers first. */ #ifdef NDS32_SAVE_ALL_REGS SAVE_ALL #else SAVE_PARTIAL #endif - /* Prepare to call 2nd level handler. */ + +/* According to vector size, we need to have different implementation. */ +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* Prepare to call 2nd level handler. */ + la $r2, _nds32_jmptbl_00 + lw $r2, [$r2 + $r0 << #2] + addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */ + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ + jral $r2 +#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ + /* Prepare to call 2nd level handler. */ la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */ lw $r2, [$r2 + $r0 << #2] ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ jral $r2 - /* Restore used registers. */ +#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ + +/* Restore used registers. */ #ifdef NDS32_SAVE_ALL_REGS RESTORE_ALL #else @@ -113,6 +127,7 @@ _nds32_i_ps_nn: #endif iret + #ifdef NDS32_SAVE_ALL_REGS #if defined(NDS32_NESTED) .size _nds32_i_sa_ns, .-_nds32_i_sa_ns diff --git a/libgcc/config/nds32/isr-library/reset.S b/libgcc/config/nds32/isr-library/reset.S index 78abeb2127c..2ac247e99fb 100644 --- a/libgcc/config/nds32/isr-library/reset.S +++ b/libgcc/config/nds32/isr-library/reset.S @@ -26,22 +26,18 @@ .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ .align 1 .weak _SDA_BASE_ /* For reset handler only. */ - .weak _FP_BASE_ /* For reset handler only. */ .weak _nds32_init_mem /* User defined memory initialization function. */ .globl _start .globl _nds32_reset .type _nds32_reset, @function _nds32_reset: _start: -#ifdef NDS32_EXT_EX9 - .no_ex9_begin -#endif /* Handle NMI and warm boot if any of them exists. */ beqz $sp, 1f /* Reset, NMI or warm boot? */ /* Either NMI or warm boot; save all regs. */ /* Preserve registers for context-switching. */ -#ifdef __NDS32_REDUCED_REGS__ +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS /* For 16-reg mode. */ smw.adm $r0, [$sp], $r10, #0x0 smw.adm $r15, [$sp], $r15, #0xf @@ -49,10 +45,9 @@ _start: /* For 32-reg mode. */ smw.adm $r0, [$sp], $r27, #0xf #endif -#ifdef NDS32_EXT_IFC +#if __NDS32_EXT_IFC__ mfusr $r1, $IFC_LP - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep - stack 8-byte alignment. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte alignment. */ #endif la $gp, _SDA_BASE_ /* Init GP for small data access. */ @@ -71,12 +66,11 @@ _start: bnez $r0, 1f /* If fail to resume, do cold boot. */ /* Restore registers for context-switching. */ -#ifdef NDS32_EXT_IFC - lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep - stack 8-byte alignment. */ +#if __NDS32_EXT_IFC__ + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep stack 8-byte alignment. */ mtusr $r1, $IFC_LP #endif -#ifdef __NDS32_REDUCED_REGS__ +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS /* For 16-reg mode. */ lmw.bim $r15, [$sp], $r15, #0xf lmw.bim $r0, [$sp], $r10, #0x0 @@ -88,6 +82,17 @@ _start: 1: /* Cold boot. */ +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* With vector ID feature for v3 architecture, default vector size is 4-byte. */ + /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */ + mfsr $r0, $IVB + li $r1, #0xc000 + or $r0, $r0, $r1 + xor $r0, $r0, $r1 + mtsr $r0, $IVB + dsb +#else + /* There is no vector ID feature, so the vector size must be 16-byte. */ /* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */ mfsr $r0, $IVB li $r1, #0xffff3fff @@ -95,36 +100,54 @@ _start: ori $r0, $r0, #0x4000 mtsr $r0, $IVB dsb +#endif la $gp, _SDA_BASE_ /* Init $gp. */ - la $fp, _FP_BASE_ /* Init $fp. */ la $sp, _stack /* Init $sp. */ -#ifdef NDS32_EXT_EX9 -/* - * Initialize the table base of EX9 instruction - * ex9 generation needs to disable before the ITB is set - */ - mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */ + +#if __NDS32_EXT_EX9__ +.L_init_itb: + /* Initialization for Instruction Table Base (ITB). + The symbol _ITB_BASE_ is determined by Linker. + Set $ITB only if MSC_CFG.EIT (cr4.b'24) is set. */ + mfsr $r0, $MSC_CFG srli $r0, $r0, 24 andi $r0, $r0, 0x1 - beqz $r0, 4f /* Zero means HW does not support EX9. */ - la $r0, _ITB_BASE_ /* Init $ITB. */ + beqz $r0, 4f /* Fall through ? */ + la $r0, _ITB_BASE_ mtusr $r0, $ITB - .no_ex9_end 4: #endif - la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem - may written by C language. */ + +#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__ +.L_init_fpu: + /* Initialize FPU + Set FUCOP_CTL.CP0EN (fucpr.b'0). */ + mfsr $r0, $FUCOP_CTL + ori $r0, $r0, 0x1 + mtsr $r0, $FUCOP_CTL + dsb + /* According to [bugzilla #9425], set flush-to-zero mode. + That is, set $FPCSR.DNZ(b'12) = 1. */ + FMFCSR $r0 + ori $r0, $r0, 0x1000 + FMTCSR $r0 + dsb +#endif + + /* Call DRAM init. _nds32_init_mem may written by C language. */ + la $r15, _nds32_init_mem beqz $r15, 6f jral $r15 6: l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */ jral $r15 -/* Reset handler() should never return in a RTOS or non-OS system. - In case it does return, an exception will be generated. - This exception will be caught either by default break handler or by EDM. - Default break handle may just do an infinite loop. - EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ + + /* Reset handler() should never return in a RTOS or non-OS system. + In case it does return, an exception will be generated. + This exception will be caught either by default break handler or by EDM. + Default break handle may just do an infinite loop. + EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ 5: break #0x7fff .size _nds32_reset, .-_nds32_reset diff --git a/libgcc/config/nds32/isr-library/restore_all.inc b/libgcc/config/nds32/isr-library/restore_all.inc index 74556466fa9..23cdf8c6f16 100644 --- a/libgcc/config/nds32/isr-library/restore_all.inc +++ b/libgcc/config/nds32/isr-library/restore_all.inc @@ -31,15 +31,11 @@ mtsr $r2, $IPSW RESTORE_FPU_REGS RESTORE_MAC_REGS -#ifdef NDS32_EXT_IFC - lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep - stack 8-byte alignment. */ - mtusr $r1, $IFC_LP -#endif -#ifdef __NDS32_REDUCED_REGS__ + RESTORE_USR_REGS +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */ lmw.bim $r15, [$sp], $r15, #0xf -#else /* not __NDS32_REDUCED_REGS__ */ +#else lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */ #endif .endm diff --git a/libgcc/config/nds32/isr-library/restore_mac_regs.inc b/libgcc/config/nds32/isr-library/restore_mac_regs.inc index 1e6aac669af..a4340833a76 100644 --- a/libgcc/config/nds32/isr-library/restore_mac_regs.inc +++ b/libgcc/config/nds32/isr-library/restore_mac_regs.inc @@ -24,7 +24,7 @@ . */ .macro RESTORE_MAC_REGS -#ifdef NDS32_DX_REGS +#if __NDS32_DX_REGS__ lmw.bim $r1, [$sp], $r4, #0x0 mtusr $r1, $d0.lo mtusr $r2, $d0.hi diff --git a/libgcc/config/nds32/isr-library/restore_partial.inc b/libgcc/config/nds32/isr-library/restore_partial.inc index d406a99820d..c43ad1600e1 100644 --- a/libgcc/config/nds32/isr-library/restore_partial.inc +++ b/libgcc/config/nds32/isr-library/restore_partial.inc @@ -31,15 +31,11 @@ mtsr $r1, $IPC /* Set IPC. */ mtsr $r2, $IPSW /* Set IPSW. */ #endif - RESTORE_FPU_REGS - RESTORE_MAC_REGS -#ifdef NDS32_EXT_IFC - lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep - stack 8-byte alignment. */ - mtusr $r1, $IFC_LP -#endif + RESTORE_FPU_REGS + RESTORE_MAC_REGS + RESTORE_USR_REGS lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */ -#ifdef __NDS32_REDUCED_REGS__ +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS lmw.bim $r15, [$sp], $r15, #0x2 #else lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */ diff --git a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc b/libgcc/config/nds32/isr-library/restore_usr_regs.inc similarity index 73% copy from libgcc/config/nds32/isr-library/adj_intr_lvl.inc copy to libgcc/config/nds32/isr-library/restore_usr_regs.inc index 5cc1a6fc88a..9602c741cbd 100644 --- a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc +++ b/libgcc/config/nds32/isr-library/restore_usr_regs.inc @@ -23,16 +23,20 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ -.macro ADJ_INTR_LVL -#if defined(NDS32_NESTED) /* Nested handler. */ - mfsr $r3, $PSW - addi $r3, $r3, #-0x1 - mtsr $r3, $PSW -#elif defined(NDS32_NESTED_READY) /* Nested ready handler. */ - /* Save ipc and ipsw and lower INT level. */ - mfsr $r3, $PSW - addi $r3, $r3, #-0x2 - mtsr $r3, $PSW -#else /* Not nested handler. */ +.macro RESTORE_USR_REGS +#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) + lmw.bim $r1, [$sp], $r4, #0x0 + mtusr $r1, $IFC_LP + mtusr $r2, $LB + mtusr $r3, $LE + mtusr $r4, $LC +#elif __NDS32_EXT_IFC__ + lmw.bim $r1, [$sp], $r2, #0x0 + mtusr $r1, $IFC_LP +#elif __NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__ + lmw.bim $r1, [$sp], $r4, #0x0 + mtusr $r1, $LB + mtusr $r2, $LE + mtusr $r3, $LC #endif .endm diff --git a/libgcc/config/nds32/isr-library/save_all.inc b/libgcc/config/nds32/isr-library/save_all.inc index fa08b399bb4..8886edb1f64 100644 --- a/libgcc/config/nds32/isr-library/save_all.inc +++ b/libgcc/config/nds32/isr-library/save_all.inc @@ -23,45 +23,42 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ -.macro SAVE_ALL_4B -#ifdef __NDS32_REDUCED_REGS__ +#if __NDS32_ISR_VECTOR_SIZE_4__ + +/* If vector size is 4-byte, we have to save registers + in the macro implementation. */ +.macro SAVE_ALL +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS smw.adm $r15, [$sp], $r15, #0xf smw.adm $r0, [$sp], $r10, #0x0 -#else /* not __NDS32_REDUCED_REGS__ */ +#else smw.adm $r0, [$sp], $r27, #0xf -#endif /* not __NDS32_REDUCED_REGS__ */ -#ifdef NDS32_EXT_IFC - mfusr $r1, $IFC_LP - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep - stack 8-byte alignment. */ #endif - SAVE_MAC_REGS - SAVE_FPU_REGS + SAVE_USR_REGS + SAVE_MAC_REGS + SAVE_FPU_REGS mfsr $r1, $IPC /* Get IPC. */ mfsr $r2, $IPSW /* Get IPSW. */ smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ mfsr $r0, $ITYPE /* Get VID to $r0. */ srli $r0, $r0, #5 -#ifdef __NDS32_ISA_V2__ andi $r0, $r0, #127 -#else - fexti33 $r0, #6 -#endif .endm +#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ + +/* If vector size is 16-byte, some works can be done in + the vector section generated by compiler, so that we + can implement less in the macro. */ .macro SAVE_ALL -/* SAVE_REG_TBL code has been moved to - vector table generated by compiler. */ -#ifdef NDS32_EXT_IFC - mfusr $r1, $IFC_LP - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep - stack 8-byte alignment. */ -#endif - SAVE_MAC_REGS - SAVE_FPU_REGS + SAVE_USR_REGS + SAVE_MAC_REGS + SAVE_FPU_REGS mfsr $r1, $IPC /* Get IPC. */ mfsr $r2, $IPSW /* Get IPSW. */ smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ .endm + +#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ diff --git a/libgcc/config/nds32/isr-library/save_mac_regs.inc b/libgcc/config/nds32/isr-library/save_mac_regs.inc index ff120e87a8f..a6a92307fef 100644 --- a/libgcc/config/nds32/isr-library/save_mac_regs.inc +++ b/libgcc/config/nds32/isr-library/save_mac_regs.inc @@ -24,7 +24,7 @@ . */ .macro SAVE_MAC_REGS -#ifdef NDS32_DX_REGS +#if __NDS32_DX_REGS__ mfusr $r1, $d0.lo mfusr $r2, $d0.hi mfusr $r3, $d1.lo diff --git a/libgcc/config/nds32/isr-library/save_partial.inc b/libgcc/config/nds32/isr-library/save_partial.inc index 2445e48067e..c81ebaa693c 100644 --- a/libgcc/config/nds32/isr-library/save_partial.inc +++ b/libgcc/config/nds32/isr-library/save_partial.inc @@ -23,20 +23,20 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ -.macro SAVE_PARTIAL_4B -#ifdef __NDS32_REDUCED_REGS__ +#if __NDS32_ISR_VECTOR_SIZE_4__ + +/* If vector size is 4-byte, we have to save registers + in the macro implementation. */ +.macro SAVE_PARTIAL +#if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS smw.adm $r15, [$sp], $r15, #0x2 -#else /* not __NDS32_REDUCED_REGS__ */ +#else smw.adm $r15, [$sp], $r27, #0x2 -#endif /* not __NDS32_REDUCED_REGS__ */ - smw.adm $r0, [$sp], $r5, #0x0 -#ifdef NDS32_EXT_IFC - mfusr $r1, $IFC_LP - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep - stack 8-byte alignment. */ #endif - SAVE_MAC_REGS - SAVE_FPU_REGS + smw.adm $r0, [$sp], $r5, #0x0 + SAVE_USR_REGS + SAVE_MAC_REGS + SAVE_FPU_REGS #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) mfsr $r1, $IPC /* Get IPC. */ mfsr $r2, $IPSW /* Get IPSW. */ @@ -44,26 +44,24 @@ #endif mfsr $r0, $ITYPE /* Get VID to $r0. */ srli $r0, $r0, #5 -#ifdef __NDS32_ISA_V2__ andi $r0, $r0, #127 -#else - fexti33 $r0, #6 -#endif .endm +#else /* not __NDS32_ISR_VECTOR_SIZE_4__ */ + +/* If vector size is 16-byte, some works can be done in + the vector section generated by compiler, so that we + can implement less in the macro. */ + .macro SAVE_PARTIAL -/* SAVE_CALLER_REGS code has been moved to - vector table generated by compiler. */ -#ifdef NDS32_EXT_IFC - mfusr $r1, $IFC_LP - smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep - stack 8-byte alignment. */ -#endif - SAVE_MAC_REGS - SAVE_FPU_REGS + SAVE_USR_REGS + SAVE_MAC_REGS + SAVE_FPU_REGS #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) mfsr $r1, $IPC /* Get IPC. */ mfsr $r2, $IPSW /* Get IPSW. */ smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ #endif .endm + +#endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */ diff --git a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc b/libgcc/config/nds32/isr-library/save_usr_regs.inc similarity index 62% copy from libgcc/config/nds32/isr-library/adj_intr_lvl.inc copy to libgcc/config/nds32/isr-library/save_usr_regs.inc index 5cc1a6fc88a..5a3f6183b68 100644 --- a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc +++ b/libgcc/config/nds32/isr-library/save_usr_regs.inc @@ -23,16 +23,22 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ -.macro ADJ_INTR_LVL -#if defined(NDS32_NESTED) /* Nested handler. */ - mfsr $r3, $PSW - addi $r3, $r3, #-0x1 - mtsr $r3, $PSW -#elif defined(NDS32_NESTED_READY) /* Nested ready handler. */ - /* Save ipc and ipsw and lower INT level. */ - mfsr $r3, $PSW - addi $r3, $r3, #-0x2 - mtsr $r3, $PSW -#else /* Not nested handler. */ +.macro SAVE_USR_REGS +/* Store User Special Registers according to supported ISA extension + !!! WATCH OUT !!! Take care of 8-byte alignment issue. */ +#if __NDS32_EXT_IFC__ && (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) + mfusr $r1, $IFC_LP + mfusr $r2, $LB + mfusr $r3, $LE + mfusr $r4, $LC + smw.adm $r1, [$sp], $r4, #0x0 /* Save even. Ok! */ +#elif __NDS32_EXT_IFC__ + mfusr $r1, $IFC_LP + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte aligned. */ +#elif (__NDS32_EXT_ZOL__ || __NDS32_EXT_DSP__) + mfusr $r1, $LB + mfusr $r2, $LE + mfusr $r3, $LC + smw.adm $r1, [$sp], $r4, #0x0 /* Save extra $r4 to keep stack 8-byte aligned. */ #endif .endm diff --git a/libgcc/config/nds32/isr-library/vec_vid00.S b/libgcc/config/nds32/isr-library/vec_vid00.S index b2a645c53f0..643009eb800 100644 --- a/libgcc/config/nds32/isr-library/vec_vid00.S +++ b/libgcc/config/nds32/isr-library/vec_vid00.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.00, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_00 .type _nds32_vector_00, @function _nds32_vector_00: diff --git a/libgcc/config/nds32/isr-library/vec_vid01.S b/libgcc/config/nds32/isr-library/vec_vid01.S index 9e796c70524..fd9bc8b6850 100644 --- a/libgcc/config/nds32/isr-library/vec_vid01.S +++ b/libgcc/config/nds32/isr-library/vec_vid01.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.01, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_01 .type _nds32_vector_01, @function _nds32_vector_01: diff --git a/libgcc/config/nds32/isr-library/vec_vid02.S b/libgcc/config/nds32/isr-library/vec_vid02.S index a6b34b7d63a..c5a88435cab 100644 --- a/libgcc/config/nds32/isr-library/vec_vid02.S +++ b/libgcc/config/nds32/isr-library/vec_vid02.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.02, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_02 .type _nds32_vector_02, @function _nds32_vector_02: diff --git a/libgcc/config/nds32/isr-library/vec_vid03.S b/libgcc/config/nds32/isr-library/vec_vid03.S index 680f6d9a60f..7f11fb9166b 100644 --- a/libgcc/config/nds32/isr-library/vec_vid03.S +++ b/libgcc/config/nds32/isr-library/vec_vid03.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.03, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_03 .type _nds32_vector_03, @function _nds32_vector_03: diff --git a/libgcc/config/nds32/isr-library/vec_vid04.S b/libgcc/config/nds32/isr-library/vec_vid04.S index f0b616ceb8a..de2e249b78f 100644 --- a/libgcc/config/nds32/isr-library/vec_vid04.S +++ b/libgcc/config/nds32/isr-library/vec_vid04.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.04, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_04 .type _nds32_vector_04, @function _nds32_vector_04: diff --git a/libgcc/config/nds32/isr-library/vec_vid05.S b/libgcc/config/nds32/isr-library/vec_vid05.S index 47cbcea0a51..62e1cdac4a3 100644 --- a/libgcc/config/nds32/isr-library/vec_vid05.S +++ b/libgcc/config/nds32/isr-library/vec_vid05.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.05, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_05 .type _nds32_vector_05, @function _nds32_vector_05: diff --git a/libgcc/config/nds32/isr-library/vec_vid06.S b/libgcc/config/nds32/isr-library/vec_vid06.S index 851836cf9ea..e41a60c4db4 100644 --- a/libgcc/config/nds32/isr-library/vec_vid06.S +++ b/libgcc/config/nds32/isr-library/vec_vid06.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.06, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_06 .type _nds32_vector_06, @function _nds32_vector_06: diff --git a/libgcc/config/nds32/isr-library/vec_vid07.S b/libgcc/config/nds32/isr-library/vec_vid07.S index 664ee0ca7b0..b5447a85045 100644 --- a/libgcc/config/nds32/isr-library/vec_vid07.S +++ b/libgcc/config/nds32/isr-library/vec_vid07.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.07, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_07 .type _nds32_vector_07, @function _nds32_vector_07: diff --git a/libgcc/config/nds32/isr-library/vec_vid08.S b/libgcc/config/nds32/isr-library/vec_vid08.S index 1b5534c3475..2c07dd35416 100644 --- a/libgcc/config/nds32/isr-library/vec_vid08.S +++ b/libgcc/config/nds32/isr-library/vec_vid08.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.08, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_08 .type _nds32_vector_08, @function _nds32_vector_08: diff --git a/libgcc/config/nds32/isr-library/vec_vid09.S b/libgcc/config/nds32/isr-library/vec_vid09.S index 81a56753202..e858cea5f11 100644 --- a/libgcc/config/nds32/isr-library/vec_vid09.S +++ b/libgcc/config/nds32/isr-library/vec_vid09.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.09, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_09 .type _nds32_vector_09, @function _nds32_vector_09: diff --git a/libgcc/config/nds32/isr-library/vec_vid10.S b/libgcc/config/nds32/isr-library/vec_vid10.S index 102f7cf2ae6..e8bbc0b6a2c 100644 --- a/libgcc/config/nds32/isr-library/vec_vid10.S +++ b/libgcc/config/nds32/isr-library/vec_vid10.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.10, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_10 .type _nds32_vector_10, @function _nds32_vector_10: diff --git a/libgcc/config/nds32/isr-library/vec_vid11.S b/libgcc/config/nds32/isr-library/vec_vid11.S index ade2ee5190c..92aebb41022 100644 --- a/libgcc/config/nds32/isr-library/vec_vid11.S +++ b/libgcc/config/nds32/isr-library/vec_vid11.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.11, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_11 .type _nds32_vector_11, @function _nds32_vector_11: diff --git a/libgcc/config/nds32/isr-library/vec_vid12.S b/libgcc/config/nds32/isr-library/vec_vid12.S index a5958111946..6fd050afd40 100644 --- a/libgcc/config/nds32/isr-library/vec_vid12.S +++ b/libgcc/config/nds32/isr-library/vec_vid12.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.12, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_12 .type _nds32_vector_12, @function _nds32_vector_12: diff --git a/libgcc/config/nds32/isr-library/vec_vid13.S b/libgcc/config/nds32/isr-library/vec_vid13.S index 55863be5e72..0a45c456b24 100644 --- a/libgcc/config/nds32/isr-library/vec_vid13.S +++ b/libgcc/config/nds32/isr-library/vec_vid13.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.13, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_13 .type _nds32_vector_13, @function _nds32_vector_13: diff --git a/libgcc/config/nds32/isr-library/vec_vid14.S b/libgcc/config/nds32/isr-library/vec_vid14.S index abe7f42d1df..837b8487606 100644 --- a/libgcc/config/nds32/isr-library/vec_vid14.S +++ b/libgcc/config/nds32/isr-library/vec_vid14.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.14, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_14 .type _nds32_vector_14, @function _nds32_vector_14: diff --git a/libgcc/config/nds32/isr-library/vec_vid15.S b/libgcc/config/nds32/isr-library/vec_vid15.S index 890819f3ec2..c639aa444ba 100644 --- a/libgcc/config/nds32/isr-library/vec_vid15.S +++ b/libgcc/config/nds32/isr-library/vec_vid15.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.15, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_15 .type _nds32_vector_15, @function _nds32_vector_15: diff --git a/libgcc/config/nds32/isr-library/vec_vid16.S b/libgcc/config/nds32/isr-library/vec_vid16.S index 20db62501ba..a762130631c 100644 --- a/libgcc/config/nds32/isr-library/vec_vid16.S +++ b/libgcc/config/nds32/isr-library/vec_vid16.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.16, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_16 .type _nds32_vector_16, @function _nds32_vector_16: diff --git a/libgcc/config/nds32/isr-library/vec_vid17.S b/libgcc/config/nds32/isr-library/vec_vid17.S index c1ca9f62353..b17681fcb96 100644 --- a/libgcc/config/nds32/isr-library/vec_vid17.S +++ b/libgcc/config/nds32/isr-library/vec_vid17.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.17, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_17 .type _nds32_vector_17, @function _nds32_vector_17: diff --git a/libgcc/config/nds32/isr-library/vec_vid18.S b/libgcc/config/nds32/isr-library/vec_vid18.S index ef4cbeec2e6..4166fa1957f 100644 --- a/libgcc/config/nds32/isr-library/vec_vid18.S +++ b/libgcc/config/nds32/isr-library/vec_vid18.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.18, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_18 .type _nds32_vector_18, @function _nds32_vector_18: diff --git a/libgcc/config/nds32/isr-library/vec_vid19.S b/libgcc/config/nds32/isr-library/vec_vid19.S index 5efab98f379..0d7d1de38c7 100644 --- a/libgcc/config/nds32/isr-library/vec_vid19.S +++ b/libgcc/config/nds32/isr-library/vec_vid19.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.19, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_19 .type _nds32_vector_19, @function _nds32_vector_19: diff --git a/libgcc/config/nds32/isr-library/vec_vid20.S b/libgcc/config/nds32/isr-library/vec_vid20.S index 95e124700c3..d39d74b9ad6 100644 --- a/libgcc/config/nds32/isr-library/vec_vid20.S +++ b/libgcc/config/nds32/isr-library/vec_vid20.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.20, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_20 .type _nds32_vector_20, @function _nds32_vector_20: diff --git a/libgcc/config/nds32/isr-library/vec_vid21.S b/libgcc/config/nds32/isr-library/vec_vid21.S index f3f401e25a0..deff0cf9ea9 100644 --- a/libgcc/config/nds32/isr-library/vec_vid21.S +++ b/libgcc/config/nds32/isr-library/vec_vid21.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.21, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_21 .type _nds32_vector_21, @function _nds32_vector_21: diff --git a/libgcc/config/nds32/isr-library/vec_vid22.S b/libgcc/config/nds32/isr-library/vec_vid22.S index 28d0d99795f..ebd3891af71 100644 --- a/libgcc/config/nds32/isr-library/vec_vid22.S +++ b/libgcc/config/nds32/isr-library/vec_vid22.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.22, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_22 .type _nds32_vector_22, @function _nds32_vector_22: diff --git a/libgcc/config/nds32/isr-library/vec_vid23.S b/libgcc/config/nds32/isr-library/vec_vid23.S index a8246298fed..90562e77bad 100644 --- a/libgcc/config/nds32/isr-library/vec_vid23.S +++ b/libgcc/config/nds32/isr-library/vec_vid23.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.23, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_23 .type _nds32_vector_23, @function _nds32_vector_23: diff --git a/libgcc/config/nds32/isr-library/vec_vid24.S b/libgcc/config/nds32/isr-library/vec_vid24.S index 2c0e2d81c8c..7bd344c6c26 100644 --- a/libgcc/config/nds32/isr-library/vec_vid24.S +++ b/libgcc/config/nds32/isr-library/vec_vid24.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.24, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_24 .type _nds32_vector_24, @function _nds32_vector_24: diff --git a/libgcc/config/nds32/isr-library/vec_vid25.S b/libgcc/config/nds32/isr-library/vec_vid25.S index 56f78863cef..245db6e67b0 100644 --- a/libgcc/config/nds32/isr-library/vec_vid25.S +++ b/libgcc/config/nds32/isr-library/vec_vid25.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.25, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_25 .type _nds32_vector_25, @function _nds32_vector_25: diff --git a/libgcc/config/nds32/isr-library/vec_vid26.S b/libgcc/config/nds32/isr-library/vec_vid26.S index b02163ead68..4df61ff52e4 100644 --- a/libgcc/config/nds32/isr-library/vec_vid26.S +++ b/libgcc/config/nds32/isr-library/vec_vid26.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.26, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_26 .type _nds32_vector_26, @function _nds32_vector_26: diff --git a/libgcc/config/nds32/isr-library/vec_vid27.S b/libgcc/config/nds32/isr-library/vec_vid27.S index 276d1f0b49e..50960dbd12c 100644 --- a/libgcc/config/nds32/isr-library/vec_vid27.S +++ b/libgcc/config/nds32/isr-library/vec_vid27.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.27, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_27 .type _nds32_vector_27, @function _nds32_vector_27: diff --git a/libgcc/config/nds32/isr-library/vec_vid28.S b/libgcc/config/nds32/isr-library/vec_vid28.S index 59e8cc2c4ea..e44adbb58af 100644 --- a/libgcc/config/nds32/isr-library/vec_vid28.S +++ b/libgcc/config/nds32/isr-library/vec_vid28.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.28, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_28 .type _nds32_vector_28, @function _nds32_vector_28: diff --git a/libgcc/config/nds32/isr-library/vec_vid29.S b/libgcc/config/nds32/isr-library/vec_vid29.S index 7119e254afc..f7e6c770e2b 100644 --- a/libgcc/config/nds32/isr-library/vec_vid29.S +++ b/libgcc/config/nds32/isr-library/vec_vid29.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.29, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_29 .type _nds32_vector_29, @function _nds32_vector_29: diff --git a/libgcc/config/nds32/isr-library/vec_vid30.S b/libgcc/config/nds32/isr-library/vec_vid30.S index 7c7bd5fd191..7fac25da175 100644 --- a/libgcc/config/nds32/isr-library/vec_vid30.S +++ b/libgcc/config/nds32/isr-library/vec_vid30.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.30, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_30 .type _nds32_vector_30, @function _nds32_vector_30: diff --git a/libgcc/config/nds32/isr-library/vec_vid31.S b/libgcc/config/nds32/isr-library/vec_vid31.S index bd29e03c4b8..5857765d22e 100644 --- a/libgcc/config/nds32/isr-library/vec_vid31.S +++ b/libgcc/config/nds32/isr-library/vec_vid31.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.31, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_31 .type _nds32_vector_31, @function _nds32_vector_31: diff --git a/libgcc/config/nds32/isr-library/vec_vid32.S b/libgcc/config/nds32/isr-library/vec_vid32.S index 57b8db0bbe4..bcd5dbf88c8 100644 --- a/libgcc/config/nds32/isr-library/vec_vid32.S +++ b/libgcc/config/nds32/isr-library/vec_vid32.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.32, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_32 .type _nds32_vector_32, @function _nds32_vector_32: diff --git a/libgcc/config/nds32/isr-library/vec_vid33.S b/libgcc/config/nds32/isr-library/vec_vid33.S index 609735e731d..abfed4eaf7a 100644 --- a/libgcc/config/nds32/isr-library/vec_vid33.S +++ b/libgcc/config/nds32/isr-library/vec_vid33.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.33, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_33 .type _nds32_vector_33, @function _nds32_vector_33: diff --git a/libgcc/config/nds32/isr-library/vec_vid34.S b/libgcc/config/nds32/isr-library/vec_vid34.S index 2a91328fb11..f9446bb1b07 100644 --- a/libgcc/config/nds32/isr-library/vec_vid34.S +++ b/libgcc/config/nds32/isr-library/vec_vid34.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.34, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_34 .type _nds32_vector_34, @function _nds32_vector_34: diff --git a/libgcc/config/nds32/isr-library/vec_vid35.S b/libgcc/config/nds32/isr-library/vec_vid35.S index 65dd081d7b3..8862137b38f 100644 --- a/libgcc/config/nds32/isr-library/vec_vid35.S +++ b/libgcc/config/nds32/isr-library/vec_vid35.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.35, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_35 .type _nds32_vector_35, @function _nds32_vector_35: diff --git a/libgcc/config/nds32/isr-library/vec_vid36.S b/libgcc/config/nds32/isr-library/vec_vid36.S index fa47b8e879c..dbcbbf4298f 100644 --- a/libgcc/config/nds32/isr-library/vec_vid36.S +++ b/libgcc/config/nds32/isr-library/vec_vid36.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.36, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_36 .type _nds32_vector_36, @function _nds32_vector_36: diff --git a/libgcc/config/nds32/isr-library/vec_vid37.S b/libgcc/config/nds32/isr-library/vec_vid37.S index ece845633f2..392f18bfe05 100644 --- a/libgcc/config/nds32/isr-library/vec_vid37.S +++ b/libgcc/config/nds32/isr-library/vec_vid37.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.37, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_37 .type _nds32_vector_37, @function _nds32_vector_37: diff --git a/libgcc/config/nds32/isr-library/vec_vid38.S b/libgcc/config/nds32/isr-library/vec_vid38.S index c4a12f574ef..efe6619b3a7 100644 --- a/libgcc/config/nds32/isr-library/vec_vid38.S +++ b/libgcc/config/nds32/isr-library/vec_vid38.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.38, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_38 .type _nds32_vector_38, @function _nds32_vector_38: diff --git a/libgcc/config/nds32/isr-library/vec_vid39.S b/libgcc/config/nds32/isr-library/vec_vid39.S index b3e56ed7077..238c43aec88 100644 --- a/libgcc/config/nds32/isr-library/vec_vid39.S +++ b/libgcc/config/nds32/isr-library/vec_vid39.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.39, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_39 .type _nds32_vector_39, @function _nds32_vector_39: diff --git a/libgcc/config/nds32/isr-library/vec_vid40.S b/libgcc/config/nds32/isr-library/vec_vid40.S index 01364aa4909..cf3eaa21fa6 100644 --- a/libgcc/config/nds32/isr-library/vec_vid40.S +++ b/libgcc/config/nds32/isr-library/vec_vid40.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.40, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_40 .type _nds32_vector_40, @function _nds32_vector_40: diff --git a/libgcc/config/nds32/isr-library/vec_vid41.S b/libgcc/config/nds32/isr-library/vec_vid41.S index f20beec98c0..27b7aac3dbb 100644 --- a/libgcc/config/nds32/isr-library/vec_vid41.S +++ b/libgcc/config/nds32/isr-library/vec_vid41.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.41, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_41 .type _nds32_vector_41, @function _nds32_vector_41: diff --git a/libgcc/config/nds32/isr-library/vec_vid42.S b/libgcc/config/nds32/isr-library/vec_vid42.S index 6c29f1ff5a4..bfeed46e263 100644 --- a/libgcc/config/nds32/isr-library/vec_vid42.S +++ b/libgcc/config/nds32/isr-library/vec_vid42.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.42, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_42 .type _nds32_vector_42, @function _nds32_vector_42: diff --git a/libgcc/config/nds32/isr-library/vec_vid43.S b/libgcc/config/nds32/isr-library/vec_vid43.S index 8767f998513..54640c9b4f7 100644 --- a/libgcc/config/nds32/isr-library/vec_vid43.S +++ b/libgcc/config/nds32/isr-library/vec_vid43.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.43, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_43 .type _nds32_vector_43, @function _nds32_vector_43: diff --git a/libgcc/config/nds32/isr-library/vec_vid44.S b/libgcc/config/nds32/isr-library/vec_vid44.S index 8b6f53db5a8..f617243c473 100644 --- a/libgcc/config/nds32/isr-library/vec_vid44.S +++ b/libgcc/config/nds32/isr-library/vec_vid44.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.44, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_44 .type _nds32_vector_44, @function _nds32_vector_44: diff --git a/libgcc/config/nds32/isr-library/vec_vid45.S b/libgcc/config/nds32/isr-library/vec_vid45.S index 52e344b0de4..2cfeb785b1b 100644 --- a/libgcc/config/nds32/isr-library/vec_vid45.S +++ b/libgcc/config/nds32/isr-library/vec_vid45.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.45, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_45 .type _nds32_vector_45, @function _nds32_vector_45: diff --git a/libgcc/config/nds32/isr-library/vec_vid46.S b/libgcc/config/nds32/isr-library/vec_vid46.S index f9dc0d11382..45c88477ee9 100644 --- a/libgcc/config/nds32/isr-library/vec_vid46.S +++ b/libgcc/config/nds32/isr-library/vec_vid46.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.46, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_46 .type _nds32_vector_46, @function _nds32_vector_46: diff --git a/libgcc/config/nds32/isr-library/vec_vid47.S b/libgcc/config/nds32/isr-library/vec_vid47.S index 436e7e3a977..25469e456fd 100644 --- a/libgcc/config/nds32/isr-library/vec_vid47.S +++ b/libgcc/config/nds32/isr-library/vec_vid47.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.47, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_47 .type _nds32_vector_47, @function _nds32_vector_47: diff --git a/libgcc/config/nds32/isr-library/vec_vid48.S b/libgcc/config/nds32/isr-library/vec_vid48.S index 219dfd49b19..5a001194edd 100644 --- a/libgcc/config/nds32/isr-library/vec_vid48.S +++ b/libgcc/config/nds32/isr-library/vec_vid48.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.48, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_48 .type _nds32_vector_48, @function _nds32_vector_48: diff --git a/libgcc/config/nds32/isr-library/vec_vid49.S b/libgcc/config/nds32/isr-library/vec_vid49.S index e3ba7537f08..dfe11f14017 100644 --- a/libgcc/config/nds32/isr-library/vec_vid49.S +++ b/libgcc/config/nds32/isr-library/vec_vid49.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.49, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_49 .type _nds32_vector_49, @function _nds32_vector_49: diff --git a/libgcc/config/nds32/isr-library/vec_vid50.S b/libgcc/config/nds32/isr-library/vec_vid50.S index b0b3fc2b73f..0dacd26315d 100644 --- a/libgcc/config/nds32/isr-library/vec_vid50.S +++ b/libgcc/config/nds32/isr-library/vec_vid50.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.50, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_50 .type _nds32_vector_50, @function _nds32_vector_50: diff --git a/libgcc/config/nds32/isr-library/vec_vid51.S b/libgcc/config/nds32/isr-library/vec_vid51.S index bf3011d5ccb..5ab28ef7238 100644 --- a/libgcc/config/nds32/isr-library/vec_vid51.S +++ b/libgcc/config/nds32/isr-library/vec_vid51.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.51, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_51 .type _nds32_vector_51, @function _nds32_vector_51: diff --git a/libgcc/config/nds32/isr-library/vec_vid52.S b/libgcc/config/nds32/isr-library/vec_vid52.S index eaf5f14ef25..ed00f4000d1 100644 --- a/libgcc/config/nds32/isr-library/vec_vid52.S +++ b/libgcc/config/nds32/isr-library/vec_vid52.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.52, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_52 .type _nds32_vector_52, @function _nds32_vector_52: diff --git a/libgcc/config/nds32/isr-library/vec_vid53.S b/libgcc/config/nds32/isr-library/vec_vid53.S index 3f92e56d665..564cadbf1d4 100644 --- a/libgcc/config/nds32/isr-library/vec_vid53.S +++ b/libgcc/config/nds32/isr-library/vec_vid53.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.53, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_53 .type _nds32_vector_53, @function _nds32_vector_53: diff --git a/libgcc/config/nds32/isr-library/vec_vid54.S b/libgcc/config/nds32/isr-library/vec_vid54.S index f22793fe3f2..377c524361e 100644 --- a/libgcc/config/nds32/isr-library/vec_vid54.S +++ b/libgcc/config/nds32/isr-library/vec_vid54.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.54, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_54 .type _nds32_vector_54, @function _nds32_vector_54: diff --git a/libgcc/config/nds32/isr-library/vec_vid55.S b/libgcc/config/nds32/isr-library/vec_vid55.S index 1017130a9da..497252ada22 100644 --- a/libgcc/config/nds32/isr-library/vec_vid55.S +++ b/libgcc/config/nds32/isr-library/vec_vid55.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.55, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_55 .type _nds32_vector_55, @function _nds32_vector_55: diff --git a/libgcc/config/nds32/isr-library/vec_vid56.S b/libgcc/config/nds32/isr-library/vec_vid56.S index a0923e9e791..b62534b9cbc 100644 --- a/libgcc/config/nds32/isr-library/vec_vid56.S +++ b/libgcc/config/nds32/isr-library/vec_vid56.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.56, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_56 .type _nds32_vector_56, @function _nds32_vector_56: diff --git a/libgcc/config/nds32/isr-library/vec_vid57.S b/libgcc/config/nds32/isr-library/vec_vid57.S index e711b890ef4..b1bb42d9c03 100644 --- a/libgcc/config/nds32/isr-library/vec_vid57.S +++ b/libgcc/config/nds32/isr-library/vec_vid57.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.57, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_57 .type _nds32_vector_57, @function _nds32_vector_57: diff --git a/libgcc/config/nds32/isr-library/vec_vid58.S b/libgcc/config/nds32/isr-library/vec_vid58.S index f8d90643af1..14595a527a9 100644 --- a/libgcc/config/nds32/isr-library/vec_vid58.S +++ b/libgcc/config/nds32/isr-library/vec_vid58.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.58, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_58 .type _nds32_vector_58, @function _nds32_vector_58: diff --git a/libgcc/config/nds32/isr-library/vec_vid59.S b/libgcc/config/nds32/isr-library/vec_vid59.S index 58fb6e626e3..e5be1772425 100644 --- a/libgcc/config/nds32/isr-library/vec_vid59.S +++ b/libgcc/config/nds32/isr-library/vec_vid59.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.59, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_59 .type _nds32_vector_59, @function _nds32_vector_59: diff --git a/libgcc/config/nds32/isr-library/vec_vid60.S b/libgcc/config/nds32/isr-library/vec_vid60.S index 94aa6e0ef7a..f6df9712907 100644 --- a/libgcc/config/nds32/isr-library/vec_vid60.S +++ b/libgcc/config/nds32/isr-library/vec_vid60.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.60, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_60 .type _nds32_vector_60, @function _nds32_vector_60: diff --git a/libgcc/config/nds32/isr-library/vec_vid61.S b/libgcc/config/nds32/isr-library/vec_vid61.S index 869f6c86514..4f97b043154 100644 --- a/libgcc/config/nds32/isr-library/vec_vid61.S +++ b/libgcc/config/nds32/isr-library/vec_vid61.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.61, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_61 .type _nds32_vector_61, @function _nds32_vector_61: diff --git a/libgcc/config/nds32/isr-library/vec_vid62.S b/libgcc/config/nds32/isr-library/vec_vid62.S index acc846c320b..08d1bbb2567 100644 --- a/libgcc/config/nds32/isr-library/vec_vid62.S +++ b/libgcc/config/nds32/isr-library/vec_vid62.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.62, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_62 .type _nds32_vector_62, @function _nds32_vector_62: diff --git a/libgcc/config/nds32/isr-library/vec_vid63.S b/libgcc/config/nds32/isr-library/vec_vid63.S index d0727ecdd08..2b2068c4fb5 100644 --- a/libgcc/config/nds32/isr-library/vec_vid63.S +++ b/libgcc/config/nds32/isr-library/vec_vid63.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.63, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_63 .type _nds32_vector_63, @function _nds32_vector_63: diff --git a/libgcc/config/nds32/isr-library/vec_vid64.S b/libgcc/config/nds32/isr-library/vec_vid64.S index cb1659ad3ee..2c06ea0cc90 100644 --- a/libgcc/config/nds32/isr-library/vec_vid64.S +++ b/libgcc/config/nds32/isr-library/vec_vid64.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.64, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_64 .type _nds32_vector_64, @function _nds32_vector_64: diff --git a/libgcc/config/nds32/isr-library/vec_vid65.S b/libgcc/config/nds32/isr-library/vec_vid65.S index da46481ec02..d2359fd6b2b 100644 --- a/libgcc/config/nds32/isr-library/vec_vid65.S +++ b/libgcc/config/nds32/isr-library/vec_vid65.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.65, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_65 .type _nds32_vector_65, @function _nds32_vector_65: diff --git a/libgcc/config/nds32/isr-library/vec_vid66.S b/libgcc/config/nds32/isr-library/vec_vid66.S index a8c18b804b3..69ccf368f6d 100644 --- a/libgcc/config/nds32/isr-library/vec_vid66.S +++ b/libgcc/config/nds32/isr-library/vec_vid66.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.66, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_66 .type _nds32_vector_66, @function _nds32_vector_66: diff --git a/libgcc/config/nds32/isr-library/vec_vid67.S b/libgcc/config/nds32/isr-library/vec_vid67.S index d2996a375ee..78a68cb89a9 100644 --- a/libgcc/config/nds32/isr-library/vec_vid67.S +++ b/libgcc/config/nds32/isr-library/vec_vid67.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.67, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_67 .type _nds32_vector_67, @function _nds32_vector_67: diff --git a/libgcc/config/nds32/isr-library/vec_vid68.S b/libgcc/config/nds32/isr-library/vec_vid68.S index 0c9de86b1d7..a120ec34377 100644 --- a/libgcc/config/nds32/isr-library/vec_vid68.S +++ b/libgcc/config/nds32/isr-library/vec_vid68.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.68, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_68 .type _nds32_vector_68, @function _nds32_vector_68: diff --git a/libgcc/config/nds32/isr-library/vec_vid69.S b/libgcc/config/nds32/isr-library/vec_vid69.S index 43cf748d442..e2bdd5f0442 100644 --- a/libgcc/config/nds32/isr-library/vec_vid69.S +++ b/libgcc/config/nds32/isr-library/vec_vid69.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.69, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_69 .type _nds32_vector_69, @function _nds32_vector_69: diff --git a/libgcc/config/nds32/isr-library/vec_vid70.S b/libgcc/config/nds32/isr-library/vec_vid70.S index aba3e6aede0..a5ac1f306ff 100644 --- a/libgcc/config/nds32/isr-library/vec_vid70.S +++ b/libgcc/config/nds32/isr-library/vec_vid70.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.70, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_70 .type _nds32_vector_70, @function _nds32_vector_70: diff --git a/libgcc/config/nds32/isr-library/vec_vid71.S b/libgcc/config/nds32/isr-library/vec_vid71.S index be8aaa52534..06ed89c633a 100644 --- a/libgcc/config/nds32/isr-library/vec_vid71.S +++ b/libgcc/config/nds32/isr-library/vec_vid71.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.71, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_71 .type _nds32_vector_71, @function _nds32_vector_71: diff --git a/libgcc/config/nds32/isr-library/vec_vid72.S b/libgcc/config/nds32/isr-library/vec_vid72.S index 041c89517e3..2163201b620 100644 --- a/libgcc/config/nds32/isr-library/vec_vid72.S +++ b/libgcc/config/nds32/isr-library/vec_vid72.S @@ -24,8 +24,15 @@ . */ .section .nds32_vector.72, "ax" +#if __NDS32_ISR_VECTOR_SIZE_4__ + /* The vector size is default 4-byte for v3 architecture. */ + .vec_size 4 + .align 2 +#else + /* The vector size is default 16-byte for other architectures. */ .vec_size 16 .align 4 +#endif .weak _nds32_vector_72 .type _nds32_vector_72, @function _nds32_vector_72: diff --git a/libgcc/config/nds32/t-nds32-isr b/libgcc/config/nds32/t-nds32-isr index 4f86f900395..abfd82b2248 100644 --- a/libgcc/config/nds32/t-nds32-isr +++ b/libgcc/config/nds32/t-nds32-isr @@ -23,11 +23,11 @@ # Makfile fragment rules for libnds32_isr.a to support ISR attribute extension ############################################################################### -# basic flags setting +# Basic flags setting. ISR_CFLAGS = $(CFLAGS) -c -# the object files we would like to create -LIBNDS32_ISR_16B_OBJS = \ +# The object files we would like to create. +LIBNDS32_ISR_VEC_OBJS = \ vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \ vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \ vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \ @@ -46,40 +46,9 @@ LIBNDS32_ISR_16B_OBJS = \ vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \ vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \ vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \ - vec_vid72.o \ - excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \ - excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \ - intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \ - intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \ - reset.o - -LIBNDS32_ISR_4B_OBJS = \ - vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \ - vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \ - vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \ - vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \ - vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \ - vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \ - vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \ - vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \ - vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \ - vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \ - vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \ - vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \ - vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \ - vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \ - vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \ - vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \ - vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \ - vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \ - vec_vid72_4b.o \ - excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \ - excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \ - intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \ - intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \ - reset_4b.o + vec_vid72.o -LIBNDS32_ISR_COMMON_OBJS = \ +LIBNDS32_ISR_JMP_OBJS = \ jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \ jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \ jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \ @@ -98,29 +67,32 @@ LIBNDS32_ISR_COMMON_OBJS = \ jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \ jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \ jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \ - jmptbl_vid72.o \ + jmptbl_vid72.o + +LIBNDS32_ISR_COMMON_OBJS = \ + excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \ + excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \ + intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \ + intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \ + reset.o \ nmih.o \ wrh.o -LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS) +LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_VEC_OBJS) $(LIBNDS32_ISR_JMP_OBJS) $(LIBNDS32_ISR_COMMON_OBJS) -# Build common objects for ISR library -nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o -wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o - -jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S +# Build vector vid objects for ISR library. +vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ - -# Build 16b version objects for ISR library. (no "_4b" postfix string) -vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S +# Build jump table objects for ISR library. +jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ + +# Build commen objects for ISR library. excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o @@ -160,48 +132,12 @@ intr_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S reset.o: $(srcdir)/config/nds32/isr-library/reset.S $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o -# Build 4b version objects for ISR library. -vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ - -excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o - -excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o - -excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o - -excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o - -excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o - -excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o - -intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o - -intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o - -intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o - -intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o - -intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o +nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o -intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o +wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o -reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S - $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o # The rule to create libnds32_isr.a file -- 2.11.4.GIT