From c92b4c3f5b9dd4d1f1b76c7fadf6ba8a6fda7453 Mon Sep 17 00:00:00 2001 From: dje Date: Fri, 22 Apr 2005 14:36:30 +0000 Subject: [PATCH] PR target/20813 * config/rs6000/default64.h (TARGET_DEFAULT): Add MASK_PPC_GFXOPT. * config/rs6000/rs6000.c (processor_target_table): Rename rs64a to rs64. Add MASK_PPC_GFXOPT to powerpc64 and rs64. (rs6000_init_libfuncs): Set TFmode optabs to xlq names if TARGET_XL_COMPAT. * doc/invoke.texi (PowerPC options): Change rs64a to rs64. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@98562 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/rs6000/default64.h | 3 ++- gcc/config/rs6000/rs6000.c | 25 ++++++++++++++++++------- gcc/doc/invoke.texi | 2 +- 4 files changed, 31 insertions(+), 9 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0dda76280fd..643192939d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2005-04-22 David Edelsohn + + PR target/20813 + * config/rs6000/default64.h (TARGET_DEFAULT): Add MASK_PPC_GFXOPT. + * config/rs6000/rs6000.c (processor_target_table): Rename rs64a to + rs64. Add MASK_PPC_GFXOPT to powerpc64 and rs64. + (rs6000_init_libfuncs): Set TFmode optabs to xlq names if + TARGET_XL_COMPAT. + * doc/invoke.texi (PowerPC options): Change rs64a to rs64. + 2005-04-22 Nathan Sidwell * lambda-code.c: Define VEC(int,heap), VEC(lambda_loop,heap). diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index c6ed142d69b..f94103ccce7 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -21,4 +21,5 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT \ - (MASK_POWERPC | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS) + (MASK_POWERPC | MASK_PPC_GFXOPT | \ + MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index fc4683d388b..90ffed037f6 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1161,14 +1161,15 @@ rs6000_override_options (const char *default_cpu) POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64}, {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK}, {"powerpc64", PROCESSOR_POWERPC64, - POWERPC_BASE_MASK | MASK_POWERPC64}, + POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}, {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, {"rios2", PROCESSOR_RIOS2, MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING}, {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING}, - {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64}, + {"rs64", PROCESSOR_RS64A, + POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64} }; const size_t ptt_size = ARRAY_SIZE (processor_target_table); @@ -8139,11 +8140,21 @@ rs6000_init_libfuncs (void) set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc"); } - /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */ - set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); - set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); - set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); - set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); + /* AIX/Darwin/64-bit Linux quad floating point routines. */ + if (!TARGET_XL_COMPAT) + { + set_optab_libfunc (add_optab, TFmode, "__gcc_qadd"); + set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub"); + set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul"); + set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv"); + } + else + { + set_optab_libfunc (add_optab, TFmode, "_xlqadd"); + set_optab_libfunc (sub_optab, TFmode, "_xlqsub"); + set_optab_libfunc (smul_optab, TFmode, "_xlqmul"); + set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv"); + } } else { diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 56a0fc35cfc..f273c2c51d8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -10565,7 +10565,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64}, -@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}. +@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}. @option{-mcpu=common} selects a completely generic processor. Code generated under this option will run on any POWER or PowerPC processor. -- 2.11.4.GIT