From a827513c82d669eb91d53edf2450ecf2b55351a2 Mon Sep 17 00:00:00 2001 From: meissner Date: Fri, 19 Feb 1999 20:48:27 +0000 Subject: [PATCH] Fix logical operators for cr0 git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/meissner-ppc-branch@25331 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 13 + gcc/config/rs6000/rs6000.c | 6 + gcc/config/rs6000/rs6000.md | 582 +++++++++++++++++++++++++++++++++++--------- 3 files changed, 487 insertions(+), 114 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a1946ef7246..d9739bbc75c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +1999-02-15 Michael Meissner + + * rs6000.md (logical 32-bit `.' patterns): For logical 32-bit + insns that do something and set cr0, add an alternative that does + the operation, and then sets a different flag, in order to avoid + using the costly mcrf instruction and also allow cr0 to be + clobbered in asm statements. + + * rs6000.c (and{,64}_operand): If the user did -ffixed-cr0, don't + allow andi. or andis. which always set cr0. + +==================== End of Meissner Changes ==================== + Fri Feb 19 22:47:01 1999 J"orn Rennecke * rtlanal.c (insn_first_p): Fix return value for insn == reference. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a2bfcca9f27..176a7df4b32 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1041,6 +1041,9 @@ and64_operand (op, mode) register rtx op; enum machine_mode mode; { + if (fixed_regs[68]) /* CR0 not available, don't do andi./andis. */ + return (register_operand (op, mode) || mask64_operand (op, mode)); + return (logical_operand (op, mode) || mask64_operand (op, mode)); } @@ -1053,6 +1056,9 @@ and_operand (op, mode) register rtx op; enum machine_mode mode; { + if (fixed_regs[68]) /* CR0 not available, don't do andi./andis. */ + return (register_operand (op, mode) || mask_operand (op, mode)); + return (logical_operand (op, mode) || mask_operand (op, mode)); } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 22daa14820f..67a9fafb974 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1018,23 +1018,56 @@ "nor %0,%1,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r"))] + (clobber (match_scratch:SI 2 "=r,r"))] "" - "nor. %2,%1,%1" - [(set_attr "type" "compare")]) + "@ + nor. %2,%1,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 2 ""))] + "reload_completed" + [(set (match_dup 2) + (not:SI (match_dup 1))) + (set (match_dup 0) + (compare:CC (match_dup 2) + (const_int 0)))] + "") (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (not:SI (match_dup 1)))] "" - "nor. %0,%1,%1" - [(set_attr "type" "compare")]) + "@ + nor. %0,%1,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (not:SI (match_dup 1)))] + "reload_completed" + [(set (match_dup 0) + (not:SI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1828,36 +1861,89 @@ {rlinm|rlwinm} %0,%1,0,%m2,%M2 {andil.|andi.} %0,%1,%b2 {andiu.|andis.} %0,%1,%u2" - [(set_attr "length" "4,4,4,4")]) + [(set_attr "length" "4")]) + +;; Note to set cr's other than cr0 we do the and immediate and then +;; the test again -- this avoids a mcrf which on the higher end +;; machines causes an execution serialization (define_insn "*andsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,J,L")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) + (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] "" "@ and. %3,%1,%2 {andil.|andi.} %3,%1,%b2 {andiu.|andis.} %3,%1,%u2 - {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" - [(set_attr "type" "compare,compare,compare,delayed_compare")]) + {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 + # + # + # + #" + [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") + (set_attr "length" "4,4,4,4,8,8,8,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "and_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 "")) + (clobber (match_scratch:CC 4 ""))] + "reload_completed" + [(parallel [(set (match_dup 3) + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*andsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,J,L")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (and:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] "" "@ and. %0,%1,%2 {andil.|andi.} %0,%1,%b2 {andiu.|andis.} %0,%1,%u2 - {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" - [(set_attr "type" "compare,compare,compare,delayed_compare")]) + {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 + # + # + # + #" + [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") + (set_attr "length" "4,4,4,4,8,8,8,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "and_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 ""))] + "reload_completed" + [(parallel [(set (match_dup 0) + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_expand "iorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -1893,25 +1979,63 @@ [(set_attr "length" "4,4,4")]) (define_insn "*iorsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "or. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + or. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (ior:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*iorsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ior:SI (match_dup 1) + (match_dup 2)))] "" - "or. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + or. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (ior:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") ;; Split an IOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -1963,25 +2087,63 @@ [(set_attr "length" "4,4,4")]) (define_insn "*xorsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "xor. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + xor. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (xor:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*xorsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (xor:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (xor:SI (match_dup 1) + (match_dup 2)))] "" - "xor. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + xor. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (xor:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (xor:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") ;; Split an XOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -2007,25 +2169,63 @@ "eqv %0,%1,%2") (define_insn "*eqvsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "eqv. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + eqv. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (not:SI (xor:SI (match_dup 1) + (match_dup 2)))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*eqvsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" - "eqv. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + eqv. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_short_operand" ""))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (not:SI (xor:SI (match_dup 1) + (match_dup 2))))] + "reload_completed" + [(set (match_dup 0) + (not:SI (xor:SI (match_dup 1) + (match_dup 2)))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "*andcsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2035,25 +2235,64 @@ "andc %0,%2,%1") (define_insn "*andcsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "andc. %3,%2,%1" - [(set_attr "type" "compare")]) + "@ + andc. %3,%2,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (and:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*andcsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_dup 1)) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (not:SI (match_dup 1)) + (match_dup 2)))] "" - "andc. %0,%2,%1" - [(set_attr "type" "compare")]) + "@ + andc. %0,%2,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (not:SI (match_dup 1)) + (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "*iorcsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2063,81 +2302,196 @@ "orc %0,%2,%1") (define_insn "*iorcsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "orc. %3,%2,%1" - [(set_attr "type" "compare")]) + "@ + orc. %3,%2,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (ior:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*iorcsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] "" - "orc. %0,%2,%1" + "@ + orc. %0,%2,%1 + #" [(set_attr "type" "compare")]) +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (not:SI (match_dup 1)) + (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (ior:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + (define_insn "*nandsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) + (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nand %0,%1,%2") (define_insn "*nandsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "nand. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + nand. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*nandsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] "" - "nand. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + nand. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] + "reload_completed" + [(set (match_dup 0) + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "*norsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nor %0,%1,%2") (define_insn "*norsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "nor. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + nor. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*norsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] "" - "nor. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + nor. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] + "reload_completed" + [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") ;; maskir insn. We need four forms because things might be in arbitrary ;; orders. Don't define forms that only set CR fields because these -- 2.11.4.GIT