From 48aac529353efd651f355fc92045447a8419c694 Mon Sep 17 00:00:00 2001 From: jakub Date: Fri, 9 Feb 2018 18:19:08 +0000 Subject: [PATCH] PR target/84226 * config/rs6000/vsx.md (p9_xxbrq_v16qi): Change input operand constraint from =wa to wa. Avoid a subreg on the output operand, instead use a pseudo and subreg it in a move. (p9_xxbrd_): Changed to ... (p9_xxbrd_v2di): ... this insn, without VSX_D iterator. (p9_xxbrd_v2df): New expander. (p9_xxbrw_): Changed to ... (p9_xxbrw_v4si): ... this insn, without VSX_W iterator. (p9_xxbrw_v4sf): New expander. * gcc.target/powerpc/pr84226.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@257536 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 17 +++++++++-- gcc/config/rs6000/vsx.md | 45 +++++++++++++++++++++++------- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gcc.target/powerpc/pr84226.c | 6 ++++ 4 files changed, 61 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr84226.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7f198589476..4ac7fff372a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,7 +1,20 @@ +2018-02-09 Jakub Jelinek + + PR target/84226 + * config/rs6000/vsx.md (p9_xxbrq_v16qi): Change input operand + constraint from =wa to wa. Avoid a subreg on the output operand, + instead use a pseudo and subreg it in a move. + (p9_xxbrd_): Changed to ... + (p9_xxbrd_v2di): ... this insn, without VSX_D iterator. + (p9_xxbrd_v2df): New expander. + (p9_xxbrw_): Changed to ... + (p9_xxbrw_v4si): ... this insn, without VSX_W iterator. + (p9_xxbrw_v4sf): New expander. + 2018-02-09 Sebastian Perta - *config/rx.md: updated "movsicc" expand to be matched by GCC - *testsuite/gcc.target/rx/movsicc.c: new test case + * config/rx.md: updated "movsicc" expand to be matched by GCC + * testsuite/gcc.target/rx/movsicc.c: new test case 2018-02-09 Peter Bergner diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 86efdced2a8..6f0bd09e9bb 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5363,35 +5363,60 @@ (define_expand "p9_xxbrq_v16qi" [(use (match_operand:V16QI 0 "vsx_register_operand" "=wa")) - (use (match_operand:V16QI 1 "vsx_register_operand" "=wa"))] + (use (match_operand:V16QI 1 "vsx_register_operand" "wa"))] "TARGET_P9_VECTOR" { - rtx op0 = gen_lowpart (V1TImode, operands[0]); + rtx op0 = gen_reg_rtx (V1TImode); rtx op1 = gen_lowpart (V1TImode, operands[1]); emit_insn (gen_p9_xxbrq_v1ti (op0, op1)); + emit_move_insn (operands[0], gen_lowpart (V16QImode, op0)); DONE; }) ;; Swap all bytes in each 64-bit element -(define_insn "p9_xxbrd_" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa") - (bswap:VSX_D (match_operand:VSX_D 1 "vsx_register_operand" "wa")))] +(define_insn "p9_xxbrd_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (bswap:V2DI (match_operand:V2DI 1 "vsx_register_operand" "wa")))] "TARGET_P9_VECTOR" "xxbrd %x0,%x1" [(set_attr "type" "vecperm")]) +(define_expand "p9_xxbrd_v2df" + [(use (match_operand:V2DF 0 "vsx_register_operand" "=wa")) + (use (match_operand:V2DF 1 "vsx_register_operand" "wa"))] + "TARGET_P9_VECTOR" +{ + rtx op0 = gen_reg_rtx (V2DImode); + rtx op1 = gen_lowpart (V2DImode, operands[1]); + emit_insn (gen_p9_xxbrd_v2di (op0, op1)); + emit_move_insn (operands[0], gen_lowpart (V2DFmode, op0)); + DONE; +}) + ;; Swap all bytes in each 32-bit element -(define_insn "p9_xxbrw_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") - (bswap:VSX_W (match_operand:VSX_W 1 "vsx_register_operand" "wa")))] +(define_insn "p9_xxbrw_v4si" + [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") + (bswap:V4SI (match_operand:V4SI 1 "vsx_register_operand" "wa")))] "TARGET_P9_VECTOR" "xxbrw %x0,%x1" [(set_attr "type" "vecperm")]) +(define_expand "p9_xxbrw_v4sf" + [(use (match_operand:V4SF 0 "vsx_register_operand" "=wa")) + (use (match_operand:V4SF 1 "vsx_register_operand" "wa"))] + "TARGET_P9_VECTOR" +{ + rtx op0 = gen_reg_rtx (V4SImode); + rtx op1 = gen_lowpart (V4SImode, operands[1]); + emit_insn (gen_p9_xxbrw_v4si (op0, op1)); + emit_move_insn (operands[0], gen_lowpart (V4SFmode, op0)); + DONE; +}) + ;; Swap all bytes in each element of vector (define_expand "revb_" - [(set (match_operand:VEC_REVB 0 "vsx_register_operand") - (bswap:VEC_REVB (match_operand:VEC_REVB 1 "vsx_register_operand")))] + [(use (match_operand:VEC_REVB 0 "vsx_register_operand")) + (use (match_operand:VEC_REVB 1 "vsx_register_operand"))] "" { if (TARGET_P9_VECTOR) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4536b53a751..64018db7165 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-02-09 Jakub Jelinek + + PR target/84226 + * gcc.target/powerpc/pr84226.c: New test. + 2018-02-09 Peter Bergner * gcc.target/powerpc/builtins-1-be.c : Rename duplicate test diff --git a/gcc/testsuite/gcc.target/powerpc/pr84226.c b/gcc/testsuite/gcc.target/powerpc/pr84226.c new file mode 100644 index 00000000000..aae922ba905 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr84226.c @@ -0,0 +1,6 @@ +/* PR target/84226 */ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mpower9-misc -O1" } */ + +#include "builtins-revb-runnable.c" -- 2.11.4.GIT