From 2df5a3822c084962f7d00868d1d1769bb10558a4 Mon Sep 17 00:00:00 2001 From: clyon Date: Mon, 6 Nov 2017 10:43:19 +0000 Subject: [PATCH] [ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated part 2 2017-11-06 Christophe Lyon PR target/67591 * config/arm/arm.md (*sub_shiftsi): Add predicable_short_it attribute. (*cmp_ite0): Add enabled_for_depr_it attribute. (*cmp_ite1): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@254446 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 8 ++++++++ gcc/config/arm/arm.md | 3 +++ 2 files changed, 11 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c4a360fe434..b21c5fce2ad 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-11-06 Christophe Lyon + + PR target/67591 + * config/arm/arm.md (*sub_shiftsi): Add predicable_short_it + attribute. + (*cmp_ite0): Add enabled_for_depr_it attribute. + (*cmp_ite1): Likewise. + 2017-11-06 Segher Boessenkool * config/rs6000/rs6000.c (rs6000_insn_cost): Handle TYPE_MFCR and diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ddb9d8f3590..7f6f0d24de9 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -8906,6 +8906,7 @@ "TARGET_32BIT" "sub%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") (set_attr "shift" "3") (set_attr "arch" "32,a") (set_attr "type" "alus_shift_imm,alus_shift_reg")]) @@ -9344,6 +9345,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") (set_attr "type" "multiple") (set_attr_alternative "length" [(const_int 6) @@ -9427,6 +9429,7 @@ }" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) -- 2.11.4.GIT