From 1c25284bf7ba986111f51321f3a3eabd3d385a00 Mon Sep 17 00:00:00 2001 From: jasonwucj Date: Wed, 25 Apr 2018 12:17:29 +0000 Subject: [PATCH] [NDS32] Split movdi/df if reigster number is illegal. gcc/ * config/nds32/nds32-doubleword.md: New define_split pattern for illegal register number. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@259646 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 +++++ gcc/config/nds32/nds32-doubleword.md | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3c7e29d2d7d..a0adc88433e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2018-04-25 Chung-Ju Wu + * config/nds32/nds32-doubleword.md: New define_split pattern for + illegal register number. + +2018-04-25 Chung-Ju Wu + * config/nds32/nds32.c (nds32_print_operand): Set op_value ealier. 2018-04-25 Chung-Ju Wu diff --git a/gcc/config/nds32/nds32-doubleword.md b/gcc/config/nds32/nds32-doubleword.md index 7df715a771f..4505337c3aa 100644 --- a/gcc/config/nds32/nds32-doubleword.md +++ b/gcc/config/nds32/nds32-doubleword.md @@ -118,6 +118,24 @@ ]) (set_attr "feature" " v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")]) +;; Split move_di pattern when the hard register is odd. +(define_split + [(set (match_operand:DIDF 0 "register_operand" "") + (match_operand:DIDF 1 "register_operand" ""))] + "(NDS32_IS_GPR_REGNUM (REGNO (operands[0])) + && ((REGNO (operands[0]) & 0x1) == 1)) + || (NDS32_IS_GPR_REGNUM (REGNO (operands[1])) + && ((REGNO (operands[1]) & 0x1) == 1))" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5))] + { + operands[2] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[0]); + operands[3] = gen_lowpart (SImode, operands[1]); + operands[5] = gen_highpart (SImode, operands[1]); + } +) + (define_split [(set (match_operand:DIDF 0 "register_operand" "") (match_operand:DIDF 1 "const_double_operand" ""))] -- 2.11.4.GIT