From 1376215c339900e0ec23d0d2116e419521f1df08 Mon Sep 17 00:00:00 2001 From: segher Date: Sun, 21 Sep 2014 18:04:53 +0000 Subject: [PATCH] 2014-09-21 Segher Boessenkool * config/rs6000/rs6000.md (div3): Fix comment. Use a different insn for divides by integer powers of two. (div3_sra, *div3_sra_dot, *div3_sra_dot2): New. (mod3): Fix formatting. (three anonymous define_insn and two define_split): Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@215437 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 8 +++ gcc/config/rs6000/rs6000.md | 147 +++++++++++++++++++++----------------------- 2 files changed, 79 insertions(+), 76 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 96e5094f336..944352da240 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2014-09-21 Segher Boessenkool + * config/rs6000/rs6000.md (div3): Fix comment. Use a different + insn for divides by integer powers of two. + (div3_sra, *div3_sra_dot, *div3_sra_dot2): New. + (mod3): Fix formatting. + (three anonymous define_insn and two define_split): Delete. + +2014-09-21 Segher Boessenkool + * config/rs6000/rs6000.md (ashr3, *ashr3, *ashrsi3_64, *ashr3_dot, *ashr3_dot2): Clobber CA_REGNO. (floatdisf2_internal2): Ditto. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 91bdb7d9d28..ae33e557e95 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2488,7 +2488,7 @@ (set_attr "size" "")]) -;; For powers of two we can do srai/aze for divide and then adjust for +;; For powers of two we can do sra[wd]i/addze for divide and then adjust for ;; modulus. If it isn't a power of two, force operands into register and do ;; a normal divide. (define_expand "div3" @@ -2497,10 +2497,15 @@ (match_operand:GPR 2 "reg_or_cint_operand" "")))] "" { - if (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) <= 0 - || exact_log2 (INTVAL (operands[2])) < 0) - operands[2] = force_reg (mode, operands[2]); + if (CONST_INT_P (operands[2]) + && INTVAL (operands[2]) > 0 + && exact_log2 (INTVAL (operands[2])) >= 0) + { + emit_insn (gen_div3_sra (operands[0], operands[1], operands[2])); + DONE; + } + + operands[2] = force_reg (mode, operands[2]); }) (define_insn "*div3" @@ -2512,12 +2517,71 @@ [(set_attr "type" "div") (set_attr "size" "")]) +(define_insn "div3_sra" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "exact_log2_cint_operand" "N"))) + (clobber (reg:GPR CA_REGNO))] + "" + "srai %0,%1,%p2\;addze %0,%0" + [(set_attr "type" "two") + (set_attr "length" "8")]) + +(define_insn_and_split "*div3_sra_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "exact_log2_cint_operand" "N,N")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r")) + (clobber (reg:GPR CA_REGNO))] + "mode == Pmode" + "@ + srai %0,%1,%p2\;addze. %0,%0 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(parallel [(set (match_dup 0) + (div:GPR (match_dup 1) + (match_dup 2))) + (clobber (reg:GPR CA_REGNO))]) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "two") + (set_attr "length" "8,12") + (set_attr "cell_micro" "not")]) + +(define_insn_and_split "*div3_sra_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "exact_log2_cint_operand" "N,N")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (div:GPR (match_dup 1) + (match_dup 2))) + (clobber (reg:GPR CA_REGNO))] + "mode == Pmode" + "@ + srai %0,%1,%p2\;addze. %0,%0 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(parallel [(set (match_dup 0) + (div:GPR (match_dup 1) + (match_dup 2))) + (clobber (reg:GPR CA_REGNO))]) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "two") + (set_attr "length" "8,12") + (set_attr "cell_micro" "not")]) + (define_expand "mod3" [(use (match_operand:GPR 0 "gpc_reg_operand" "")) (use (match_operand:GPR 1 "gpc_reg_operand" "")) (use (match_operand:GPR 2 "reg_or_cint_operand" ""))] "" - " { int i; rtx temp1; @@ -2535,76 +2599,7 @@ emit_insn (gen_ashl3 (temp2, temp1, GEN_INT (i))); emit_insn (gen_sub3 (operands[0], operands[1], temp2)); DONE; -}") - -(define_insn "" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "exact_log2_cint_operand" "N")))] - "" - "srai %0,%1,%p2\;addze %0,%0" - [(set_attr "type" "two") - (set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") - (match_operand:P 2 "exact_log2_cint_operand" "N,N")) - (const_int 0))) - (clobber (match_scratch:P 3 "=r,r"))] - "" - "@ - srai %3,%1,%p2\;addze. %3,%3 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12") - (set_attr "cell_micro" "not")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") - (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "exact_log2_cint_operand" - "")) - (const_int 0))) - (clobber (match_scratch:GPR 3 ""))] - "reload_completed" - [(set (match_dup 3) - (div: (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") - (match_operand:P 2 "exact_log2_cint_operand" "N,N")) - (const_int 0))) - (set (match_operand:P 0 "gpc_reg_operand" "=r,r") - (div:P (match_dup 1) (match_dup 2)))] - "" - "@ - srai %0,%1,%p2\;addze. %0,%0 - #" - [(set_attr "type" "compare") - (set_attr "length" "8,12") - (set_attr "cell_micro" "not")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") - (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "exact_log2_cint_operand" - "")) - (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (div: (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") +}) ;; Logical instructions ;; The logical instructions are mostly combined by using match_operator, -- 2.11.4.GIT