From 1186e47cd2723440ea27a01adbae5cec0ec7045c Mon Sep 17 00:00:00 2001
From: ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Fri, 2 Jun 2017 15:03:54 +0000
Subject: [PATCH] [AArch64] Add HF vector modes to lane-to-lane INS pattern

        * config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
        Use VALL_F16 iterator rather than VALL.

        * gcc.target/aarch64/hfmode_ins_1.c: New test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248835 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog                                   |  5 +++++
 gcc/config/aarch64/aarch64-simd.md              | 10 +++++-----
 gcc/testsuite/ChangeLog                         |  4 ++++
 gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c | 21 +++++++++++++++++++++
 4 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 345c3ecdc89..079f1fd61f0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -10,6 +10,11 @@
 
 2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
+	* config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
+	Use VALL_F16 iterator rather than VALL.
+
+2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
 	* config/aarch64/aarch64.c (aarch64_split_compare_and_swap):
 	Emit CBNZ inside loop when doing a strong exchange and comparing
 	against zero.  Generate the CC flags after the loop.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 6852f39c35a..693b476788e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -565,14 +565,14 @@
 )
 
 (define_insn "*aarch64_simd_vec_copy_lane<mode>"
-  [(set (match_operand:VALL 0 "register_operand" "=w")
-	(vec_merge:VALL
-	    (vec_duplicate:VALL
+  [(set (match_operand:VALL_F16 0 "register_operand" "=w")
+	(vec_merge:VALL_F16
+	    (vec_duplicate:VALL_F16
 	      (vec_select:<VEL>
-		(match_operand:VALL 3 "register_operand" "w")
+		(match_operand:VALL_F16 3 "register_operand" "w")
 		(parallel
 		  [(match_operand:SI 4 "immediate_operand" "i")])))
-	    (match_operand:VALL 1 "register_operand" "0")
+	    (match_operand:VALL_F16 1 "register_operand" "0")
 	    (match_operand:SI 2 "immediate_operand" "i")))]
   "TARGET_SIMD"
   {
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fdd4a90ddca..70a8335d5df 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -8,6 +8,10 @@
 
 2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
+	* gcc.target/aarch64/hfmode_ins_1.c: New test.
+
+2017-06-02  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
 	* gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: New test.
 
 2017-06-02  Will Schmidt  <will_schmidt@vnet.ibm.com>
diff --git a/gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c b/gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c
new file mode 100644
index 00000000000..7fafe92f490
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/hfmode_ins_1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* Check that we can perform this in a single INS without doing any DUPs.  */
+
+#include <arm_neon.h>
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b)
+{
+  return vsetq_lane_f16 (vgetq_lane_f16 (b, 2), a, 3);
+}
+
+float16x4_t
+bar (float16x4_t a, float16x4_t b)
+{
+  return vset_lane_f16 (vget_lane_f16 (b, 2), a, 3);
+}
+
+/* { dg-final { scan-assembler-times "ins\\t" 2 } } */
+/* { dg-final { scan-assembler-not "dup\\t" } } */
-- 
2.11.4.GIT