| commit | fa1f9c9ed97f703af5ac3ffd65f2c3379dea5afd | |
| author | thopre01 <thopre01@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Wed, 16 Nov 2016 18:30:56 +0000 (16 18:30 +0000) | ||
| committer | thopre01 <thopre01@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Wed, 16 Nov 2016 18:30:56 +0000 (16 18:30 +0000) | ||
| tree | 0e26028c9bf60b7ec7247434464570e6f1dc6643 | treesnapshot (tar.gz zip) |
| parent | c508be16612136a4c2428e9988b332ba80868900 | commitdiff |
Fix ICE on empty FIQ interrupt handler on ARM
2016-11-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.md (arm_addsi3): Add alternative for addition of
general register with general register or ARM constant into SP
register.
gcc/testsuite/
* gcc.target/arm/empty_fiq_handler.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242508 138bc75d-0d04-0410-961f-82ee72b054a4
2016-11-16 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.md (arm_addsi3): Add alternative for addition of
general register with general register or ARM constant into SP
register.
gcc/testsuite/
* gcc.target/arm/empty_fiq_handler.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@242508 138bc75d-0d04-0410-961f-82ee72b054a4