1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "stringpool.h"
32 #include "insn-config.h"
35 #include "diagnostic-core.h"
37 #include "stor-layout.h"
41 #include "insn-attr.h"
44 #include "tm-constrs.h"
47 /* This file should be included last. */
48 #include "target-def.h"
50 /* Array of valid operand punctuation characters. */
51 static char m32r_punct_chars
[256];
53 /* Machine-specific symbol_ref flags. */
54 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
55 #define SYMBOL_REF_MODEL(X) \
56 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
58 /* For string literals, etc. */
59 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
61 /* Forward declaration. */
62 static void m32r_option_override (void);
63 static void init_reg_tables (void);
64 static void block_move_call (rtx
, rtx
, rtx
);
65 static int m32r_is_insn (rtx
);
66 static bool m32r_legitimate_address_p (machine_mode
, rtx
, bool);
67 static rtx
m32r_legitimize_address (rtx
, rtx
, machine_mode
);
68 static bool m32r_mode_dependent_address_p (const_rtx
, addr_space_t
);
69 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
70 static void m32r_print_operand (FILE *, rtx
, int);
71 static void m32r_print_operand_address (FILE *, machine_mode
, rtx
);
72 static bool m32r_print_operand_punct_valid_p (unsigned char code
);
73 static void m32r_output_function_prologue (FILE *);
74 static void m32r_output_function_epilogue (FILE *);
76 static void m32r_file_start (void);
78 static int m32r_adjust_priority (rtx_insn
*, int);
79 static int m32r_issue_rate (void);
81 static void m32r_encode_section_info (tree
, rtx
, int);
82 static bool m32r_in_small_data_p (const_tree
);
83 static bool m32r_return_in_memory (const_tree
, const_tree
);
84 static rtx
m32r_function_value (const_tree
, const_tree
, bool);
85 static rtx
m32r_libcall_value (machine_mode
, const_rtx
);
86 static bool m32r_function_value_regno_p (const unsigned int);
87 static void m32r_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
89 static void init_idents (void);
90 static bool m32r_rtx_costs (rtx
, machine_mode
, int, int, int *, bool speed
);
91 static int m32r_memory_move_cost (machine_mode
, reg_class_t
, bool);
92 static bool m32r_pass_by_reference (cumulative_args_t
, machine_mode
,
94 static int m32r_arg_partial_bytes (cumulative_args_t
, machine_mode
,
96 static rtx
m32r_function_arg (cumulative_args_t
, machine_mode
,
98 static void m32r_function_arg_advance (cumulative_args_t
, machine_mode
,
100 static bool m32r_can_eliminate (const int, const int);
101 static void m32r_conditional_register_usage (void);
102 static void m32r_trampoline_init (rtx
, tree
, rtx
);
103 static bool m32r_legitimate_constant_p (machine_mode
, rtx
);
104 static bool m32r_attribute_identifier (const_tree
);
105 static bool m32r_hard_regno_mode_ok (unsigned int, machine_mode
);
106 static bool m32r_modes_tieable_p (machine_mode
, machine_mode
);
107 static HOST_WIDE_INT
m32r_starting_frame_offset (void);
109 /* M32R specific attributes. */
111 static const struct attribute_spec m32r_attribute_table
[] =
113 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
114 affects_type_identity, exclusions } */
115 { "interrupt", 0, 0, true, false, false, NULL
, false, NULL
},
116 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
,
118 { NULL
, 0, 0, false, false, false, NULL
, false, NULL
}
121 /* Initialize the GCC target structure. */
122 #undef TARGET_ATTRIBUTE_TABLE
123 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
124 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
125 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P m32r_attribute_identifier
128 #define TARGET_LRA_P hook_bool_void_false
130 #undef TARGET_LEGITIMATE_ADDRESS_P
131 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
132 #undef TARGET_LEGITIMIZE_ADDRESS
133 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
134 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
135 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
137 #undef TARGET_ASM_ALIGNED_HI_OP
138 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
139 #undef TARGET_ASM_ALIGNED_SI_OP
140 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
142 #undef TARGET_PRINT_OPERAND
143 #define TARGET_PRINT_OPERAND m32r_print_operand
144 #undef TARGET_PRINT_OPERAND_ADDRESS
145 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
146 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
147 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
149 #undef TARGET_ASM_FUNCTION_PROLOGUE
150 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
151 #undef TARGET_ASM_FUNCTION_EPILOGUE
152 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
154 #undef TARGET_ASM_FILE_START
155 #define TARGET_ASM_FILE_START m32r_file_start
157 #undef TARGET_SCHED_ADJUST_PRIORITY
158 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
159 #undef TARGET_SCHED_ISSUE_RATE
160 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
162 #undef TARGET_OPTION_OVERRIDE
163 #define TARGET_OPTION_OVERRIDE m32r_option_override
165 #undef TARGET_ENCODE_SECTION_INFO
166 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
167 #undef TARGET_IN_SMALL_DATA_P
168 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
171 #undef TARGET_MEMORY_MOVE_COST
172 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
173 #undef TARGET_RTX_COSTS
174 #define TARGET_RTX_COSTS m32r_rtx_costs
175 #undef TARGET_ADDRESS_COST
176 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
178 #undef TARGET_PROMOTE_PROTOTYPES
179 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
180 #undef TARGET_RETURN_IN_MEMORY
181 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
183 #undef TARGET_FUNCTION_VALUE
184 #define TARGET_FUNCTION_VALUE m32r_function_value
185 #undef TARGET_LIBCALL_VALUE
186 #define TARGET_LIBCALL_VALUE m32r_libcall_value
187 #undef TARGET_FUNCTION_VALUE_REGNO_P
188 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
190 #undef TARGET_SETUP_INCOMING_VARARGS
191 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
192 #undef TARGET_MUST_PASS_IN_STACK
193 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
194 #undef TARGET_PASS_BY_REFERENCE
195 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
196 #undef TARGET_ARG_PARTIAL_BYTES
197 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
198 #undef TARGET_FUNCTION_ARG
199 #define TARGET_FUNCTION_ARG m32r_function_arg
200 #undef TARGET_FUNCTION_ARG_ADVANCE
201 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
203 #undef TARGET_CAN_ELIMINATE
204 #define TARGET_CAN_ELIMINATE m32r_can_eliminate
206 #undef TARGET_CONDITIONAL_REGISTER_USAGE
207 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
209 #undef TARGET_TRAMPOLINE_INIT
210 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
212 #undef TARGET_LEGITIMATE_CONSTANT_P
213 #define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
215 #undef TARGET_HARD_REGNO_MODE_OK
216 #define TARGET_HARD_REGNO_MODE_OK m32r_hard_regno_mode_ok
218 #undef TARGET_MODES_TIEABLE_P
219 #define TARGET_MODES_TIEABLE_P m32r_modes_tieable_p
221 #undef TARGET_CONSTANT_ALIGNMENT
222 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
224 #undef TARGET_STARTING_FRAME_OFFSET
225 #define TARGET_STARTING_FRAME_OFFSET m32r_starting_frame_offset
227 struct gcc_target targetm
= TARGET_INITIALIZER
;
229 /* Called by m32r_option_override to initialize various things. */
236 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
237 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
238 m32r_punct_chars
['#'] = 1;
239 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
241 /* Provide default value if not specified. */
242 if (!global_options_set
.x_g_switch_value
)
243 g_switch_value
= SDATA_DEFAULT_SIZE
;
247 m32r_option_override (void)
249 /* These need to be done at start up.
250 It's convenient to do them here. */
252 SUBTARGET_OVERRIDE_OPTIONS
;
255 /* Vectors to keep interesting information about registers where it can easily
256 be got. We use to use the actual mode value as the bit number, but there
257 is (or may be) more than 32 modes now. Instead we use two tables: one
258 indexed by hard register number, and one indexed by mode. */
260 /* The purpose of m32r_mode_class is to shrink the range of modes so that
261 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
262 mapped into one m32r_mode_class mode. */
267 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
268 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
271 /* Modes for condition codes. */
272 #define C_MODES (1 << (int) C_MODE)
274 /* Modes for single-word and smaller quantities. */
275 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
277 /* Modes for double-word and smaller quantities. */
278 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
280 /* Modes for quad-word and smaller quantities. */
281 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
283 /* Modes for accumulators. */
284 #define A_MODES (1 << (int) A_MODE)
286 /* Value is 1 if register/mode pair is acceptable on arc. */
288 static const unsigned int m32r_hard_regno_modes
[FIRST_PSEUDO_REGISTER
] =
290 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
291 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
292 S_MODES
, C_MODES
, A_MODES
, A_MODES
295 static unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
297 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
300 init_reg_tables (void)
304 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
306 machine_mode m
= (machine_mode
) i
;
308 switch (GET_MODE_CLASS (m
))
311 case MODE_PARTIAL_INT
:
312 case MODE_COMPLEX_INT
:
313 if (GET_MODE_SIZE (m
) <= 4)
314 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
315 else if (GET_MODE_SIZE (m
) == 8)
316 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
317 else if (GET_MODE_SIZE (m
) == 16)
318 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
319 else if (GET_MODE_SIZE (m
) == 32)
320 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
322 m32r_mode_class
[i
] = 0;
325 case MODE_COMPLEX_FLOAT
:
326 if (GET_MODE_SIZE (m
) <= 4)
327 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
328 else if (GET_MODE_SIZE (m
) == 8)
329 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
330 else if (GET_MODE_SIZE (m
) == 16)
331 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
332 else if (GET_MODE_SIZE (m
) == 32)
333 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
335 m32r_mode_class
[i
] = 0;
338 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
341 m32r_mode_class
[i
] = 0;
346 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
349 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
350 else if (i
== ARG_POINTER_REGNUM
)
351 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
353 m32r_regno_reg_class
[i
] = NO_REGS
;
357 /* M32R specific attribute support.
359 interrupt - for interrupt functions
361 model - select code model used to access object
363 small: addresses use 24 bits, use bl to make calls
364 medium: addresses use 32 bits, use bl to make calls
365 large: addresses use 32 bits, use seth/add3/jl to make calls
367 Grep for MODEL in m32r.h for more info. */
369 static tree small_ident1
;
370 static tree small_ident2
;
371 static tree medium_ident1
;
372 static tree medium_ident2
;
373 static tree large_ident1
;
374 static tree large_ident2
;
379 if (small_ident1
== 0)
381 small_ident1
= get_identifier ("small");
382 small_ident2
= get_identifier ("__small__");
383 medium_ident1
= get_identifier ("medium");
384 medium_ident2
= get_identifier ("__medium__");
385 large_ident1
= get_identifier ("large");
386 large_ident2
= get_identifier ("__large__");
390 /* Handle an "model" attribute; arguments as in
391 struct attribute_spec.handler. */
393 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
394 tree args
, int flags ATTRIBUTE_UNUSED
,
400 arg
= TREE_VALUE (args
);
402 if (arg
!= small_ident1
403 && arg
!= small_ident2
404 && arg
!= medium_ident1
405 && arg
!= medium_ident2
406 && arg
!= large_ident1
407 && arg
!= large_ident2
)
409 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
410 IDENTIFIER_POINTER (name
));
411 *no_add_attrs
= true;
418 m32r_attribute_identifier (const_tree name
)
420 return strcmp (IDENTIFIER_POINTER (name
), "model") == 0
421 || strcmp (IDENTIFIER_POINTER (name
), "__model__") == 0;
424 /* Encode section information of DECL, which is either a VAR_DECL,
425 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
427 For the M32R we want to record:
429 - whether the object lives in .sdata/.sbss.
430 - what code model should be used to access the object
434 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
438 enum m32r_model model
;
440 default_encode_section_info (decl
, rtl
, first
);
445 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
452 id
= TREE_VALUE (TREE_VALUE (model_attr
));
454 if (id
== small_ident1
|| id
== small_ident2
)
455 model
= M32R_MODEL_SMALL
;
456 else if (id
== medium_ident1
|| id
== medium_ident2
)
457 model
= M32R_MODEL_MEDIUM
;
458 else if (id
== large_ident1
|| id
== large_ident2
)
459 model
= M32R_MODEL_LARGE
;
461 gcc_unreachable (); /* shouldn't happen */
465 if (TARGET_MODEL_SMALL
)
466 model
= M32R_MODEL_SMALL
;
467 else if (TARGET_MODEL_MEDIUM
)
468 model
= M32R_MODEL_MEDIUM
;
469 else if (TARGET_MODEL_LARGE
)
470 model
= M32R_MODEL_LARGE
;
472 gcc_unreachable (); /* shouldn't happen */
474 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
477 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
480 /* Only mark the object as being small data area addressable if
481 it hasn't been explicitly marked with a code model.
483 The user can explicitly put an object in the small data area with the
484 section attribute. If the object is in sdata/sbss and marked with a
485 code model do both [put the object in .sdata and mark it as being
486 addressed with a specific code model - don't mark it as being addressed
487 with an SDA reloc though]. This is ok and might be useful at times. If
488 the object doesn't fit the linker will give an error. */
491 m32r_in_small_data_p (const_tree decl
)
495 if (TREE_CODE (decl
) != VAR_DECL
)
498 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
501 section
= DECL_SECTION_NAME (decl
);
504 if (strcmp (section
, ".sdata") == 0 || strcmp (section
, ".sbss") == 0)
509 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
511 int size
= int_size_in_bytes (TREE_TYPE (decl
));
513 if (size
> 0 && size
<= g_switch_value
)
521 /* Do anything needed before RTL is emitted for each function. */
524 m32r_init_expanders (void)
526 /* ??? At one point there was code here. The function is left in
527 to make it easy to experiment. */
531 call_operand (rtx op
, machine_mode mode
)
536 return call_address_operand (op
, mode
);
539 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
542 small_data_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
544 if (! TARGET_SDATA_USE
)
547 if (GET_CODE (op
) == SYMBOL_REF
)
548 return SYMBOL_REF_SMALL_P (op
);
550 if (GET_CODE (op
) == CONST
551 && GET_CODE (XEXP (op
, 0)) == PLUS
552 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
553 && satisfies_constraint_J (XEXP (XEXP (op
, 0), 1)))
554 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
559 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
562 addr24_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
569 if (GET_CODE (op
) == LABEL_REF
)
570 return TARGET_ADDR24
;
572 if (GET_CODE (op
) == SYMBOL_REF
)
574 else if (GET_CODE (op
) == CONST
575 && GET_CODE (XEXP (op
, 0)) == PLUS
576 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
577 && satisfies_constraint_M (XEXP (XEXP (op
, 0), 1)))
578 sym
= XEXP (XEXP (op
, 0), 0);
582 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
586 && (CONSTANT_POOL_ADDRESS_P (sym
)
587 || LIT_NAME_P (XSTR (sym
, 0))))
593 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
596 addr32_operand (rtx op
, machine_mode mode
)
600 if (GET_CODE (op
) == LABEL_REF
)
601 return TARGET_ADDR32
;
603 if (GET_CODE (op
) == SYMBOL_REF
)
605 else if (GET_CODE (op
) == CONST
606 && GET_CODE (XEXP (op
, 0)) == PLUS
607 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
608 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
610 sym
= XEXP (XEXP (op
, 0), 0);
614 return (! addr24_operand (sym
, mode
)
615 && ! small_data_operand (sym
, mode
));
618 /* Return 1 if OP is a function that can be called with the `bl' insn. */
621 call26_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
626 if (GET_CODE (op
) == SYMBOL_REF
)
627 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
629 return TARGET_CALL26
;
632 /* Return 1 if OP is a DImode const we want to handle inline.
633 This must match the code in the movdi pattern.
634 It is used by the 'G' constraint. */
637 easy_di_const (rtx op
)
639 rtx high_rtx
, low_rtx
;
640 HOST_WIDE_INT high
, low
;
642 split_double (op
, &high_rtx
, &low_rtx
);
643 high
= INTVAL (high_rtx
);
644 low
= INTVAL (low_rtx
);
645 /* Pick constants loadable with 2 16-bit `ldi' insns. */
646 if (high
>= -128 && high
<= 127
647 && low
>= -128 && low
<= 127)
652 /* Return 1 if OP is a DFmode const we want to handle inline.
653 This must match the code in the movdf pattern.
654 It is used by the 'H' constraint. */
657 easy_df_const (rtx op
)
661 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
662 if (l
[0] == 0 && l
[1] == 0)
664 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
669 /* Return 1 if OP is (mem (reg ...)).
670 This is used in insn length calcs. */
673 memreg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
675 return MEM_P (op
) && REG_P (XEXP (op
, 0));
678 /* Return nonzero if TYPE must be passed by indirect reference. */
681 m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
682 machine_mode mode
, const_tree type
,
683 bool named ATTRIBUTE_UNUSED
)
688 size
= int_size_in_bytes (type
);
690 size
= GET_MODE_SIZE (mode
);
692 return (size
< 0 || size
> 8);
697 /* X and Y are two things to compare using CODE. Emit the compare insn and
698 return the rtx for compare [arg0 of the if_then_else].
699 If need_compare is true then the comparison insn must be generated, rather
700 than being subsumed into the following branch instruction. */
703 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
705 enum rtx_code compare_code
;
706 enum rtx_code branch_code
;
707 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
712 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
713 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
714 case LT
: compare_code
= LT
; branch_code
= NE
; break;
715 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
716 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
717 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
718 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
719 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
720 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
721 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
729 switch (compare_code
)
732 if (satisfies_constraint_P (y
) /* Reg equal to small const. */
735 rtx tmp
= gen_reg_rtx (SImode
);
737 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
741 else if (CONSTANT_P (y
)) /* Reg equal to const. */
743 rtx tmp
= force_reg (GET_MODE (x
), y
);
747 if (register_operand (y
, SImode
) /* Reg equal to reg. */
748 || y
== const0_rtx
) /* Reg equal to zero. */
750 emit_insn (gen_cmp_eqsi_insn (x
, y
));
752 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
757 if (register_operand (y
, SImode
)
758 || satisfies_constraint_P (y
))
760 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
765 emit_insn (gen_cmp_ltsi_insn (x
, y
));
772 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
773 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
778 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
780 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
781 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
785 emit_insn (gen_cmp_ltsi_insn (x
, y
));
792 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
797 if (register_operand (y
, SImode
)
798 || satisfies_constraint_P (y
))
800 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
805 emit_insn (gen_cmp_ltusi_insn (x
, y
));
812 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
813 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
818 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
820 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
821 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
825 emit_insn (gen_cmp_ltusi_insn (x
, y
));
832 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
842 /* Reg/reg equal comparison. */
843 if (compare_code
== EQ
844 && register_operand (y
, SImode
))
845 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
847 /* Reg/zero signed comparison. */
848 if ((compare_code
== EQ
|| compare_code
== LT
)
850 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
852 /* Reg/smallconst equal comparison. */
853 if (compare_code
== EQ
854 && satisfies_constraint_P (y
))
856 rtx tmp
= gen_reg_rtx (SImode
);
858 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
859 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
862 /* Reg/const equal comparison. */
863 if (compare_code
== EQ
866 rtx tmp
= force_reg (GET_MODE (x
), y
);
868 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
875 y
= force_reg (GET_MODE (x
), y
);
878 int ok_const
= reg_or_int16_operand (y
, GET_MODE (y
));
881 y
= force_reg (GET_MODE (x
), y
);
885 switch (compare_code
)
888 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
891 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
894 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
901 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
905 gen_cond_store (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
907 machine_mode mode
= GET_MODE (op0
);
909 gcc_assert (mode
== SImode
);
913 if (!register_operand (op1
, mode
))
914 op1
= force_reg (mode
, op1
);
916 if (TARGET_M32RX
|| TARGET_M32R2
)
918 if (!reg_or_zero_operand (op2
, mode
))
919 op2
= force_reg (mode
, op2
);
921 emit_insn (gen_seq_insn_m32rx (op0
, op1
, op2
));
924 if (CONST_INT_P (op2
) && INTVAL (op2
) == 0)
926 emit_insn (gen_seq_zero_insn (op0
, op1
));
930 if (!reg_or_eq_int16_operand (op2
, mode
))
931 op2
= force_reg (mode
, op2
);
933 emit_insn (gen_seq_insn (op0
, op1
, op2
));
937 if (!CONST_INT_P (op2
)
938 || (INTVAL (op2
) != 0 && satisfies_constraint_K (op2
)))
942 if (reload_completed
|| reload_in_progress
)
945 reg
= gen_reg_rtx (SImode
);
946 emit_insn (gen_xorsi3 (reg
, op1
, op2
));
949 if (!register_operand (op1
, mode
))
950 op1
= force_reg (mode
, op1
);
952 emit_insn (gen_sne_zero_insn (op0
, op1
));
967 if (!register_operand (op1
, mode
))
968 op1
= force_reg (mode
, op1
);
970 if (!reg_or_int16_operand (op2
, mode
))
971 op2
= force_reg (mode
, op2
);
973 emit_insn (gen_slt_insn (op0
, op1
, op2
));
986 if (!register_operand (op1
, mode
))
987 op1
= force_reg (mode
, op1
);
989 if (!reg_or_int16_operand (op2
, mode
))
990 op2
= force_reg (mode
, op2
);
992 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
997 if (!register_operand (op1
, mode
))
998 op1
= force_reg (mode
, op1
);
1000 if (!reg_or_int16_operand (op2
, mode
))
1001 op2
= force_reg (mode
, op2
);
1004 emit_insn (gen_sge_insn (op0
, op1
, op2
));
1006 emit_insn (gen_sgeu_insn (op0
, op1
, op2
));
1011 if (!register_operand (op1
, mode
))
1012 op1
= force_reg (mode
, op1
);
1014 if (CONST_INT_P (op2
))
1016 HOST_WIDE_INT value
= INTVAL (op2
);
1017 if (value
>= 2147483647)
1019 emit_move_insn (op0
, const1_rtx
);
1023 op2
= GEN_INT (value
+ 1);
1024 if (value
< -32768 || value
>= 32767)
1025 op2
= force_reg (mode
, op2
);
1028 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
1030 emit_insn (gen_slt_insn (op0
, op1
, op2
));
1034 if (!register_operand (op2
, mode
))
1035 op2
= force_reg (mode
, op2
);
1038 emit_insn (gen_sleu_insn (op0
, op1
, op2
));
1040 emit_insn (gen_sle_insn (op0
, op1
, op2
));
1049 /* Split a 2 word move (DI or DF) into component parts. */
1052 gen_split_move_double (rtx operands
[])
1054 machine_mode mode
= GET_MODE (operands
[0]);
1055 rtx dest
= operands
[0];
1056 rtx src
= operands
[1];
1059 /* We might have (SUBREG (MEM)) here, so just get rid of the
1060 subregs to make this code simpler. It is safe to call
1061 alter_subreg any time after reload. */
1062 if (GET_CODE (dest
) == SUBREG
)
1063 alter_subreg (&dest
, true);
1064 if (GET_CODE (src
) == SUBREG
)
1065 alter_subreg (&src
, true);
1070 int dregno
= REGNO (dest
);
1075 int sregno
= REGNO (src
);
1077 int reverse
= (dregno
== sregno
+ 1);
1079 /* We normally copy the low-numbered register first. However, if
1080 the first register operand 0 is the same as the second register of
1081 operand 1, we must copy in the opposite order. */
1082 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
1083 operand_subword (src
, reverse
, TRUE
, mode
)));
1085 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
1086 operand_subword (src
, !reverse
, TRUE
, mode
)));
1089 /* Reg = constant. */
1090 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
1093 split_double (src
, &words
[0], &words
[1]);
1094 emit_insn (gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
),
1097 emit_insn (gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
),
1102 else if (MEM_P (src
))
1104 /* If the high-address word is used in the address, we must load it
1105 last. Otherwise, load it first. */
1106 int reverse
= refers_to_regno_p (dregno
, XEXP (src
, 0));
1108 /* We used to optimize loads from single registers as
1112 if r3 were not used subsequently. However, the REG_NOTES aren't
1113 propagated correctly by the reload phase, and it can cause bad
1114 code to be generated. We could still try:
1116 ld r1,r3+; ld r2,r3; addi r3,-4
1118 which saves 2 bytes and doesn't force longword alignment. */
1119 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
1120 adjust_address (src
, SImode
,
1121 reverse
* UNITS_PER_WORD
)));
1123 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
1124 adjust_address (src
, SImode
,
1125 !reverse
* UNITS_PER_WORD
)));
1132 /* We used to optimize loads from single registers as
1136 if r3 were not used subsequently. However, the REG_NOTES aren't
1137 propagated correctly by the reload phase, and it can cause bad
1138 code to be generated. We could still try:
1140 st r1,r3; st r2,+r3; addi r3,-4
1142 which saves 2 bytes and doesn't force longword alignment. */
1143 else if (MEM_P (dest
) && REG_P (src
))
1145 emit_insn (gen_rtx_SET (adjust_address (dest
, SImode
, 0),
1146 operand_subword (src
, 0, TRUE
, mode
)));
1148 emit_insn (gen_rtx_SET (adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1149 operand_subword (src
, 1, TRUE
, mode
)));
1162 m32r_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
1163 tree type
, bool named ATTRIBUTE_UNUSED
)
1165 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1169 (((mode
== BLKmode
&& type
)
1170 ? (unsigned int) int_size_in_bytes (type
)
1171 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1174 if (*cum
>= M32R_MAX_PARM_REGS
)
1176 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1177 words
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1181 return words
* UNITS_PER_WORD
;
1184 /* The ROUND_ADVANCE* macros are local to this file. */
1185 /* Round SIZE up to a word boundary. */
1186 #define ROUND_ADVANCE(SIZE) \
1187 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1189 /* Round arg MODE/TYPE up to the next word boundary. */
1190 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1191 ((MODE) == BLKmode \
1192 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1193 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1195 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1196 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1198 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1199 a reg. This includes arguments that have to be passed by reference as the
1200 pointer to them is passed in a reg if one is available (and that is what
1202 This macro is only used in this file. */
1203 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1204 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1206 /* Determine where to put an argument to a function.
1207 Value is zero to push the argument on the stack,
1208 or a hard register in which to store the argument.
1210 MODE is the argument's machine mode.
1211 TYPE is the data type of the argument (as a tree).
1212 This is null for libcalls where that information may
1214 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1215 the preceding args and about the function being called.
1216 NAMED is nonzero if this argument is a named parameter
1217 (otherwise it is an extra parameter matching an ellipsis). */
1218 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1219 and the rest are pushed. */
1222 m32r_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1223 const_tree type ATTRIBUTE_UNUSED
,
1224 bool named ATTRIBUTE_UNUSED
)
1226 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1228 return (PASS_IN_REG_P (*cum
, mode
, type
)
1229 ? gen_rtx_REG (mode
, ROUND_ADVANCE_CUM (*cum
, mode
, type
))
1233 /* Update the data in CUM to advance over an argument
1234 of mode MODE and data type TYPE.
1235 (TYPE is null for libcalls where that information may not be available.) */
1238 m32r_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1239 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1241 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1243 *cum
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1244 + ROUND_ADVANCE_ARG (mode
, type
));
1247 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1250 m32r_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1252 cumulative_args_t dummy
= pack_cumulative_args (NULL
);
1254 return m32r_pass_by_reference (dummy
, TYPE_MODE (type
), type
, false);
1257 /* Worker function for TARGET_FUNCTION_VALUE. */
1260 m32r_function_value (const_tree valtype
,
1261 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1262 bool outgoing ATTRIBUTE_UNUSED
)
1264 return gen_rtx_REG (TYPE_MODE (valtype
), 0);
1267 /* Worker function for TARGET_LIBCALL_VALUE. */
1270 m32r_libcall_value (machine_mode mode
,
1271 const_rtx fun ATTRIBUTE_UNUSED
)
1273 return gen_rtx_REG (mode
, 0);
1276 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1278 ??? What about r1 in DI/DF values. */
1281 m32r_function_value_regno_p (const unsigned int regno
)
1283 return (regno
== 0);
1286 /* Do any needed setup for a variadic function. For the M32R, we must
1287 create a register parameter block, and then copy any anonymous arguments
1288 in registers to memory.
1290 CUM has not been updated for the last named argument which has type TYPE
1291 and mode MODE, and we rely on this fact. */
1294 m32r_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
1295 tree type
, int *pretend_size
, int no_rtl
)
1302 /* All BLKmode values are passed by reference. */
1303 gcc_assert (mode
!= BLKmode
);
1305 first_anon_arg
= (ROUND_ADVANCE_CUM (*get_cumulative_args (cum
), mode
, type
)
1306 + ROUND_ADVANCE_ARG (mode
, type
));
1308 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1310 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1311 int first_reg_offset
= first_anon_arg
;
1312 /* Size in words to "pretend" allocate. */
1313 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1316 regblock
= gen_frame_mem (BLKmode
,
1317 plus_constant (Pmode
, arg_pointer_rtx
,
1318 FIRST_PARM_OFFSET (0)));
1319 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1320 move_block_from_reg (first_reg_offset
, regblock
, size
);
1322 *pretend_size
= (size
* UNITS_PER_WORD
);
1327 /* Return true if INSN is real instruction bearing insn. */
1330 m32r_is_insn (rtx insn
)
1332 return (NONDEBUG_INSN_P (insn
)
1333 && GET_CODE (PATTERN (insn
)) != USE
1334 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
1337 /* Increase the priority of long instructions so that the
1338 short instructions are scheduled ahead of the long ones. */
1341 m32r_adjust_priority (rtx_insn
*insn
, int priority
)
1343 if (m32r_is_insn (insn
)
1344 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1351 /* Indicate how many instructions can be issued at the same time.
1352 This is sort of a lie. The m32r can issue only 1 long insn at
1353 once, but it can issue 2 short insns. The default therefore is
1354 set at 2, but this can be overridden by the command line option
1358 m32r_issue_rate (void)
1360 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1363 /* Cost functions. */
1364 /* Memory is 3 times as expensive as registers.
1365 ??? Is that the right way to look at it? */
1368 m32r_memory_move_cost (machine_mode mode
,
1369 reg_class_t rclass ATTRIBUTE_UNUSED
,
1370 bool in ATTRIBUTE_UNUSED
)
1372 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1379 m32r_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
1380 int outer_code ATTRIBUTE_UNUSED
,
1381 int opno ATTRIBUTE_UNUSED
, int *total
,
1382 bool speed ATTRIBUTE_UNUSED
)
1384 int code
= GET_CODE (x
);
1388 /* Small integers are as cheap as registers. 4 byte values can be
1389 fetched as immediate constants - let's give that the cost of an
1392 if (INT16_P (INTVAL (x
)))
1402 *total
= COSTS_N_INSNS (1);
1409 split_double (x
, &high
, &low
);
1410 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1411 + !INT16_P (INTVAL (low
)));
1416 *total
= COSTS_N_INSNS (3);
1423 *total
= COSTS_N_INSNS (10);
1431 /* Type of function DECL.
1433 The result is cached. To reset the cache at the end of a function,
1434 call with DECL = NULL_TREE. */
1436 enum m32r_function_type
1437 m32r_compute_function_type (tree decl
)
1440 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1441 /* Last function we were called for. */
1442 static tree last_fn
= NULL_TREE
;
1444 /* Resetting the cached value? */
1445 if (decl
== NULL_TREE
)
1447 fn_type
= M32R_FUNCTION_UNKNOWN
;
1448 last_fn
= NULL_TREE
;
1452 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1455 /* Compute function type. */
1456 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1457 ? M32R_FUNCTION_INTERRUPT
1458 : M32R_FUNCTION_NORMAL
);
1463 \f/* Function prologue/epilogue handlers. */
1465 /* M32R stack frames look like:
1467 Before call After call
1468 +-----------------------+ +-----------------------+
1470 high | local variables, | | local variables, |
1471 mem | reg save area, etc. | | reg save area, etc. |
1473 +-----------------------+ +-----------------------+
1475 | arguments on stack. | | arguments on stack. |
1477 SP+0->+-----------------------+ +-----------------------+
1478 | reg parm save area, |
1479 | only created for |
1480 | variable argument |
1482 +-----------------------+
1483 | previous frame ptr |
1484 +-----------------------+
1486 | register save area |
1488 +-----------------------+
1490 +-----------------------+
1494 +-----------------------+
1496 | alloca allocations |
1498 +-----------------------+
1500 low | arguments on stack |
1502 SP+0->+-----------------------+
1505 1) The "reg parm save area" does not exist for non variable argument fns.
1506 2) The "reg parm save area" can be eliminated completely if we saved regs
1507 containing anonymous args separately but that complicates things too
1508 much (so it's not done).
1509 3) The return address is saved after the register save area so as to have as
1510 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1512 /* Structure to be filled in by m32r_compute_frame_size with register
1513 save masks, and offsets for the current function. */
1514 struct m32r_frame_info
1516 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1517 unsigned int extra_size
; /* # bytes of extra stuff. */
1518 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1519 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1520 unsigned int reg_size
; /* # bytes needed to store regs. */
1521 unsigned int var_size
; /* # bytes that variables take up. */
1522 unsigned int gmask
; /* Mask of saved gp registers. */
1523 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1524 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1525 int initialized
; /* Nonzero if frame size already calculated. */
1528 /* Current frame information calculated by m32r_compute_frame_size. */
1529 static struct m32r_frame_info current_frame_info
;
1531 /* Zero structure to initialize current_frame_info. */
1532 static struct m32r_frame_info zero_frame_info
;
1534 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1535 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1537 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1538 The return address and frame pointer are treated separately.
1539 Don't consider them here. */
1540 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1541 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1542 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1544 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1545 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1547 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1548 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1550 /* Return the bytes needed to compute the frame pointer from the current
1553 SIZE is the size needed for local variables. */
1556 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1559 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1560 unsigned int reg_size
;
1562 enum m32r_function_type fn_type
;
1564 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1567 var_size
= M32R_STACK_ALIGN (size
);
1568 args_size
= M32R_STACK_ALIGN (crtl
->outgoing_args_size
);
1569 pretend_size
= crtl
->args
.pretend_args_size
;
1570 extra_size
= FIRST_PARM_OFFSET (0);
1571 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1575 /* See if this is an interrupt handler. Call used registers must be saved
1577 fn_type
= m32r_compute_function_type (current_function_decl
);
1578 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1580 /* Calculate space needed for registers. */
1581 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1583 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1584 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1586 reg_size
+= UNITS_PER_WORD
;
1587 gmask
|= 1 << regno
;
1591 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1592 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1594 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1596 total_size
+= reg_size
;
1598 /* ??? Not sure this is necessary, and I don't think the epilogue
1599 handler will do the right thing if this changes total_size. */
1600 total_size
= M32R_STACK_ALIGN (total_size
);
1602 /* frame_size = total_size - (pretend_size + reg_size); */
1604 /* Save computed information. */
1605 current_frame_info
.total_size
= total_size
;
1606 current_frame_info
.extra_size
= extra_size
;
1607 current_frame_info
.pretend_size
= pretend_size
;
1608 current_frame_info
.var_size
= var_size
;
1609 current_frame_info
.args_size
= args_size
;
1610 current_frame_info
.reg_size
= reg_size
;
1611 current_frame_info
.gmask
= gmask
;
1612 current_frame_info
.initialized
= reload_completed
;
1614 /* Ok, we're done. */
1618 /* Worker function for TARGET_CAN_ELIMINATE. */
1621 m32r_can_eliminate (const int from
, const int to
)
1623 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1624 ? ! frame_pointer_needed
1629 /* The table we use to reference PIC data. */
1630 static rtx global_offset_table
;
1633 m32r_reload_lr (rtx sp
, int size
)
1635 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1638 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, sp
)));
1639 else if (size
< 32768)
1640 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
,
1641 gen_rtx_PLUS (Pmode
, sp
,
1645 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1647 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1648 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1649 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, tmp
)));
1656 m32r_load_pic_register (void)
1658 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1659 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1660 GEN_INT (TARGET_MODEL_SMALL
)));
1662 /* Need to emit this whether or not we obey regdecls,
1663 since setjmp/longjmp can cause life info to screw up. */
1664 emit_use (pic_offset_table_rtx
);
1667 /* Expand the m32r prologue as a series of insns. */
1670 m32r_expand_prologue (void)
1675 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1678 if (! current_frame_info
.initialized
)
1679 m32r_compute_frame_size (get_frame_size ());
1681 if (flag_stack_usage_info
)
1682 current_function_static_stack_size
= current_frame_info
.total_size
;
1684 gmask
= current_frame_info
.gmask
;
1686 /* These cases shouldn't happen. Catch them now. */
1687 gcc_assert (current_frame_info
.total_size
|| !gmask
);
1689 /* Allocate space for register arguments if this is a variadic function. */
1690 if (current_frame_info
.pretend_size
!= 0)
1692 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1693 the wrong result on a 64-bit host. */
1694 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1695 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1697 GEN_INT (-pretend_size
)));
1700 /* Save any registers we need to and set up fp. */
1701 if (current_frame_info
.save_fp
)
1702 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1704 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1706 /* Save any needed call-saved regs (and call-used if this is an
1707 interrupt handler). */
1708 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1710 if ((gmask
& (1 << regno
)) != 0)
1711 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1712 gen_rtx_REG (Pmode
, regno
)));
1715 if (current_frame_info
.save_lr
)
1716 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1717 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1719 /* Allocate the stack frame. */
1720 frame_size
= (current_frame_info
.total_size
1721 - (current_frame_info
.pretend_size
1722 + current_frame_info
.reg_size
));
1724 if (frame_size
== 0)
1725 ; /* Nothing to do. */
1726 else if (frame_size
<= 32768)
1727 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1728 GEN_INT (-frame_size
)));
1731 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1733 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1734 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1737 if (frame_pointer_needed
)
1738 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1741 /* Push lr for mcount (form_pc, x). */
1742 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1743 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1747 m32r_load_pic_register ();
1748 m32r_reload_lr (stack_pointer_rtx
,
1749 (crtl
->profile
? 0 : frame_size
));
1752 if (crtl
->profile
&& !pic_reg_used
)
1753 emit_insn (gen_blockage ());
1757 /* Set up the stack and frame pointer (if desired) for the function.
1758 Note, if this is changed, you need to mirror the changes in
1759 m32r_compute_frame_size which calculates the prolog size. */
1762 m32r_output_function_prologue (FILE * file
)
1764 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1766 /* If this is an interrupt handler, mark it as such. */
1767 if (M32R_INTERRUPT_P (fn_type
))
1768 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1770 if (! current_frame_info
.initialized
)
1771 m32r_compute_frame_size (get_frame_size ());
1773 /* This is only for the human reader. */
1775 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1777 current_frame_info
.var_size
,
1778 current_frame_info
.reg_size
/ 4,
1779 current_frame_info
.args_size
,
1780 current_frame_info
.extra_size
);
1783 /* Output RTL to pop register REGNO from the stack. */
1790 x
= emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode
, regno
),
1791 stack_pointer_rtx
));
1792 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
1795 /* Expand the m32r epilogue as a series of insns. */
1798 m32r_expand_epilogue (void)
1801 int noepilogue
= FALSE
;
1804 gcc_assert (current_frame_info
.initialized
);
1805 total_size
= current_frame_info
.total_size
;
1807 if (total_size
== 0)
1809 rtx_insn
*insn
= get_last_insn ();
1811 /* If the last insn was a BARRIER, we don't have to write any code
1812 because a jump (aka return) was put there. */
1813 if (insn
&& NOTE_P (insn
))
1814 insn
= prev_nonnote_insn (insn
);
1815 if (insn
&& BARRIER_P (insn
))
1821 unsigned int var_size
= current_frame_info
.var_size
;
1822 unsigned int args_size
= current_frame_info
.args_size
;
1823 unsigned int gmask
= current_frame_info
.gmask
;
1824 int can_trust_sp_p
= !cfun
->calls_alloca
;
1826 if (flag_exceptions
)
1827 emit_insn (gen_blockage ());
1829 /* The first thing to do is point the sp at the bottom of the register
1833 unsigned int reg_offset
= var_size
+ args_size
;
1835 if (reg_offset
== 0)
1836 ; /* Nothing to do. */
1837 else if (reg_offset
< 32768)
1838 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1839 GEN_INT (reg_offset
)));
1842 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1844 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1845 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1849 else if (frame_pointer_needed
)
1851 unsigned int reg_offset
= var_size
+ args_size
;
1853 if (reg_offset
== 0)
1854 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1855 else if (reg_offset
< 32768)
1856 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_rtx
,
1857 GEN_INT (reg_offset
)));
1860 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1862 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1863 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1864 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1871 if (current_frame_info
.save_lr
)
1872 pop (RETURN_ADDR_REGNUM
);
1874 /* Restore any saved registers, in reverse order of course. */
1875 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1876 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1878 if ((gmask
& (1L << regno
)) != 0)
1882 if (current_frame_info
.save_fp
)
1883 pop (FRAME_POINTER_REGNUM
);
1885 /* Remove varargs area if present. */
1886 if (current_frame_info
.pretend_size
!= 0)
1887 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1888 GEN_INT (current_frame_info
.pretend_size
)));
1890 emit_insn (gen_blockage ());
1894 /* Do any necessary cleanup after a function to restore stack, frame,
1898 m32r_output_function_epilogue (FILE *)
1900 /* Reset state info for each function. */
1901 current_frame_info
= zero_frame_info
;
1902 m32r_compute_function_type (NULL_TREE
);
1905 /* Return nonzero if this function is known to have a null or 1 instruction
1909 direct_return (void)
1911 if (!reload_completed
)
1914 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl
)))
1917 if (! current_frame_info
.initialized
)
1918 m32r_compute_frame_size (get_frame_size ());
1920 return current_frame_info
.total_size
== 0;
1927 m32r_legitimate_pic_operand_p (rtx x
)
1929 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1932 if (GET_CODE (x
) == CONST
1933 && GET_CODE (XEXP (x
, 0)) == PLUS
1934 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1935 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1936 && (CONST_INT_P (XEXP (XEXP (x
, 0), 1))))
1943 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1946 printf("m32r_legitimize_pic_address()\n");
1949 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1951 rtx pic_ref
, address
;
1956 gcc_assert (!reload_in_progress
&& !reload_completed
);
1957 reg
= gen_reg_rtx (Pmode
);
1963 address
= gen_reg_rtx (Pmode
);
1967 crtl
->uses_pic_offset_table
= 1;
1969 if (GET_CODE (orig
) == LABEL_REF
1970 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
1972 emit_insn (gen_gotoff_load_addr (reg
, orig
));
1973 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1977 emit_insn (gen_pic_load_addr (address
, orig
));
1979 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
1980 pic_ref
= gen_const_mem (Pmode
, address
);
1981 emit_move_insn (reg
, pic_ref
);
1984 else if (GET_CODE (orig
) == CONST
)
1988 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1989 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
1994 gcc_assert (!reload_in_progress
&& !reload_completed
);
1995 reg
= gen_reg_rtx (Pmode
);
1998 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2000 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
2002 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
2004 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
2009 if (CONST_INT_P (offset
))
2011 if (INT16_P (INTVAL (offset
)))
2012 return plus_constant (Pmode
, base
, INTVAL (offset
));
2015 gcc_assert (! reload_in_progress
&& ! reload_completed
);
2016 offset
= force_reg (Pmode
, offset
);
2020 return gen_rtx_PLUS (Pmode
, base
, offset
);
2027 m32r_legitimize_address (rtx x
, rtx orig_x ATTRIBUTE_UNUSED
,
2028 machine_mode mode ATTRIBUTE_UNUSED
)
2031 return m32r_legitimize_pic_address (x
, NULL_RTX
);
2036 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2039 m32r_mode_dependent_address_p (const_rtx addr
, addr_space_t as ATTRIBUTE_UNUSED
)
2041 if (GET_CODE (addr
) == LO_SUM
)
2047 /* Nested function support. */
2049 /* Emit RTL insns to initialize the variable parts of a trampoline.
2050 FNADDR is an RTX for the address of the function's pure code.
2051 CXT is an RTX for the static chain value for the function. */
2054 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
2055 rtx fnaddr ATTRIBUTE_UNUSED
,
2056 rtx cxt ATTRIBUTE_UNUSED
)
2061 m32r_file_start (void)
2063 default_file_start ();
2065 if (flag_verbose_asm
)
2066 fprintf (asm_out_file
,
2067 "%s M32R/D special options: -G %d\n",
2068 ASM_COMMENT_START
, g_switch_value
);
2070 if (TARGET_LITTLE_ENDIAN
)
2071 fprintf (asm_out_file
, "\t.little\n");
2074 /* Print operand X (an rtx) in assembler syntax to file FILE.
2075 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2076 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2079 m32r_print_operand (FILE * file
, rtx x
, int code
)
2085 /* The 's' and 'p' codes are used by output_block_move() to
2086 indicate post-increment 's'tores and 'p're-increment loads. */
2089 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2091 output_operand_lossage ("invalid operand to %%s code");
2096 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2098 output_operand_lossage ("invalid operand to %%p code");
2102 /* Write second word of DImode or DFmode reference,
2103 register or memory. */
2105 fputs (reg_names
[REGNO (x
)+1], file
);
2108 machine_mode mode
= GET_MODE (x
);
2110 fprintf (file
, "@(");
2111 /* Handle possible auto-increment. Since it is pre-increment and
2112 we have already done it, we can just use an offset of four. */
2113 /* ??? This is taken from rs6000.c I think. I don't think it is
2114 currently necessary, but keep it around. */
2115 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2116 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2117 output_address (mode
, plus_constant (Pmode
,
2118 XEXP (XEXP (x
, 0), 0), 4));
2120 output_address (mode
, plus_constant (Pmode
, XEXP (x
, 0), 4));
2124 output_operand_lossage ("invalid operand to %%R code");
2127 case 'H' : /* High word. */
2128 case 'L' : /* Low word. */
2131 /* L = least significant word, H = most significant word. */
2132 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2133 fputs (reg_names
[REGNO (x
)], file
);
2135 fputs (reg_names
[REGNO (x
)+1], file
);
2137 else if (CONST_INT_P (x
)
2138 || GET_CODE (x
) == CONST_DOUBLE
)
2142 split_double (x
, &first
, &second
);
2143 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2144 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2147 output_operand_lossage ("invalid operand to %%H/%%L code");
2154 if (GET_CODE (x
) != CONST_DOUBLE
2155 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2156 fatal_insn ("bad insn for 'A'", x
);
2158 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2159 fprintf (file
, "%s", str
);
2163 case 'B' : /* Bottom half. */
2164 case 'T' : /* Top half. */
2165 /* Output the argument to a `seth' insn (sets the Top half-word).
2166 For constants output arguments to a seth/or3 pair to set Top and
2167 Bottom halves. For symbols output arguments to a seth/add3 pair to
2168 set Top and Bottom halves. The difference exists because for
2169 constants seth/or3 is more readable but for symbols we need to use
2170 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2171 switch (GET_CODE (x
))
2178 split_double (x
, &first
, &second
);
2179 x
= WORDS_BIG_ENDIAN
? second
: first
;
2180 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2182 ? INTVAL (x
) & 0xffff
2183 : (INTVAL (x
) >> 16) & 0xffff));
2189 && small_data_operand (x
, VOIDmode
))
2191 fputs ("sda(", file
);
2192 output_addr_const (file
, x
);
2198 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2199 output_addr_const (file
, x
);
2203 output_operand_lossage ("invalid operand to %%T/%%B code");
2210 /* Output a load/store with update indicator if appropriate. */
2213 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2214 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2218 output_operand_lossage ("invalid operand to %%U code");
2222 /* Print a constant value negated. */
2223 if (CONST_INT_P (x
))
2224 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2226 output_operand_lossage ("invalid operand to %%N code");
2230 /* Print a const_int in hex. Used in comments. */
2231 if (CONST_INT_P (x
))
2232 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2236 fputs (IMMEDIATE_PREFIX
, file
);
2240 /* Do nothing special. */
2245 output_operand_lossage ("invalid operand output code");
2248 switch (GET_CODE (x
))
2251 fputs (reg_names
[REGNO (x
)], file
);
2256 if (GET_CODE (addr
) == PRE_INC
)
2258 if (!REG_P (XEXP (addr
, 0)))
2259 fatal_insn ("pre-increment address is not a register", x
);
2261 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2263 else if (GET_CODE (addr
) == PRE_DEC
)
2265 if (!REG_P (XEXP (addr
, 0)))
2266 fatal_insn ("pre-decrement address is not a register", x
);
2268 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2270 else if (GET_CODE (addr
) == POST_INC
)
2272 if (!REG_P (XEXP (addr
, 0)))
2273 fatal_insn ("post-increment address is not a register", x
);
2275 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2280 output_address (GET_MODE (x
), addr
);
2286 /* We handle SFmode constants here as output_addr_const doesn't. */
2287 if (GET_MODE (x
) == SFmode
)
2291 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2292 fprintf (file
, "0x%08lx", l
);
2297 /* Let output_addr_const deal with it. */
2300 output_addr_const (file
, x
);
2305 /* Print a memory address as an operand to reference that memory location. */
2308 m32r_print_operand_address (FILE * file
, machine_mode
/*mode*/, rtx addr
)
2314 switch (GET_CODE (addr
))
2317 fputs (reg_names
[REGNO (addr
)], file
);
2321 if (CONST_INT_P (XEXP (addr
, 0)))
2322 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2323 else if (CONST_INT_P (XEXP (addr
, 1)))
2324 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2326 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2329 /* Print the offset first (if present) to conform to the manual. */
2333 fprintf (file
, "%d,", offset
);
2334 fputs (reg_names
[REGNO (base
)], file
);
2336 /* The chip doesn't support this, but left in for generality. */
2337 else if (REG_P (index
))
2338 fprintf (file
, "%s,%s",
2339 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2340 /* Not sure this can happen, but leave in for now. */
2341 else if (GET_CODE (index
) == SYMBOL_REF
)
2343 output_addr_const (file
, index
);
2345 fputs (reg_names
[REGNO (base
)], file
);
2348 fatal_insn ("bad address", addr
);
2350 else if (GET_CODE (base
) == LO_SUM
)
2352 gcc_assert (!index
&& REG_P (XEXP (base
, 0)));
2353 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2354 fputs ("sda(", file
);
2356 fputs ("low(", file
);
2357 output_addr_const (file
, plus_constant (Pmode
, XEXP (base
, 1),
2360 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2363 fatal_insn ("bad address", addr
);
2367 if (!REG_P (XEXP (addr
, 0)))
2368 fatal_insn ("lo_sum not of register", addr
);
2369 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2370 fputs ("sda(", file
);
2372 fputs ("low(", file
);
2373 output_addr_const (file
, XEXP (addr
, 1));
2375 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2378 case PRE_INC
: /* Assume SImode. */
2379 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2382 case PRE_DEC
: /* Assume SImode. */
2383 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2386 case POST_INC
: /* Assume SImode. */
2387 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2391 output_addr_const (file
, addr
);
2397 m32r_print_operand_punct_valid_p (unsigned char code
)
2399 return m32r_punct_chars
[code
];
2402 /* Return true if the operands are the constants 0 and 1. */
2405 zero_and_one (rtx operand1
, rtx operand2
)
2408 CONST_INT_P (operand1
)
2409 && CONST_INT_P (operand2
)
2410 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2411 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2414 /* Generate the correct assembler code to handle the conditional loading of a
2415 value into a register. It is known that the operands satisfy the
2416 conditional_move_operand() function above. The destination is operand[0].
2417 The condition is operand [1]. The 'true' value is operand [2] and the
2418 'false' value is operand [3]. */
2421 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2423 static char buffer
[100];
2424 const char * dest
= reg_names
[REGNO (operands
[0])];
2428 /* Destination must be a register. */
2429 gcc_assert (REG_P (operands
[0]));
2430 gcc_assert (conditional_move_operand (operands
[2], SImode
));
2431 gcc_assert (conditional_move_operand (operands
[3], SImode
));
2433 /* Check to see if the test is reversed. */
2434 if (GET_CODE (operands
[1]) == NE
)
2436 rtx tmp
= operands
[2];
2437 operands
[2] = operands
[3];
2441 sprintf (buffer
, "mvfc %s, cbr", dest
);
2443 /* If the true value was '0' then we need to invert the results of the move. */
2444 if (INTVAL (operands
[2]) == 0)
2445 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2451 /* Returns true if the registers contained in the two
2452 rtl expressions are different. */
2455 m32r_not_same_reg (rtx a
, rtx b
)
2460 while (GET_CODE (a
) == SUBREG
)
2466 while (GET_CODE (b
) == SUBREG
)
2472 return reg_a
!= reg_b
;
2477 m32r_function_symbol (const char *name
)
2479 int extra_flags
= 0;
2480 enum m32r_model model
;
2481 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2483 if (TARGET_MODEL_SMALL
)
2484 model
= M32R_MODEL_SMALL
;
2485 else if (TARGET_MODEL_MEDIUM
)
2486 model
= M32R_MODEL_MEDIUM
;
2487 else if (TARGET_MODEL_LARGE
)
2488 model
= M32R_MODEL_LARGE
;
2490 gcc_unreachable (); /* Shouldn't happen. */
2491 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2494 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2499 /* Use a library function to move some bytes. */
2502 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2504 /* We want to pass the size as Pmode, which will normally be SImode
2505 but will be DImode if we are using 64-bit longs and pointers. */
2506 if (GET_MODE (bytes_rtx
) != VOIDmode
2507 && GET_MODE (bytes_rtx
) != Pmode
)
2508 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2510 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL
,
2511 VOIDmode
, dest_reg
, Pmode
, src_reg
, Pmode
,
2512 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2513 TYPE_UNSIGNED (sizetype
)),
2514 TYPE_MODE (sizetype
));
2517 /* Expand string/block move operations.
2519 operands[0] is the pointer to the destination.
2520 operands[1] is the pointer to the source.
2521 operands[2] is the number of bytes to move.
2522 operands[3] is the alignment.
2524 Returns 1 upon success, 0 otherwise. */
2527 m32r_expand_block_move (rtx operands
[])
2529 rtx orig_dst
= operands
[0];
2530 rtx orig_src
= operands
[1];
2531 rtx bytes_rtx
= operands
[2];
2532 rtx align_rtx
= operands
[3];
2533 int constp
= CONST_INT_P (bytes_rtx
);
2534 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2535 int align
= INTVAL (align_rtx
);
2540 if (constp
&& bytes
<= 0)
2543 /* Move the address into scratch registers. */
2544 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2545 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2547 if (align
> UNITS_PER_WORD
)
2548 align
= UNITS_PER_WORD
;
2550 /* If we prefer size over speed, always use a function call.
2551 If we do not know the size, use a function call.
2552 If the blocks are not word aligned, use a function call. */
2553 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2555 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2559 leftover
= bytes
% MAX_MOVE_BYTES
;
2562 /* If necessary, generate a loop to handle the bulk of the copy. */
2565 rtx_code_label
*label
= NULL
;
2566 rtx final_src
= NULL_RTX
;
2567 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2568 rtx rounded_total
= GEN_INT (bytes
);
2569 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2570 rtx new_src_reg
= gen_reg_rtx (SImode
);
2572 /* If we are going to have to perform this loop more than
2573 once, then generate a label and compute the address the
2574 source register will contain upon completion of the final
2576 if (bytes
> MAX_MOVE_BYTES
)
2578 final_src
= gen_reg_rtx (Pmode
);
2581 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2584 emit_insn (gen_movsi (final_src
, rounded_total
));
2585 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2588 label
= gen_label_rtx ();
2592 /* It is known that output_block_move() will update src_reg to point
2593 to the word after the end of the source block, and dst_reg to point
2594 to the last word of the destination block, provided that the block
2595 is MAX_MOVE_BYTES long. */
2596 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2597 new_dst_reg
, new_src_reg
));
2598 emit_move_insn (dst_reg
, new_dst_reg
);
2599 emit_move_insn (src_reg
, new_src_reg
);
2600 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2602 if (bytes
> MAX_MOVE_BYTES
)
2604 rtx test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2605 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2610 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2611 gen_reg_rtx (SImode
),
2612 gen_reg_rtx (SImode
)));
2617 /* Emit load/stores for a small constant word aligned block_move.
2619 operands[0] is the memory address of the destination.
2620 operands[1] is the memory address of the source.
2621 operands[2] is the number of bytes to move.
2622 operands[3] is a temp register.
2623 operands[4] is a temp register. */
2626 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2628 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2632 gcc_assert (bytes
>= 1 && bytes
<= MAX_MOVE_BYTES
);
2634 /* We do not have a post-increment store available, so the first set of
2635 stores are done without any increment, then the remaining ones can use
2636 the pre-increment addressing mode.
2638 Note: expand_block_move() also relies upon this behavior when building
2639 loops to copy large blocks. */
2648 output_asm_insn ("ld\t%5, %p1", operands
);
2649 output_asm_insn ("ld\t%6, %p1", operands
);
2650 output_asm_insn ("st\t%5, @%0", operands
);
2651 output_asm_insn ("st\t%6, %s0", operands
);
2655 output_asm_insn ("ld\t%5, %p1", operands
);
2656 output_asm_insn ("ld\t%6, %p1", operands
);
2657 output_asm_insn ("st\t%5, %s0", operands
);
2658 output_asm_insn ("st\t%6, %s0", operands
);
2663 else if (bytes
>= 4)
2668 output_asm_insn ("ld\t%5, %p1", operands
);
2671 output_asm_insn ("ld\t%6, %p1", operands
);
2674 output_asm_insn ("st\t%5, @%0", operands
);
2676 output_asm_insn ("st\t%5, %s0", operands
);
2682 /* Get the entire next word, even though we do not want all of it.
2683 The saves us from doing several smaller loads, and we assume that
2684 we cannot cause a page fault when at least part of the word is in
2685 valid memory [since we don't get called if things aren't properly
2687 int dst_offset
= first_time
? 0 : 4;
2688 /* The amount of increment we have to make to the
2689 destination pointer. */
2690 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2691 /* The same for the source pointer. */
2692 int src_inc_amount
= bytes
;
2696 /* If got_extra is true then we have already loaded
2697 the next word as part of loading and storing the previous word. */
2699 output_asm_insn ("ld\t%6, @%1", operands
);
2705 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2706 my_operands
[0] = operands
[5];
2707 my_operands
[1] = GEN_INT (dst_offset
);
2708 my_operands
[2] = operands
[0];
2709 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2711 /* If there is a byte left to store then increment the
2712 destination address and shift the contents of the source
2713 register down by 8 bits. We could not do the address
2714 increment in the store half word instruction, because it does
2715 not have an auto increment mode. */
2716 if (bytes
> 0) /* assert (bytes == 1) */
2727 my_operands
[0] = operands
[6];
2728 my_operands
[1] = GEN_INT (last_shift
);
2729 output_asm_insn ("srai\t%0, #%1", my_operands
);
2730 my_operands
[0] = operands
[6];
2731 my_operands
[1] = GEN_INT (dst_offset
);
2732 my_operands
[2] = operands
[0];
2733 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2736 /* Update the destination pointer if needed. We have to do
2737 this so that the patterns matches what we output in this
2740 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2742 my_operands
[0] = operands
[0];
2743 my_operands
[1] = GEN_INT (dst_inc_amount
);
2744 output_asm_insn ("addi\t%0, #%1", my_operands
);
2747 /* Update the source pointer if needed. We have to do this
2748 so that the patterns matches what we output in this
2751 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2753 my_operands
[0] = operands
[1];
2754 my_operands
[1] = GEN_INT (src_inc_amount
);
2755 output_asm_insn ("addi\t%0, #%1", my_operands
);
2765 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2768 m32r_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2770 return (m32r_hard_regno_modes
[regno
] & m32r_mode_class
[mode
]) != 0;
2773 /* Implement TARGET_MODES_TIEABLE_P. Tie QI/HI/SI modes together. */
2776 m32r_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2778 return (GET_MODE_CLASS (mode1
) == MODE_INT
2779 && GET_MODE_CLASS (mode2
) == MODE_INT
2780 && GET_MODE_SIZE (mode1
) <= UNITS_PER_WORD
2781 && GET_MODE_SIZE (mode2
) <= UNITS_PER_WORD
);
2784 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2787 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2788 unsigned int new_reg
)
2790 /* Interrupt routines can't clobber any register that isn't already used. */
2791 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2792 && !df_regs_ever_live_p (new_reg
))
2799 m32r_return_addr (int count
)
2804 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
2808 m32r_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2810 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
2811 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2812 0x017e8e17 : 0x178e7e01, SImode
));
2813 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
2814 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2815 0x0c00ae86 : 0x86ae000c, SImode
));
2816 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
2817 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2818 0xe627871e : 0x1e8727e6, SImode
));
2819 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
2820 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2821 0xc616c626 : 0x26c61fc6, SImode
));
2822 emit_move_insn (adjust_address (m_tramp
, SImode
, 16),
2824 emit_move_insn (adjust_address (m_tramp
, SImode
, 20),
2825 XEXP (DECL_RTL (fndecl
), 0));
2827 if (m32r_cache_flush_trap
>= 0)
2828 emit_insn (gen_flush_icache
2829 (validize_mem (adjust_address (m_tramp
, SImode
, 0)),
2830 gen_int_mode (m32r_cache_flush_trap
, SImode
)));
2831 else if (m32r_cache_flush_func
&& m32r_cache_flush_func
[0])
2832 emit_library_call (m32r_function_symbol (m32r_cache_flush_func
),
2833 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
,
2834 gen_int_mode (TRAMPOLINE_SIZE
, SImode
), SImode
,
2835 GEN_INT (3), SImode
);
2838 /* True if X is a reg that can be used as a base reg. */
2841 m32r_rtx_ok_for_base_p (const_rtx x
, bool strict
)
2848 if (GPR_P (REGNO (x
)))
2853 if (GPR_P (REGNO (x
))
2854 || REGNO (x
) == ARG_POINTER_REGNUM
2855 || ! HARD_REGISTER_P (x
))
2863 m32r_rtx_ok_for_offset_p (const_rtx x
)
2865 return (CONST_INT_P (x
) && INT16_P (INTVAL (x
)));
2869 m32r_legitimate_offset_addres_p (machine_mode mode ATTRIBUTE_UNUSED
,
2870 const_rtx x
, bool strict
)
2872 if (GET_CODE (x
) == PLUS
2873 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2874 && m32r_rtx_ok_for_offset_p (XEXP (x
, 1)))
2880 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2881 since more than one instruction will be required. */
2884 m32r_legitimate_lo_sum_addres_p (machine_mode mode
, const_rtx x
,
2887 if (GET_CODE (x
) == LO_SUM
2888 && (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2889 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2890 && CONSTANT_P (XEXP (x
, 1)))
2896 /* Is this a load and increment operation. */
2899 m32r_load_postinc_p (machine_mode mode
, const_rtx x
, bool strict
)
2901 if ((mode
== SImode
|| mode
== SFmode
)
2902 && GET_CODE (x
) == POST_INC
2903 && REG_P (XEXP (x
, 0))
2904 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2910 /* Is this an increment/decrement and store operation. */
2913 m32r_store_preinc_predec_p (machine_mode mode
, const_rtx x
, bool strict
)
2915 if ((mode
== SImode
|| mode
== SFmode
)
2916 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
2917 && REG_P (XEXP (x
, 0)) \
2918 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2924 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2927 m32r_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
2929 if (m32r_rtx_ok_for_base_p (x
, strict
)
2930 || m32r_legitimate_offset_addres_p (mode
, x
, strict
)
2931 || m32r_legitimate_lo_sum_addres_p (mode
, x
, strict
)
2932 || m32r_load_postinc_p (mode
, x
, strict
)
2933 || m32r_store_preinc_predec_p (mode
, x
, strict
))
2940 m32r_conditional_register_usage (void)
2944 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2945 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2949 /* Implement TARGET_LEGITIMATE_CONSTANT_P
2951 We don't allow (plus symbol large-constant) as the relocations can't
2952 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2953 We allow all CONST_DOUBLE's as the md file patterns will force the
2954 constant to memory if they can't handle them. */
2957 m32r_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2959 return !(GET_CODE (x
) == CONST
2960 && GET_CODE (XEXP (x
, 0)) == PLUS
2961 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2962 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
2963 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
2964 && UINTVAL (XEXP (XEXP (x
, 0), 1)) > 32767);
2967 /* Implement TARGET_STARTING_FRAME_OFFSET. The frame pointer points at
2968 the same place as the stack pointer, except if alloca has been called. */
2970 static HOST_WIDE_INT
2971 m32r_starting_frame_offset (void)
2973 return M32R_STACK_ALIGN (crtl
->outgoing_args_size
);