From 9df010725faff9c0bf4dccd3bc45f871293d5d64 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Tue, 24 Aug 2010 14:08:16 -0700 Subject: [PATCH] Optimize mov r64,imm Handle immediate-size optimization for "mov r64,imm" -- reduce it to "mov r32,imm32" or "mov r64,imm32" as appropriate. Signed-off-by: H. Peter Anvin --- insns.dat | 2 ++ insns.pl | 2 +- nasm.h | 2 +- opflags.h | 15 ++++++++------- parser.c | 9 ++++++++- test/imm64.asm | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 70 insertions(+), 10 deletions(-) diff --git a/insns.dat b/insns.dat index 79cc2a76..54a87ef0 100644 --- a/insns.dat +++ b/insns.dat @@ -813,6 +813,8 @@ MOV reg64,reg64 \324\1\x8B\110 X64 MOV reg8,imm \10\xB0\21 8086,SM MOV reg16,imm \320\10\xB8\31 8086,SM MOV reg32,imm \321\10\xB8\41 386,SM +MOV reg64,udword64 \323\10\xB8\41 X64,SM,OPT,ND +MOV reg64,sdword64 \324\1\xC7\200\255 X64,SM,OPT,ND MOV reg64,imm \324\10\xB8\55 X64,SM MOV rm8,imm \1\xC6\200\21 8086,SM MOV rm16,imm \320\1\xC7\200\31 8086,SM diff --git a/insns.pl b/insns.pl index 5ffdce2f..d43f05a1 100755 --- a/insns.pl +++ b/insns.pl @@ -442,7 +442,7 @@ sub format_insn($$$$$) { if ($opp =~ /^(.*[^\d])(8|16|32|64|80|128|256)$/) { my $ox = $1; my $on = $2; - if ($ox !~ /^sbyte$/) { + if ($ox !~ /^(sbyte|sdword|udword)$/) { $opp = $ox; push(@oppx, "bits$on"); } diff --git a/nasm.h b/nasm.h index f78ed0fc..069584bd 100644 --- a/nasm.h +++ b/nasm.h @@ -1,6 +1,6 @@ /* ----------------------------------------------------------------------- * * - * Copyright 1996-2009 The NASM Authors - All Rights Reserved + * Copyright 1996-2010 The NASM Authors - All Rights Reserved * See the file AUTHORS included with the NASM distribution for * the specific copyright holders. * diff --git a/opflags.h b/opflags.h index b4912445..c2b72b03 100644 --- a/opflags.h +++ b/opflags.h @@ -66,11 +66,10 @@ * 23: 256 bits (YWORD) * 29: 128 bits (OWORD) * - * Bits 8-11 modifiers + * Bits 8-10 modifiers * 8: TO * 9: COLON * 10: STRICT - * 11: (reserved) * * Bits 12-15: type of operand * 12: REGISTER @@ -78,7 +77,7 @@ * 14: MEMORY (always has REGMEM attribute as well) * 15: REGMEM (valid EA operand) * - * Bits 16-19, 28: subclasses + * Bits 11, 16-19, 28: subclasses * With REG_CDT: * 16: REG_CREG (CRx) * 17: REG_DREG (DRx) @@ -115,6 +114,8 @@ * 17: BYTENESS16 (-128..127) * 18: BYTENESS32 (-128..127) * 19: BYTENESS64 (-128..127) + * 28: SDWORD64 (-2^31..2^31-1) + * 11: UDWORD64 (0..2^32-1) * * Bits 20-22, 24-27: register classes * 20: REG_CDT (CRx, DRx, TRx) @@ -125,8 +126,6 @@ * 26: RM_XMM (XMMREG) * 27: RM_YMM (YMMREG) * - * Bit 31 is currently unallocated. - * * 30: SAME_AS * Special flag only used in instruction patterns; means this operand * has to be identical to another operand. Currently only supported @@ -151,7 +150,7 @@ typedef uint32_t opflags_t; #define SIZE_MASK 0x208000FFU /* all the size attributes */ /* Modifiers */ -#define MODIFIER_MASK 0x00000f00U +#define MODIFIER_MASK 0x00000700U #define TO 0x00000100U /* reverse effect in FADD, FSUB &c */ #define COLON 0x00000200U /* operand is followed by a colon */ #define STRICT 0x00000400U /* do not optimize this operand */ @@ -197,7 +196,7 @@ typedef uint32_t opflags_t; #define REG_EIP 0x00801004U /* EIP relative addressing */ /* Special GPRs */ -#define REG_SMASK 0x100f0000U /* a mask for the following */ +#define REG_SMASK 0x100f0800U /* a mask for the following */ #define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */ #define REG_AL 0x00219001U #define REG_AX 0x00219002U @@ -232,6 +231,8 @@ typedef uint32_t opflags_t; #define SBYTE32 0x00042000U /* for op r32,immediate instrs. */ #define SBYTE64 0x00082000U /* for op r64,immediate instrs. */ #define BYTENESS 0x000e0000U /* for testing for byteness */ +#define SDWORD64 0x10002000U /* for op r64,simm32 instrs. */ +#define UDWORD64 0x00002800U /* for op r64,uimm32 instrs. */ /* special flags */ #define SAME_AS 0x40000000U diff --git a/parser.c b/parser.c index ea36e86c..75bd344d 100644 --- a/parser.c +++ b/parser.c @@ -843,7 +843,8 @@ is_expression: if(optimizing >= 0 && !(result->oprs[operand].type & STRICT)) { /* Be optimistic */ - result->oprs[operand].type |= SBYTE16 | SBYTE32 | SBYTE64; + result->oprs[operand].type |= + SBYTE16 | SBYTE32 | SBYTE64 | UDWORD64 | SDWORD64; } } else if (is_reloc(value)) { /* it's immediate */ result->oprs[operand].type |= IMMEDIATE; @@ -865,6 +866,12 @@ is_expression: result->oprs[operand].type |= SBYTE32; if (v16 >= -128 && v16 <= 127) result->oprs[operand].type |= SBYTE16; + if ((uint64_t)v64 <= UINT64_C(0xffffffff)) + result->oprs[operand].type |= UDWORD64; + if (v64 >= -INT64_C(2147483648) && + v64 <= INT64_C(2147483647)) + result->oprs[operand].type |= SDWORD64; + } } } else { /* it's a register */ diff --git a/test/imm64.asm b/test/imm64.asm index d90a0642..a1140443 100644 --- a/test/imm64.asm +++ b/test/imm64.asm @@ -9,3 +9,53 @@ mov [rax],dword 11223344h ; 32-bit operation mov qword [rax],11223344h mov qword [rax],dword 11223344h + + mov rax,0_ffffffff_8899aabbh + mov rax,dword 0_ffffffff_8899aabbh + mov eax,0_ffffffff_8899aabbh + mov [rax],dword 0_ffffffff_8899aabbh ; 32-bit operation + mov qword [rax],0_ffffffff_8899aabbh + mov qword [rax],dword 0_ffffffff_8899aabbh + + mov rax,7fffffffh + mov rax,80000000h + mov rax,0_ffffffffh + mov rax,1_00000000h + mov rax,0_ffffffff_7fffffffh + mov rax,0_ffffffff_80000000h + + mov rax,0_11223344_8899aabbh + mov rax,dword 0_11223344_8899aabbh + mov eax,0_11223344_8899aabbh + mov [rax],dword 0_11223344_8899aabbh ; 32-bit operation + mov qword [rax],0_11223344_8899aabbh + mov qword [rax],dword 0_11223344_8899aabbh + + mov rax,strict 11223344h + mov rax,strict dword 11223344h + mov eax,strict 11223344h + mov [rax],strict dword 11223344h ; 32-bit operation + mov qword [rax],strict 11223344h + mov qword [rax],strict dword 11223344h + + mov rax,strict 0_ffffffff_8899aabbh + mov rax,strict dword 0_ffffffff_8899aabbh + mov eax,strict 0_ffffffff_8899aabbh + mov [rax],strict dword 0_ffffffff_8899aabbh ; 32-bit operation + mov qword [rax],strict 0_ffffffff_8899aabbh + mov qword [rax],strict dword 0_ffffffff_8899aabbh + + mov rax,strict 7fffffffh + mov rax,strict 80000000h + mov rax,strict 0_ffffffffh + mov rax,strict 1_00000000h + mov rax,strict 0_ffffffff_7fffffffh + mov rax,strict 0_ffffffff_80000000h + + mov rax,strict 0_11223344_8899aabbh + mov rax,strict dword 0_11223344_8899aabbh + mov eax,strict 0_11223344_8899aabbh + mov [rax],strict dword 0_11223344_8899aabbh ; 32-bit operation + mov qword [rax],strict 0_11223344_8899aabbh + mov qword [rax],strict dword 0_11223344_8899aabbh + -- 2.11.4.GIT