| commit | 637b9cc58196b61656e8ab7855d4d6fcb87a2840 | |
| author | H. Peter Anvin <hpa@linux.intel.com> | |
| Tue, 20 Sep 2016 23:39:46 +0000 (20 16:39 -0700) | ||
| committer | H. Peter Anvin <hpa@linux.intel.com> | |
| Tue, 20 Sep 2016 23:48:17 +0000 (20 16:48 -0700) | ||
| tree | fdac9fc1042fca919e0f5d6c4e33e0e4658b26f2 | treesnapshot (tar.gz zip) |
| parent | a77692b34dea97b4681b102ac9c94f5b1b2f000f | commitdiff |
Correct /is4 encoding for EVEX instructions
For EVEX instructions, /is4 can contain a fifth register bit, encoded
in bit 3 of the imm8. Properly generate this case, and simplifiy the
/is4 generation code somewhat.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cherry picked and ported from nasm-2.12.xx commit
976ba730622ae7c2d5e88d4fb4477ff96c1cd3f4.
Resolved Conflicts:
asm/assemble.c
For EVEX instructions, /is4 can contain a fifth register bit, encoded
in bit 3 of the imm8. Properly generate this case, and simplifiy the
/is4 generation code somewhat.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cherry picked and ported from nasm-2.12.xx commit
976ba730622ae7c2d5e88d4fb4477ff96c1cd3f4.
Resolved Conflicts:
asm/assemble.c
| asm/assemble.c | diffblobblamehistory |