x86/i386: Make sure stack-protector segment base is cache aligned
commit1ea0d14e480c245683927eecc03a70faf06e80c8
authorJeremy Fitzhardinge <jeremy@goop.org>
Thu, 3 Sep 2009 19:27:15 +0000 (3 12:27 -0700)
committerIngo Molnar <mingo@elte.hu>
Thu, 3 Sep 2009 19:30:51 +0000 (3 21:30 +0200)
treecc43a6966799aa55c0f076c1217c557fb107563c
parent23386d63bbb3199cf247313ec088878d72debcfd
x86/i386: Make sure stack-protector segment base is cache aligned

The Intel Optimization Reference Guide says:

In Intel Atom microarchitecture, the address generation unit
assumes that the segment base will be 0 by default. Non-zero
segment base will cause load and store operations to experience
a delay.
- If the segment base isn't aligned to a cache line
  boundary, the max throughput of memory operations is
  reduced to one [e]very 9 cycles.
[...]
Assembly/Compiler Coding Rule 15. (H impact, ML generality)
For Intel Atom processors, use segments with base set to 0
whenever possible; avoid non-zero segment base address that is
not aligned to cache line boundary at all cost.

We can't avoid having a non-zero base for the stack-protector
segment, but we can make it cache-aligned.

Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Cc: <stable@kernel.org>
LKML-Reference: <4AA01893.6000507@goop.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/include/asm/processor.h
arch/x86/include/asm/stackprotector.h
arch/x86/include/asm/system.h
arch/x86/kernel/cpu/common.c
arch/x86/kernel/head_32.S