| commit | fd4d1165bc59b4cb35a3d30e43ebba442c67a68c | |
| author | Mark Brown <broonie@opensource.wolfsonmicro.com> | |
| Sat, 10 Dec 2011 12:38:32 +0000 (10 20:38 +0800) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Fri, 6 Jan 2012 22:16:55 +0000 (6 14:16 -0800) | ||
| tree | 885296d35492beb1bca12f862d6dc0151f6027dc | treesnapshot (tar.gz zip) |
| parent | c5bebbd132f1d56ef3d99143f5386d58b4da318e | commitdiff |
ASoC: Fix WM8996 24.576MHz clock operation
commit 37d5993c5cc9bc83762ae1b5bd287438022e8afe upstream.
Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit 37d5993c5cc9bc83762ae1b5bd287438022e8afe upstream.
Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| sound/soc/codecs/wm8996.c | diffblobblamehistory |