| commit | be70b4e2c60c2d7e03c3193cadd1cb9eddb5e4bc | |
| author | Francois Romieu <romieu@fr.zoreil.com> | |
| Thu, 3 Feb 2011 11:02:36 +0000 (3 12:02 +0100) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Mon, 14 Mar 2011 21:17:38 +0000 (14 14:17 -0700) | ||
| tree | 941b4d807e280c34ab545583c4ff7c72de2ec7a9 | treesnapshot (tar.gz zip) |
| parent | cb1f3fd3ba182cd514e2b72487a5f84932e6a03b | commitdiff |
r8169: RxFIFO overflow oddities with 8168 chipsets.
commit 1519e57fe81c14bb8fa4855579f19264d1ef63b4 upstream.
Some experiment-based action to prevent my 8168 chipsets locking-up hard
in the irq handler under load (pktgen ~1Mpps). Apparently a reset is not
always mandatory (is it at all ?).
- RTL_GIGA_MAC_VER_12
- RTL_GIGA_MAC_VER_25
Missed ~55% packets. Note:
- this is an old SiS 965L motherboard
- the 8168 chipset emits (lots of) control frames towards the sender
- RTL_GIGA_MAC_VER_26
The chipset does not go into a frenzy of mac control pause when it
crashes yet but it can still be crashed. It needs more work.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Cc: Ivan Vecera <ivecera@redhat.com>
Cc: Hayes <hayeswang@realtek.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit 1519e57fe81c14bb8fa4855579f19264d1ef63b4 upstream.
Some experiment-based action to prevent my 8168 chipsets locking-up hard
in the irq handler under load (pktgen ~1Mpps). Apparently a reset is not
always mandatory (is it at all ?).
- RTL_GIGA_MAC_VER_12
- RTL_GIGA_MAC_VER_25
Missed ~55% packets. Note:
- this is an old SiS 965L motherboard
- the 8168 chipset emits (lots of) control frames towards the sender
- RTL_GIGA_MAC_VER_26
The chipset does not go into a frenzy of mac control pause when it
crashes yet but it can still be crashed. It needs more work.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Cc: Ivan Vecera <ivecera@redhat.com>
Cc: Hayes <hayeswang@realtek.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| drivers/net/r8169.c | diffblobblamehistory |