| commit | a7ef0640d984e265393a76aa08a09febd3e7ce34 | |
| author | Eric Anholt <eric@anholt.net> | |
| Tue, 29 Mar 2011 23:59:54 +0000 (29 16:59 -0700) | ||
| committer | Keith Packard <keithp@keithp.com> | |
| Fri, 10 Jun 2011 04:51:20 +0000 (9 21:51 -0700) | ||
| tree | 47fc1704f12debd5fad55bbc785f8b8876e47884 | treesnapshot (tar.gz zip) |
| parent | 2da3b9b940e2a18147422c54ed8b29d01e1ade88 | commitdiff |
drm/i915: Use the uncached domain for the display planes
The simplest and common method for ensuring scanout coherency on all
chipsets is to mark the scanout buffers as uncached (and for
userspace to remember to flush the render cache every so often).
We can improve upon this for later generations by marking scanout
objects as GFDT and only flush those cachelines when required. However,
we start simple.
[v2: Move the set to uncached above the clflush. Otherwise, we'd skip
the clflush and try to scan out data that was still sitting in the
cache.]
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
The simplest and common method for ensuring scanout coherency on all
chipsets is to mark the scanout buffers as uncached (and for
userspace to remember to flush the render cache every so often).
We can improve upon this for later generations by marking scanout
objects as GFDT and only flush those cachelines when required. However,
we start simple.
[v2: Move the set to uncached above the clflush. Otherwise, we'd skip
the clflush and try to scan out data that was still sitting in the
cache.]
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| drivers/gpu/drm/i915/i915_gem.c | diffblobblamehistory |