| commit | 7cc8583372a21d98a23b703ad96cab03180b5030 | |
| author | David S. Miller <davem@davemloft.net> | |
| Thu, 22 Dec 2011 21:23:59 +0000 (22 13:23 -0800) | ||
| committer | David S. Miller <davem@davemloft.net> | |
| Thu, 22 Dec 2011 21:46:53 +0000 (22 13:46 -0800) | ||
| tree | 15c342c336b72e431ce96f1b4d27930b9f58ebe2 | treesnapshot (tar.gz zip) |
| parent | b3b1b70e62a603f473619dbebc3b3d23f535e6f8 | commitdiff |
sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq().
This silently was working for many years and stopped working on
Niagara-T3 machines.
We need to set the MSIQ to VALID before we can set it's state to IDLE.
On Niagara-T3, setting the state to IDLE first was causing HV_EINVAL
errors. The hypervisor documentation says, rather ambiguously, that
the MSIQ must be "initialized" before one can set the state.
I previously understood this to mean merely that a successful setconf()
operation has been performed on the MSIQ, which we have done at this
point. But it seems to also mean that it has been set VALID too.
Signed-off-by: David S. Miller <davem@davemloft.net>
This silently was working for many years and stopped working on
Niagara-T3 machines.
We need to set the MSIQ to VALID before we can set it's state to IDLE.
On Niagara-T3, setting the state to IDLE first was causing HV_EINVAL
errors. The hypervisor documentation says, rather ambiguously, that
the MSIQ must be "initialized" before one can set the state.
I previously understood this to mean merely that a successful setconf()
operation has been performed on the MSIQ, which we have done at this
point. But it seems to also mean that it has been set VALID too.
Signed-off-by: David S. Miller <davem@davemloft.net>
| arch/sparc/kernel/pci_sun4v.c | diffblobblamehistory |