drivers/usb/net/Zydas/zd1205.h

   1 #ifndef _ZD1205_H_
   2 #define _ZD1205_H_
   3
   4 #include <linux/module.h>
   5 #include <linux/types.h>
   6 #include <linux/init.h>
   7 #include <linux/mm.h>
   8 #include <linux/errno.h>
   9 #include <linux/ioport.h>
  10 #include <linux/pci.h>
  11
  12 #ifdef HOST_IF_USB
  13         #include <linux/usb.h>
  14 #endif
  15
  16 #include <linux/kernel.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/skbuff.h>
  20 #include <linux/delay.h>
  21 #include <linux/timer.h>
  22 #include <linux/slab.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/version.h>
  25 #include <linux/string.h>
  26 #include <linux/wait.h>
  27 #include <linux/reboot.h>
  28 #include <asm/io.h>
  29 #include <asm/unaligned.h>
  30 #include <asm/processor.h>
  31 #include <linux/ethtool.h>
  32 #include <linux/inetdevice.h>
  33 #include <linux/bitops.h>
  34 #include <linux/if.h>
  35 #include <asm/uaccess.h>
  36 #include <linux/proc_fs.h>
  37 #include <linux/ip.h>
  38 #include <linux/wireless.h>
  39 #include <linux/if_arp.h>
  40 #include <linux/unistd.h>
  41 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
  42         #include <linux/workqueue.h>
  43 #endif
  44
  45 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
  46     #include <asm/div64.h>
  47 #endif
  48
  49 #include "zdcompat.h"
  50 #include "zdequates.h"
  51 #include "zdapi.h"
  52 #include "zydas_common.h"
  53
  54 #ifdef HOST_IF_USB
  55 #define fANT_DIVERSITY          0
  56 #define fTX_PWR_CTRL            1
  57 #define fZD1211_LOOPBACK        1
  58 #define fDUMP_LOOPBACK_DATA     (0 && fZD1211_LOOPBACK)
  59 #define fLOAD_BOOTCODE          1
  60 #define fPROG_FLASH             (1 && fWRITE_WORD_REG)
  61 #define fPROG_FLASH_BY_FW       (1 && fPROG_FLASH)
  62 #define fDRV_WRITE_RF_REG       (1 && fWRITE_WORD_REG)
  63 #define fMERGE_RX_FRAME         (ENHANCE_RX && fDRV_WRITE_RF_REG)
  64 #define fDRV_UPDATE_EEP         (1 && fWRITE_WORD_REG)
  65 //#define fQuickPhySet                  0 //(fREAD_MUL_REG && fWRITE_WORD_REG)
  66 #endif
  67 enum zd1205_device_type {
  68         ZD_1202 = 1,
  69         ZD_1205,
  70 };
  71
  72
  73 #define ASOC_RSP                                0x10
  74 #define REASOC_RSP                              0x30
  75 #define PROBE_RSP                               0x50
  76 #define DISASOC                                 0xA0
  77 #define AUTH                                    0xB0
  78 #define DEAUTH                                  0xC0
  79 #define DATA                                    0x08
  80 #define PS_POLL                                 0xA4
  81 #define MANAGEMENT                              0x00
  82 #define PROBE_REQ                               0x40
  83 #define BEACON                                  0x80
  84 #define ACK                                     0xD4
  85 #define CONTROL                                 0x04
  86 #define NULL_FUNCTION                           0x48
  87 #define LB_DATA                                 0x88
  88
  89 #define VLAN_SIZE       4
  90 #define CHKSUM_SIZE     2
  91
  92 #define false           (0)
  93 #define true            (1)
  94
  95
  96
  97 /**************************************************************************
  98 **              Register Offset Definitions
  99 ***************************************************************************
 100 */
 101
 102 #define         ZD1205_CR0                      0x0000
 103 #define         ZD1205_CR1                      0x0004
 104 #define         ZD1205_CR2                      0x0008
 105 #define         ZD1205_CR3                      0x000C
 106 #define         ZD1205_CR5                      0x0010
 107 #define         ZD1205_CR6                      0x0014
 108 #define         ZD1205_CR7                      0x0018
 109 #define         ZD1205_CR8                      0x001C
 110 #define         ZD1205_CR4                      0x0020
 111 #define         ZD1205_CR9                      0x0024
 112 #define         ZD1205_CR10                     0x0028
 113 #define         ZD1205_CR11                     0x002C
 114 #define         ZD1205_CR12                     0x0030
 115 #define         ZD1205_CR13                     0x0034
 116 #define         ZD1205_CR14                     0x0038
 117 #define         ZD1205_CR15                     0x003C
 118 #define         ZD1205_CR16                     0x0040
 119 #define         ZD1205_CR17                     0x0044
 120 #define         ZD1205_CR18                     0x0048
 121 #define         ZD1205_CR19                     0x004C
 122 #define         ZD1205_CR20                     0x0050
 123 #define         ZD1205_CR21                     0x0054
 124 #define         ZD1205_CR22                     0x0058
 125 #define         ZD1205_CR23                     0x005C
 126
 127
 128
 129 #define         ZD1205_CR24                     0x0060
 130 #define         ZD1205_CR25                     0x0064
 131 #define         ZD1205_CR26                     0x0068
 132 #define         ZD1205_CR27                     0x006C
 133 #define         ZD1205_CR28                     0x0070
 134 #define         ZD1205_CR29                     0x0074
 135 #define         ZD1205_CR30                     0x0078
 136 #define         ZD1205_CR31                     0x007C
 137 #define         ZD1205_CR32                     0x0080
 138 #define         ZD1205_CR33                     0x0084
 139 #define         ZD1205_CR34                     0x0088
 140 #define         ZD1205_CR35                     0x008C
 141 #define         ZD1205_CR36                     0x0090
 142 #define         ZD1205_CR37                     0x0094
 143 #define         ZD1205_CR38                     0x0098
 144 #define         ZD1205_CR39                     0x009C
 145 #define         ZD1205_CR40                     0x00A0
 146 #define         ZD1205_CR41                     0x00A4
 147 #define         ZD1205_CR42                     0x00A8
 148 #define         ZD1205_CR43                     0x00AC
 149 #define         ZD1205_CR44                     0x00B0
 150 #define         ZD1205_CR45                     0x00B4
 151 #define         ZD1205_CR46                     0x00B8
 152 #define         ZD1205_CR47                     0x00BC
 153 #define         ZD1205_CR48                     0x00C0
 154 #define         ZD1205_CR49                     0x00C4
 155
 156 #define         ZD1205_CR50                     0x00C8
 157 #define         ZD1205_CR51                     0x00CC
 158 #define         ZD1205_CR52                     0x00D0
 159 #define         ZD1205_CR53                     0x00D4
 160 #define         ZD1205_CR54                     0x00D8
 161 #define         ZD1205_CR55                     0x00DC
 162 #define         ZD1205_CR56                     0x00E0
 163 #define         ZD1205_CR57                     0x00E4
 164 #define         ZD1205_CR58                     0x00E8
 165 #define         ZD1205_CR59                     0x00EC
 166 #define         ZD1205_CR60                     0x00F0
 167 #define         ZD1205_CR61                     0x00F4
 168 #define         ZD1205_CR62                     0x00F8
 169 #define         ZD1205_CR63                     0x00FC
 170 #define         ZD1205_CR64                     0x0100
 171 #define         ZD1205_CR65                     0x0104
 172 #define         ZD1205_CR66                     0x0108
 173 #define         ZD1205_CR67                     0x010C
 174 #define         ZD1205_CR68                     0x0110
 175 #define         ZD1205_CR69                     0x0114
 176 #define         ZD1205_CR70                     0x0118
 177 #define         ZD1205_CR71                     0x011C
 178 #define         ZD1205_CR72                     0x0120
 179 #define         ZD1205_CR73                     0x0124
 180 #define         ZD1205_CR74                     0x0128
 181 #define         ZD1205_CR75                     0x012C
 182 #define         ZD1205_CR76                     0x0130
 183 #define         ZD1205_CR77                     0x0134
 184 #define         ZD1205_CR78                     0x0138
 185 #define         ZD1205_CR79                     0x013C
 186 #define         ZD1205_CR80                     0x0140
 187 #define         ZD1205_CR81                     0x0144
 188 #define         ZD1205_CR82                     0x0148
 189 #define         ZD1205_CR83                     0x014C
 190 #define         ZD1205_CR84                     0x0150
 191 #define         ZD1205_CR85                     0x0154
 192 #define         ZD1205_CR86                     0x0158
 193 #define         ZD1205_CR87                     0x015C
 194 #define         ZD1205_CR88                     0x0160
 195 #define         ZD1205_CR89                     0x0164
 196
 197 #define         ZD1205_CR90                     0x0168
 198 #define         ZD1205_CR91                     0x016C
 199 #define         ZD1205_CR92                     0x0170
 200 #define         ZD1205_CR93                     0x0174
 201 #define         ZD1205_CR94                     0x0178
 202 #define         ZD1205_CR95                     0x017C
 203 #define         ZD1205_CR96                     0x0180
 204 #define         ZD1205_CR97                     0x0184
 205 #define         ZD1205_CR98                     0x0188
 206 #define         ZD1205_CR99                     0x018C
 207 #define         ZD1205_CR100                    0x0190
 208 #define         ZD1205_CR101                    0x0194
 209 #define         ZD1205_CR102                    0x0198
 210 #define         ZD1205_CR103                    0x019C
 211 #define         ZD1205_CR104                    0x01A0
 212 #define         ZD1205_CR105                    0x01A4
 213 #define         ZD1205_CR106                    0x01A8
 214 #define         ZD1205_CR107                    0x01AC
 215 #define         ZD1205_CR108                    0x01B0
 216 #define         ZD1205_CR109                    0x01B4
 217 #define         ZD1205_CR110                    0x01B8
 218 #define         ZD1205_CR111                    0x01BC
 219 #define         ZD1205_CR112                    0x01C0
 220 #define         ZD1205_CR113                    0x01C4
 221 #define         ZD1205_CR114                    0x01C8
 222 #define         ZD1205_CR115                    0x01CC
 223 #define         ZD1205_CR116                    0x01D0
 224 #define         ZD1205_CR117                    0x01D4
 225 #define         ZD1205_CR118                    0x01D8
 226 #define         ZD1205_CR119                    0x01EC
 227 #define         ZD1205_CR120                    0x01E0
 228 #define         ZD1205_CR121                    0x01E4
 229 #define         ZD1205_CR122                    0x01E8
 230 #define         ZD1205_CR123                    0x01EC
 231 #define         ZD1205_CR124                    0x01F0
 232 #define         ZD1205_CR125                    0x01F4
 233 #define         ZD1205_CR126                    0x01F8
 234 #define         ZD1205_CR127                    0x01FC
 235 #define         ZD1205_CR128                    0x0200
 236 #define         ZD1205_CR129                    0x0204
 237 #define         ZD1205_CR130                    0x0208
 238 #define         ZD1205_CR131                    0x020C
 239 #define         ZD1205_CR132                    0x0210
 240 #define         ZD1205_CR133                    0x0214
 241 #define         ZD1205_CR134                    0x0218
 242 #define         ZD1205_CR135                    0x021C
 243 #define         ZD1205_CR136                    0x0220
 244 #define         ZD1205_CR137                    0x0224
 245 #define         ZD1205_CR138                    0x0228
 246 #define         ZD1205_CR139                    0x022C
 247 #define         ZD1205_CR140                    0x0230
 248 #define         ZD1205_CR141                    0x0234
 249 #define         ZD1205_CR142                    0x0238
 250 #define         ZD1205_CR143                    0x023C
 251 #define         ZD1205_CR144                    0x0240
 252 #define         ZD1205_CR145                    0x0244
 253 #define         ZD1205_CR146                    0x0248
 254 #define         ZD1205_CR147                    0x024C
 255 #define         ZD1205_CR148                    0x0250
 256 #define         ZD1205_CR149                    0x0254
 257 #define         ZD1205_CR150                    0x0258
 258 #define         ZD1205_CR151                    0x025C
 259 #define         ZD1205_CR152                    0x0260
 260 #define         ZD1205_CR153                    0x0264
 261 #define         ZD1205_CR154                    0x0268
 262 #define         ZD1205_CR155                    0x026C
 263 #define         ZD1205_CR156                    0x0270
 264 #define         ZD1205_CR157                    0x0274
 265 #define         ZD1205_CR158                    0x0278
 266 #define         ZD1205_CR159                    0x027C
 267 #define         ZD1205_CR160                    0x0280
 268 #define         ZD1205_CR161                    0x0284
 269 #define         ZD1205_CR162                    0x0288
 270 #define         ZD1205_CR163                    0x028C
 271 #define         ZD1205_CR164                    0x0290
 272 #define         ZD1205_CR165                    0x0294
 273
 274
 275
 276 #define         ZD1205_CR166                    0x0298
 277 #define         ZD1205_CR167                    0x029C
 278 #define         ZD1205_CR168                    0x02A0
 279 #define         ZD1205_CR169                    0x02A4
 280 #define         ZD1205_CR170                    0x02A8
 281 #define         ZD1205_CR171                    0x02AC
 282 #define         ZD1205_CR172                    0x02B0
 283 #define         ZD1205_CR173                    0x02B4
 284 #define         ZD1205_CR174                    0x02B8
 285 #define         ZD1205_CR175                    0x02BC
 286 #define         ZD1205_CR176                    0x02C0
 287 #define         ZD1205_CR177                    0x02C4
 288 #define         ZD1205_CR178                    0x02C8
 289 #define         ZD1205_CR179                    0x02CC
 290 #define         ZD1205_CR180                    0x02D0
 291 #define         ZD1205_CR181                    0x02D4
 292 #define         ZD1205_CR182                    0x02D8
 293 #define         ZD1205_CR183                    0x02DC
 294 #define         ZD1205_CR184                    0x02E0
 295 #define         ZD1205_CR185                    0x02E4
 296 #define         ZD1205_CR186                    0x02E8
 297 #define         ZD1205_CR187                    0x02EC
 298 #define         ZD1205_CR188                    0x02F0
 299 #define         ZD1205_CR189                    0x02F4
 300 #define         ZD1205_CR190                    0x02F8
 301 #define         ZD1205_CR191                    0x02FC
 302 #define         ZD1205_CR192                    0x0300
 303 #define         ZD1205_CR193                    0x0304
 304 #define         ZD1205_CR194                    0x0308
 305 #define         ZD1205_CR195                    0x030C
 306 #define         ZD1205_CR196                    0x0310
 307 #define         ZD1205_CR197                    0x0314
 308 #define         ZD1205_CR198                    0x0318
 309 #define         ZD1205_CR199                    0x031C
 310 #define         ZD1205_CR200                    0x0320
 311 #define         ZD1205_CR201                    0x0324
 312 #define         ZD1205_CR202                    0x0328
 313 #define         ZD1205_CR203                    0x032C
 314 #define         ZD1205_CR204                    0x0330
 315 #define         ZD1205_CR205                    0x0334
 316 #define         ZD1205_CR206                    0x0338
 317 #define         ZD1205_CR207                    0x033C
 318 #define         ZD1205_CR208                    0x0340
 319 #define         ZD1205_CR209                    0x0344
 320 #define         ZD1205_CR210                    0x0348
 321 #define         ZD1205_CR211                    0x034C
 322 #define         ZD1205_CR212                    0x0350
 323 #define         ZD1205_CR213                    0x0354
 324 #define         ZD1205_CR214                    0x0358
 325 #define         ZD1205_CR215                    0x035C
 326 #define         ZD1205_CR216                    0x0360
 327 #define         ZD1205_CR217                    0x0364
 328 #define         ZD1205_CR218                    0x0368
 329 #define         ZD1205_CR219                    0x036C
 330 #define         ZD1205_CR220                    0x0370
 331 #define         ZD1205_CR221                    0x0374
 332
 333 #define         ZD1205_CR222                    0x0378
 334 #define         ZD1205_CR223                    0x037C
 335 #define         ZD1205_CR224                    0x0380
 336 #define         ZD1205_CR225                    0x0384
 337 #define         ZD1205_CR226                    0x0388
 338 #define         ZD1205_CR227                    0x038C
 339 #define         ZD1205_CR228                    0x0390
 340 #define         ZD1205_CR229                    0x0394
 341 #define         ZD1205_CR230                    0x0398
 342 #define         ZD1205_CR231                    0x039C
 343
 344 #define         ZD1205_CR232                    0x03A0
 345 #define         ZD1205_CR233                    0x03A4
 346 #define         ZD1205_CR234                    0x03A8
 347 #define         ZD1205_CR235                    0x03AC
 348 #define         ZD1205_CR236                    0x03B0
 349
 350 #define         ZD1205_CR240                    0x03C0
 351 #define         ZD1205_CR241                    0x03C4
 352 #define         ZD1205_CR242                    0x03C8
 353 #define         ZD1205_CR243                    0x03CC
 354 #define         ZD1205_CR244                    0x03D0
 355 #define         ZD1205_CR245                    0x03D4
 356
 357 #define         ZD1205_CR251                    0x03EC
 358 #define         ZD1205_CR252                    0x03F0
 359 #define         ZD1205_CR253                    0x03F4
 360 #define         ZD1205_CR254                    0x03F8
 361 #define         ZD1205_CR255                    0x03FC
 362
 363
 364 #define         ZD1205_PHY_END          0x03fc
 365 #define         RF_IF_CLK               0x0400
 366 #define         RF_IF_DATA              0x0404
 367 #define         PE1_PE2                 0x0408
 368 #define         PE2_DLY                 0x040C
 369 #define         LE1                     0x0410
 370 #define         LE2                     0x0414
 371 #define         GPI_EN                  0x0418
 372 #define         RADIO_PD                0x042C
 373 #define         RF2948_PD               0x042C
 374
 375 #ifndef HOST_IF_USB
 376         #define         LED1            0x0430
 377         #define         LED2            0x0434
 378 #else
 379         #define     rLED_CTRL           0x0644
 380         #define     LED2                BIT_8   // Note: this is really LED1
 381         #define     LED1                BIT_9   // Note: this is really LED2
 382 #endif
 383
 384
 385 #define         EnablePSManualAGC       0x043C  // 1: enable
 386 #define         CONFIGPhilips           0x0440
 387 #define         SA2400_SER_AP           0x0444
 388 #define         I2C_WRITE               0x0444  // Same as SA2400_SER_AP (for compatible with ZD1201)
 389 #define         SA2400_SER_RP           0x0448
 390
 391 #define         RADIO_PE                0x0458
 392 #define         RstBusMaster            0x045C
 393
 394 #define         RFCFG                   0x0464
 395
 396 #define         HSTSCHG                 0x046C
 397
 398 #define         PHY_ON                  0x0474
 399 #define         RX_DELAY                0x0478
 400 #define         RX_PE_DELAY             0x047C
 401
 402
 403 #define         GPIO_1                  0x0490
 404 #define         GPIO_2                  0x0494
 405
 406
 407 #define         EncryBufMux             0x04A8
 408
 409
 410 #define         PS_Ctrl                 0x0500
 411
 412 #define         ADDA_MBIAS_WarmTime     0x0508
 413
 414 #define         InterruptCtrl           0x0510
 415 #define         TSF_LowPart             0x0514
 416 #define         TSF_HighPart            0x0518
 417 #define         ATIMWndPeriod           0x051C
 418 #define         BCNInterval             0x0520
 419 #define         Pre_TBTT                0x0524  //In unit of TU(1024us)
 420
 421 #define         PCI_TxAddr_p1           0x0600
 422 #define         PCI_TxAddr_p2           0x0604
 423 #define         PCI_RxAddr_p1           0x0608
 424 #define         PCI_RxAddr_p2           0x060C
 425 #define         MACAddr_P1              0x0610
 426 #define         MACAddr_P2              0x0614
 427 #define         BSSID_P1                0x0618
 428 #define         BSSID_P2                0x061C
 429 #define         BCNPLCPCfg              0x0620
 430 #define         GroupHash_P1            0x0624
 431 #define         GroupHash_P2            0x0628
 432 #define         WEPTxIV                 0x062C
 433
 434 #define         BasicRateTbl            0x0630
 435 #define         MandatoryRateTbl        0x0634
 436 #define         RTS_CTS_Rate            0x0638
 437
 438 #define         Wep_Protect             0x063C
 439 #define         RX_THRESHOLD            0x0640
 440 #define         TX_PE_CTRL              0x0644
 441
 442 #if defined(AMAC)
 443         #define AfterPNP                0x0648
 444 #endif
 445
 446 #if defined(OFDM)
 447         #define AckTime80211            0x0658
 448 #endif
 449
 450 #define         Rx_OFFSET               0x065c
 451
 452
 453 #define         PHYDelay                0x066C
 454 #define         BCNFIFO                 0x0670
 455 #define         SnifferOn               0x0674
 456 #define         EncryptionType          0x0678
 457 #define         RetryMAX                0x067C
 458 #define         CtlReg1                 0x0680  //Bit0:         IBSS mode
 459                                                                                 //Bit1:         PwrMgt mode
 460                                                                                 //Bit2-4 :      Highest basic Rate
 461                                                                                 //Bit5:         Lock bit
 462                                                                                 //Bit6:         PLCP weight select
 463                                                                                 //Bit7:         PLCP switch
 464 #define         DeviceState             0x0684
 465 #define         UnderrunCnt             0x0688
 466 #define         Rx_Filter               0x068c
 467 #define         Ack_Timeout_Ext         0x0690
 468 #define         BCN_FIFO_Semaphore      0x0694
 469 #define         IFS_Value               0x0698
 470 #define         RX_TIME_OUT             0x069C
 471 #define         TotalRxFrm              0x06A0
 472 #define         CRC32Cnt                0x06A4
 473 #define         CRC16Cnt                0x06A8
 474 #define         DecrypErr_UNI           0x06AC
 475 #define         RxFIFOOverrun           0x06B0
 476
 477 #define         DecrypErr_Mul           0x06BC
 478
 479 #define         NAV_CNT                 0x06C4
 480 #define         NAV_CCA                 0x06C8
 481 #define         RetryCnt                0x06CC
 482
 483 #define         ReadTcbAddress          0x06E8
 484
 485 #define         ReadRfdAddress          0x06EC
 486 #define         CWmin_CWmax             0x06F0
 487 #define         TotalTxFrm              0x06F4
 488 #define         RX_OFFSET_BYTE          0x06F8
 489
 490 #define         CAM_MODE                0x0700
 491 #define         CAM_ROLL_TB_LOW         0x0704
 492 #define         CAM_ROLL_TB_HIGH        0x0708
 493 #define         CAM_ADDRESS             0x070C
 494 #define         CAM_DATA                0x0710
 495 #define         DECRY_ERR_FLG_LOW       0x0714
 496 #define         DECRY_ERR_FLG_HIGH      0x0718
 497 #define         WEPKey0                 0x0720
 498 #define         WEPKey1                 0x0724
 499 #define         WEPKey2                 0x0728
 500 #define         WEPKey3                 0x072C
 501 #define         CAM_DEBUG               0x0728
 502 #define         CAM_STATUS              0x072c
 503 #define         WEPKey4                         0x0730
 504 #define         WEPKey5                         0x0734
 505 #define         WEPKey6                         0x0738
 506 #define         WEPKey7                         0x073C
 507 #define         WEPKey8                         0x0740
 508 #define         WEPKey9                         0x0744
 509 #define         WEPKey10                        0x0748
 510 #define         WEPKey11                        0x074C
 511 #define         WEPKey12                        0x0750
 512 #define         WEPKey13                        0x0754
 513 #define         WEPKey14                        0x0758
 514 #define         WEPKey15                        0x075c
 515 #define         TKIP_MODE                       0x0760
 516
 517 #define         Dbg_FIFO_Rd                     0x0800
 518 #define         Dbg_Select                      0x0804
 519 #define         FIFO_Length                     0x0808
 520
 521
 522 //#define               RF_Mode                                 0x080C
 523
 524 #define         RSSI_MGC                        0x0810
 525
 526 #define         PON                                     0x0818
 527 #define         Rx_ON                           0x081C
 528 #define         Tx_ON                           0x0820
 529 #define         CHIP_EN                         0x0824
 530 #define         LO_SW                           0x0828
 531 #define         TxRx_SW                         0x082C
 532 #define         S_MD                            0x0830
 533
 534 #define         USB_DEBUG_PORT          0x0888
 535
 536 // EEPROM Memmory Map Region
 537 #define         E2P_SUBID                       0x0900
 538 #define         E2P_POD                         0x0904
 539 #define         E2P_MACADDR_P1          0x0908
 540 #define         E2P_MACADDR_P2          0x090C
 541
 542 #ifndef HOST_IF_USB
 543 #define         E2P_PWR_CAL_VALUE       0x0910
 544
 545 #define         E2P_PWR_INT_VALUE       0x0920
 546
 547 #define         E2P_ALLOWED_CHANNEL     0x0930
 548 #define         E2P_PHY_REG                     0x0934
 549
 550 #define         E2P_REGION_CODE         0x0960
 551 #define         E2P_FEATURE_BITMAP      0x0964
 552 #endif
 553
 554 //-------------------------------------------------------------------------
 555 // Command Block (CB) Field Definitions
 556 //-------------------------------------------------------------------------
 557 //- RFD Command Bits
 558 #define RFD_EL_BIT              BIT_0           // RFD EL Bit
 559
 560 //- CB Command Word
 561 #define CB_S_BIT                0x1          // CB Suspend Bit
 562
 563 //- CB Status Word
 564 #define CB_STATUS_COMPLETE      0x1234          // CB Complete Bit
 565
 566 #define RFD_STATUS_COMPLETE     0x1234   //0x34120000       // RFD Complete Bit
 567
 568
 569 /**************************************************************************
 570 **              MAC Register Bit Definitions
 571 ***************************************************************************
 572 */
 573 // Interrupt STATUS
 574 #define TX_COMPLETE             BIT_0
 575 #define RX_COMPLETE             BIT_1
 576 #define RETRY_FAIL              BIT_2
 577 #define WAKE_UP                 BIT_3
 578 #define DTIM_NOTIFY             BIT_5
 579 #define CFG_NEXT_BCN            BIT_6
 580 #define BUS_ABORT               BIT_7
 581 #define TX_FIFO_READY           BIT_8
 582 #define UART_INT                BIT_9
 583
 584 #define TX_COMPLETE_EN          BIT_16
 585 #define RX_COMPLETE_EN          BIT_17
 586 #define RETRY_FAIL_EN           BIT_18
 587 #define WAKE_UP_EN              BIT_19
 588 #define DTIM_NOTIFY_EN          BIT_21
 589 #define CFG_NEXT_BCN_EN         BIT_22
 590 #define BUS_ABORT_EN            BIT_23
 591 #define TX_FIFO_READY_EN        BIT_24
 592 #define UART_INT_EN             BIT_25
 593
 594 #define FILTER_BEACON           0xFEFF //mask bit 8
 595 #define UN_FILTER_PS_POLL       0x0400
 596
 597 #define RX_LEN_THRESHOLD        0x640   //1600
 598
 599 #define DBG_MSG_SHOW            0x1
 600 #define DBG_MSG_HIDE            0x0
 601
 602
 603 #define RFD_POINTER(skb, macp)      ((zd1205_RFD_t *) (((unsigned char *)((skb)->data))-((macp)->rfd_size)))
 604 #define SKB_RFD_STATUS(skb, macp)   ((RFD_POINTER((skb),(macp)))->CbStatus)
 605
 606
 607 /**************************************************************************
 608 **              Descriptor Data Structure
 609 ***************************************************************************/
 610 struct driver_stats {
 611         struct net_device_stats net_stats;
 612         unsigned long tx_late_col;
 613         unsigned long tx_ok_defrd;
 614         unsigned long tx_one_retry;
 615         unsigned long tx_mt_one_retry;
 616         unsigned long rcv_cdt_frames;
 617         unsigned long xmt_fc_pkts;
 618         unsigned long rcv_fc_pkts;
 619         unsigned long rcv_fc_unsupported;
 620         unsigned long xmt_tco_pkts;
 621         unsigned long rcv_tco_pkts;
 622
 623         unsigned long rx_intr_pkts;
 624 };
 625
 626 //-------------------------------------------------------------------------
 627 // Transmit Command Block (TxCB)
 628 //-------------------------------------------------------------------------
 629 typedef struct zd1205_HwTCB_s {
 630         u32     CbStatus;                                       // Bolck status
 631         u32     CbCommand;                                      // Block command
 632         u32     NextCbPhyAddrLowPart;           // Next TCB address(low part)
 633         u32     NextCbPhyAddrHighPart;          // Next TCB address(high part)
 634         u32 TxCbFirstTbdAddrLowPart;    // First TBD address(low part)
 635         u32 TxCbFirstTbdAddrHighPart;   // First TBD address(high part)
 636         u32 TxCbTbdNumber;                              // Number of TBDs for this TCB
 637 } zd1205_HwTCB_t;
 638
 639 //-------------------------------------------------------------------------
 640 // Transmit Buffer Descriptor (TBD)
 641 //-------------------------------------------------------------------------
 642 typedef struct zd1205_TBD_s {
 643         u32 TbdBufferAddrLowPart;               // Physical Transmit Buffer Address
 644         u32 TbdBufferAddrHighPart;              // Physical Transmit Buffer Address
 645         u32 TbdCount;           // Data length
 646 #ifdef HOST_IF_USB
 647         u32 PrvFragLen;
 648 #endif
 649 } zd1205_TBD_t;
 650
 651 //-------------------------------------------------------------------------
 652 // Receive Frame Descriptor (RFD)
 653 //-------------------------------------------------------------------------
 654 typedef struct zd1205_RFD_s {
 655         u32     CbStatus;                               // Bolck status
 656         u32     ActualCount;                    // Rx buffer length
 657         u32     CbCommand;                              // Block command
 658         u32     MaxSize;                                //
 659         u32     NextCbPhyAddrLowPart;           // Next RFD address(low part)
 660         u32     NextCbPhyAddrHighPart;          // Next RFD address(high part)
 661         u8      RxBuffer[MAX_WLAN_SIZE];        // Rx buffer
 662         u32     Pad[2];                 // Pad to 16 bytes alignment - easy view for debug
 663 } __attribute__ ((__packed__)) zd1205_RFD_t;
 664
 665
 666 typedef struct zd1205_Ctrl_Set_s {
 667         u8      CtrlSetting[40];
 668 } zd1205_Ctrl_Set_t;
 669
 670 typedef struct zd1205_Header_s {
 671         u8      MacHeader[36];
 672
 673 } zd1205_Header_t;
 674
 675 //-------------------------------------------------------------------------
 676 // ZD1205SwTcb -- Software Transmit Control Block.  This structure contains
 677 // all of the variables that are related to a specific Transmit Control
 678 // block (TCB)
 679 //-------------------------------------------------------------------------
 680 typedef struct zd1205_SwTcb_s {
 681         // Link to the next SwTcb in the list
 682         struct zd1205_SwTcb_s *next;
 683         struct sk_buff *skb;
 684
 685         // physical and virtual pointers to the hardware TCB
 686         zd1205_HwTCB_t *pTcb;
 687         dma_addr_t TcbPhys;
 688
 689         // Physical and virtual pointers to the TBD array for this TCB
 690         zd1205_TBD_t *pFirstTbd;
 691         dma_addr_t FirstTbdPhys;
 692
 693         zd1205_Ctrl_Set_t *pHwCtrlPtr;
 694         dma_addr_t HwCtrlPhys;
 695
 696         zd1205_Header_t *pHwHeaderPtr;
 697         dma_addr_t HwHeaderPhys;
 698         u32 TcbCount;
 699         u8 LastFrag;
 700         u8 MsgID;
 701         u8 FrameType;
 702         u8 Rate;
 703         u16 aid;
 704         u8 bIntraBss;
 705 #if ZDCONF_LP_SUPPORT == 1
 706         U32                                     TotalLen;
 707 //    U8        PackInfo[18];
 708     U8 Padding[3]; //Used as Padding Content for A-MSDU
 709         U8      HdrInfo[8][16];
 710         void    *LP_bucket;
 711 #endif
 712
 713         //u8 encryType;
 714
 715 #ifdef HOST_IF_USB
 716         u8 bHasCompleteBeforeSend;
 717         u8 bHasBeenDelayedBefore;
 718 #endif
 719         u8 CalMIC[MIC_LNG+1];
 720         u8 MIC_Start;
 721         u8 MIC_Len;
 722         u32 LengthDiff;
 723 } zd1205_SwTcb_t;
 724
 725
 726 typedef struct SwTcbQ_s
 727 {
 728         zd1205_SwTcb_t  *first;         /* first zd1205_SwTcb_t in Q */
 729         zd1205_SwTcb_t  *last;          /* last zd1205_SwTcb_t in Q */
 730         u16                     count;          /* number of zd1205_SwTcb_t in Q */
 731 } zd1205_SwTcbQ_t;
 732
 733 //- Wireless 24-byte Header
 734 typedef struct wla_Header_s {
 735         u8              FrameCtrl[2];
 736         u8              Duration[2];
 737         u8              DA[6];
 738         u8              BSSID[6];
 739         u8              SA[6];
 740         u8              SeqCtrl[2];
 741 } wla_Header_t;
 742 struct hostap_ieee80211_hdr {
 743     u16 frame_control;
 744     u16 duration_id;
 745     u8 addr1[6];
 746     u8 addr2[6];
 747     u8 addr3[6];
 748     u16 seq_ctrl;
 749     u8 addr4[6];
 750 } __attribute__ ((packed));
 751
 752 //from station
 753 typedef struct plcp_wla_Header_s {
 754         u8              PlcpHdr[PLCP_HEADER];    //Oh! shit!!!
 755         u8              FrameCtrl[2];
 756         u8              Duration[2];
 757         u8              Address1[6];
 758         u8              Address2[6];
 759         u8              Address3[6];
 760         u8              SeqCtrl[2];
 761 } plcp_wla_Header_t;
 762
 763 typedef struct ctrl_Set_parm_s {
 764         u8                      Rate;
 765         u8                      Preamble;
 766         u8                      encryType;
 767         u8                      vapId;
 768         //u8                    bHwAppendMic;
 769         u32                     CurrFragLen;
 770         u32                     NextFragLen;
 771 } ctrl_Set_parm_t;
 772
 773 typedef struct tuple_s
 774 {
 775         u8              ta[6]; //TA (Address 2)
 776         u16             sn;
 777         u8              fn;
 778         u8              full;
 779 } tuple_t;
 780
 781 typedef struct tuple_Cache_s
 782 {
 783         tuple_t cache[TUPLE_CACHE_SIZE];
 784         u8 freeTpi;
 785 } tuple_Cache_t;
 786
 787 typedef struct defrag_Mpdu_s
 788 {
 789         u8      ta[6];
 790         u8      inUse;
 791         u8      fn;
 792         u32     eol;
 793         u16     sn;
 794         void    *buf;
 795         void    *dataStart;
 796 } defrag_Mpdu_t;
 797
 798
 799 typedef struct defrag_Array_s
 800 {
 801         defrag_Mpdu_t mpdu[MAX_DEFRAG_NUM];
 802 } defrag_Array_t;
 803
 804 /*Rx skb holding structure*/
 805 struct rx_list_elem {
 806         struct list_head list_elem;
 807         dma_addr_t dma_addr;
 808         struct sk_buff *skb;
 809 #ifdef HOST_IF_USB
 810         u32 UnFinishFrmLen;
 811 #endif
 812 }__attribute__ ((__packed__));
 813
 814
 815 #define ZD1211_MAX_MTU          2400
 816 #define MAX_EPINT_BUFFER        64
 817 #define NUM_TCB                         64//32
 818 #define NUM_TBD_PER_TCB         (2+MAX_SKB_FRAGS)       //3
 819 #define NUM_TBD                         (NUM_TCB * NUM_TBD_PER_TCB)
 820 /*===prince delete
 821 #define NUM_RFD                         32
 822 ===============*/
 823 //prince add begin
 824 #define NUM_RFD                         64
 825 //prince add end
 826
 827 #ifdef HOST_IF_USB
 828 //    #define ZD1205_INT_MASK           CFG_NEXT_BCN_EN | DTIM_NOTIFY_EN | WAKE_UP_EN
 829     #define ZD1205_INT_MASK             0x4F0000
 830 #else
 831     #define ZD1205_INT_MASK             TX_COMPLETE_EN | RX_COMPLETE_EN | RETRY_FAIL_EN | CFG_NEXT_BCN_EN | DTIM_NOTIFY_EN | WAKE_UP_EN | BUS_ABORT_EN
 832 #endif
 833 #define TX_RING_BYTES           (NUM_TCB * (sizeof(zd1205_HwTCB_t) + sizeof(zd1205_Ctrl_Set_t) + sizeof(zd1205_Header_t)))+ (NUM_TBD * sizeof(zd1205_TBD_t))
 834 #define ZD1205_REGS_SIZE        4096
 835 #define ZD_RX_OFFSET        0x03
 836
 837 struct zdap_ioctl {
 838         u16 cmd;                /* Command to run */
 839         u32 addr;                /* Length of the data buffer */
 840         u32 value;              /* Pointer to the data buffer */
 841         u8  data[0x100];
 842 };
 843
 844 struct zd1205_private
 845 {
 846         //linux used
 847         struct net_device       *device;
 848
 849 #ifdef HOST_IF_USB
 850         struct usb_device       *usb;
 851         int                     dev_index;
 852         struct urb              *ctrl_urb, *rx_urb, *tx_urb, *intr_urb, *reg_urb;
 853         struct urb              *read_urb, *write_urb; /* tmp urb pointer for rx_tasklet, tx_tasklet */
 854         wait_queue_head_t       regSet_wait;
 855         wait_queue_head_t       iorwRsp_wait;
 856         wait_queue_head_t       term_wait;
 857         wait_queue_head_t       msdelay;
 858         struct semaphore        ps_sem;
 859         struct semaphore        bcn_sem;
 860         struct semaphore        reg_sem;
 861         struct semaphore        config_sem;
 862     struct semaphore    ioctl_sem;
 863         struct usb_interface    *interface;             /* the interface for this device */
 864         spinlock_t              intr_lock;
 865         spinlock_t              rx_pool_lock;
 866         u8                      tx_buff[MAX_WLAN_SIZE];
 867 #if 1//(LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
 868         u8                      IntEPBuffer[MAX_EPINT_BUFFER];
 869 #else
 870         u8                      *IntEPBuffer;
 871         dma_addr_t              IntBufferHandle;
 872 #endif
 873 //<Slow Pairwise Key Install Fix>
 874     u8          EncTypeOfLastRxEapolPkt;
 875 //</Slow Pairwise Key Install Fix>
 876         u8                      IntEPBuffer2[MAX_EPINT_BUFFER];
 877         u8                      IntEPBuffer3[MAX_EPINT_BUFFER];
 878         u8                      num_interrupt_in;
 879         u8                      num_interrupt_out;
 880         u8                      num_bulk_in;
 881         u8                      num_bulk_out;
 882         u8                      in_interval;
 883         u8                      out_interval;
 884         u8                      ep4isIntOut;
 885         u8                      cmd_end;
 886         u8                      read_end;
 887         u8                      led_cnt ;
 888         u16                     wMaxPacketSize;
 889 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
 890         unsigned int            flags;
 891         unsigned int            kevent_flags;
 892 #else
 893         unsigned long           flags;
 894         unsigned long           kevent_flags;
 895 #endif
 896         int                     release;                        /* release number */
 897         int                     total_rx_cnt;
 898         int                     end;
 899         u32                     usbTxCnt;
 900         u32                     usbTxCompCnt;
 901         struct rx_list_elem **rx_struct_array;
 902         struct tasklet_struct zd1211_rx_tasklet;
 903         struct tasklet_struct zd1211_tx_tasklet;
 904         struct tasklet_struct rx_buff_tasklet;
 905         struct work_struct      scan_tout_event;
 906
 907         struct work_struct      kevent;
 908         struct zdap_ioctl       zdreq;
 909         struct ifreq            ifreq;
 910         struct zydas_wlan_param zd_wpa_req;
 911         int                     ifcmd;
 912
 913         //debug counter
 914         u32                     regWaitRCompCnt;
 915         u32                     regWaitWCompCnt;
 916         u32                     regRWCompCnt;
 917         u32                     regWaitRspCnt;
 918         u32                     regRspCompCnt;
 919         u32                     regUnCompCnt;
 920         u32                     regRdSleepCnt;
 921 #else
 922         struct pci_dev          *pdev;
 923 #endif
 924
 925         struct driver_stats     drv_stats;
 926 #if ZDCONF_WE_STAT_SUPPORT == 1
 927         struct iw_statistics iwstats;
 928 #elif !defined(ZDCONF_WE_STAT_SUPPORT)
 929         #error "Undefine ZDCONF_WE_STAT_SUPPORT"
 930 #endif
 931         struct timer_list       watchdog_timer;         /* watchdog timer id */
 932         struct timer_list       tm_chal_id;
 933         struct timer_list       tm_scan_id;
 934         struct timer_list       tm_auth_id;
 935         struct timer_list       tm_asoc_id;
 936         struct timer_list       tm_hking_id;
 937         struct timer_list       tm_mgt_id;
 938 #if ZDCONF_LP_SUPPORT == 1
 939     struct timer_list   tm_lp_poll_id;
 940 #endif
 941
 942         char                    ifname[IFNAMSIZ];
 943         spinlock_t              bd_lock;                /* board lock */
 944         spinlock_t              bd_non_tx_lock;         /* Non transmit command lock  */
 945         spinlock_t              q_lock;
 946         spinlock_t              cs_lock;
 947         spinlock_t              conf_lock;
 948         int                     using_dac;
 949         struct tasklet_struct zd1205_tasklet;
 950         struct tasklet_struct zd1205_ps_tasklet;
 951         struct tasklet_struct zd1205_tx_tasklet;
 952         struct proc_dir_entry *proc_parent;
 953         struct list_head        active_rx_list;         /* list of rx buffers */
 954         struct list_head        rx_struct_pool;         /* pool of rx buffer struct headers */
 955         u16                     rfd_size;
 956         u8                      rev_id;                 /* adapter PCI revision ID */
 957         u8                      sniffer_on;
 958         int                     skb_req;                /* number of skbs neede by the adapter */
 959
 960         rwlock_t                isolate_lock;
 961
 962         int                     driver_isolated;
 963         char                    *cable_status;
 964         void                    *regp;
 965         u8                      macAdr[8];
 966         u8                      mcastAdr[8];
 967         u32                     intrMask;
 968         zd1205_SwTcbQ_t         *freeTxQ;
 969         zd1205_SwTcbQ_t         *activeTxQ;
 970         u32                     txCachedSize;
 971         u8                      *txCached;
 972         u16                     dtimCount;
 973         u8                      numTcb;
 974         u16                     numTbd;
 975         u8                      numRfd;
 976         u8                      numTbdPerTcb;
 977         u32                     rxOffset;
 978         u32                     debugflag;
 979         card_Setting_t          cardSetting;
 980         u8                      BSSID[8];
 981         u32                     dbg_flag;
 982
 983         //debug counter
 984         u32                     bcnCnt;
 985         u32                     dtimCnt;
 986         u32                     txCmpCnt;
 987         u32                     rxCnt;
 988         u32                     retryFailCnt;
 989         u32                     txCnt;
 990         u32                     txIdleCnt;
 991         u32                     rxIdleCnt;
 992         u32                     rxDupCnt;
 993
 994         u32                     DriverDiscardedFrmCauseByMulticastList;
 995         u32                     DriverDiscardedFrmCauseByFrmCtrl;
 996         u32                     DriverReceivedFrm;
 997         u32                     DriverRxMgtFrmCnt;
 998         u32                     ErrLongFrmCnt;
 999         u32                     ErrShortFrmCnt;
1000
1001         u32                     ErrToHostFrmCnt;
1002         u32                     ErrZeroLenFrmCnt;
1003         u32                     ArFreeFailCnt;
1004         u32                     ArSearchFailCnt;
1005         u32                     ArAgedCnt;
1006
1007         u32                     DropFirstFragCnt;
1008         u32                     rxNeedFragCnt;
1009         u32                     rxCompFragCnt;
1010         u32                     AllocSkbFailCnt;
1011         u32                     txQueToUpCnt;
1012         u32                     txQueSetCnt;
1013         u32                     sleepCnt;
1014         u32                     wakeupCnt;
1015
1016         //HMAC counter
1017         u32                     hwTotalRxFrm;
1018         u32                     hwCRC32Cnt;
1019         u32                     hwCRC16Cnt;
1020         u32                     hwDecrypErr_UNI;
1021         u32                     hwDecrypErr_Mul;
1022         u32                     hwRxFIFOOverrun;
1023         u32                     hwTotalTxFrm;
1024         u32                     hwUnderrunCnt;
1025
1026         u32                     hwRetryCnt;
1027         u32                     TxStartTime;
1028         u32                     HMAC_TxTimeout;
1029
1030         u8                      bTraceSetPoint;
1031         u8                      bEnableTxPwrCtrl;
1032         u8                      TxOFDMCnt;
1033         u8                      TxOFDMType;
1034         u8                      TxPwrCCK;
1035         u8                      TxPwrOFDM;          // 6M - 36M
1036         u8                      bFixedRate;
1037     u8          bContinueTx;
1038         u8                      bDataTrafficLight;
1039         u8                      NoBcnDetectedCnt;
1040         u8                      LinkTimer;
1041         u32                     LinkLEDn;
1042         u32                     LinkLED_OnDur;
1043         u32                     LinkLED_OffDur;
1044         u32                     DataLED;
1045
1046         u16                     AddrEntryTable;
1047         u8                      bAllowAccessRegister;
1048         U8                      FlashType;
1049         u16                     ReadRegCount;
1050         u16                     SetPoint;
1051         u8                      dtim_notify_en;
1052         u8                      config_next_bcn_en;
1053
1054         u32                     invalid_frame_good_crc;
1055         u8                      bGkInstalled;
1056         u8                      rxSignalQuality;
1057
1058         u8                      rxSignalStrength;
1059         u8                      rxSignalQualityIndB;
1060         u8                      rxSignalQuality1;
1061         u8                      rxSignalQuality2;
1062         u16                     EepSetPoint[14];
1063         u16                     SetPointOFDM[3][14];//JWEI 2003/12/31
1064         u32                     RegionCode;
1065         u32                     RF_Mode;
1066         u8                      PA_Type;
1067         u8                      MaxTxPwrSet;
1068         u8                      MinTxPwrSet;
1069         u8                      bss_index;
1070         bss_info_t              BSSInfo[BSS_INFO_NUM];
1071         tuple_Cache_t           cache;
1072
1073         defrag_Array_t          defragArray;
1074         rxInfo_t                rxInfo;
1075
1076         //added for STA
1077         atomic_t                DoNotSleep;
1078         u8                      bSurpriseRemoved;
1079         u8                      bAssoc;
1080         u8                      PwrState;
1081         u8                      SuggestionMode;
1082         u8                      bPSMSupported;
1083         u8                      bAPAlive;
1084         u8                      BSS_Members;
1085         u8                      Notification;
1086         u8                      WorseSQThr;
1087         u8                      bIBSS_Wakeup_Dest;
1088         u8                      bFrmRxed1;
1089         u8                      bAnyActivity;
1090         u8                      NiceSQThr;
1091         u8                      NiceSQThr_OFDM;
1092         u8                      bEnableSwAntennaDiv;
1093         u8                      Ant_MonitorDur1;
1094         u8                      Ant_MonitorDur2;
1095         u8                      CR138Flag;
1096         u8                      MulticastAddr[194]; // the first byte is the number of multicast addresses
1097         u32                     TotalTxDataFrmBytes;
1098
1099         u32                     TotalRxDataFrmBytes;
1100         u32                     txMulticastFrm;
1101         u32                     txMulticastOctets;
1102         u32                     txUnicastFrm;
1103         u32                     txUnicastOctets;
1104         u32                     NormalBackoff;
1105         u32                     UrgentBackoff;
1106         u32                     LooseBackoff;
1107         u32                     Acc_Num_OFDM;
1108         u32                     Acc_SQ_OFDM;
1109         u32                     Bcn_Acc_Num;
1110         u32                     Bcn_Acc_SQ;
1111         u32                     CheckForHangLoop;
1112         u16                     SequenceNum;
1113         u16                     iv16;
1114         u32                     iv32;
1115         u32                     Acc_Num;
1116         u32                     Acc_SQ;
1117         u32                     GroupHashP1;
1118         u32                     GroupHashP2;
1119         u32                     PSThreshhold;
1120         u8                      rxDecryType;
1121         u32                     rx11bDataFrame;
1122         u32                     rxOFDMDataFrame;
1123
1124 #ifdef OFDM
1125         u8                      bTxBurstEnable;
1126         int                     TxBurstCount;
1127 #endif
1128
1129 #ifdef HOST_IF_USB
1130         u32                     USBCSRAddress;
1131         u8                      bUSBDeveiceAttached;
1132         u8                      bUSBDeveiceResetting;
1133         u8                      bHandleNonRxTxRunning;
1134         u32                     REG_6e4_Add;
1135         u32                     Continue2Rx;
1136         u8                      LastZDContinuousTxRate;
1137         u32                     WaitLenInfoCnt;
1138         u32                     CompLenInfoCnt;
1139         u32                     NoMergedRxCnt;
1140         u8                      bFlashable;
1141 #endif
1142
1143         u8                      bDisableTx;
1144         u8                      PHYSettingFlag;
1145         u8                      PHYTestIndex;
1146         u8                      PHYTestTimer;
1147         u8                      PHYTestTimerCount;
1148         u8                      PHYTestRssiBound;
1149         u8                      PHYTestRssi;
1150         u8                      PHYLowPower;
1151         u8                      IPCFlag;
1152         u8                      AdapterMaxRate;
1153
1154         u8                      PHYFreOFDMframe;
1155         u8                      EnableTxPwrCtrl;
1156
1157         u32                     PHYTestTotal;
1158         u32                     TrafficBound;
1159         u32                     DriverRxFrmCnt;
1160         u64                     rxDataPerSec;
1161         u64                     txDataPerSec;
1162
1163     U8          bContinueTxMode;
1164     U32         AllowRateArrayCount;
1165
1166 // counter
1167     U32         rxMulticastFrm;
1168     U32         rxMulticastOctets;
1169     U32         rxBroadcastFrm;
1170     U32         rxBroadcastOctets;
1171     U32         rxUnicastFrm;
1172     U32         rxUnicastOctets;
1173     U32         rxNeedFrag;
1174     U32         rxMgtFrm;
1175     U32         txFrmDrvMgt;
1176
1177 // debug counter
1178     U32         rxDiscardByNotPIBSS;
1179     U32         rxDiscardByAllocateBuf;
1180
1181     U16         SetPointLevel;
1182     U8          bPseudoIBSSMode;
1183
1184
1185
1186         u32                     txUnCachedSize;
1187         dma_addr_t              txUnCachedPhys;
1188         void                    *txUnCached;
1189         //Modified for Supplicant
1190         int                     bDefaultIbssMacMode;
1191         u32     bOLBC;
1192         u32     nOLBC_CounterInSec;
1193
1194 //prince add begin
1195         U8      ModeChBssType;
1196         U16     CurrScanCH;
1197         U16     LastCurrScanCH;
1198         U16     ModeChChannel;
1199         U8      ModeChMacMode;
1200 //prince add end
1201         U8 IBSS_DesiredMacMode;
1202         U8 IBSS_DesiredChannel;
1203
1204         U32     lastRxComp;
1205 };
1206 typedef struct _ZDTYPE_UWTxGain
1207 {
1208         U8      UWTxGainLevel;
1209         U32      UWTxGainValue;
1210 } ZDTYPE_UWTxGain, *PZDTYPE_UWTxGain;
1211
1212 typedef struct zd1205_private   zd1205_private_t;
1213
1214
1215 struct usb_eth_dev {
1216         char    *name;
1217         __u16   vendor;
1218
1219         __u16   device;
1220         __u32   private; /* LSB is gpio reset value */
1221 };
1222
1223 #define ZD_IOCTL_REG_READ                       0x01
1224 #define ZD_IOCTL_REG_WRITE                      0x02
1225 #define ZD_IOCTL_MEM_DUMP                       0x03
1226 #define ZD_IOCTL_RATE                           0x04
1227 #define ZD_IOCTL_SNIFFER                        0x05
1228 #define ZD_IOCTL_CAM_DUMP                       0x06
1229 #define ZD_IOCTL_DUMP_PHY                       0x07
1230 #define ZD_IOCTL_CARD_SETTING                   0x08
1231 #define ZD_IOCTL_HASH_DUMP                      0x09
1232 #define ZD_IOCTL_RFD_DUMP                       0x0A
1233 #define ZD_IOCTL_MEM_READ                       0x0B
1234 #define ZD_IOCTL_MEM_WRITE                      0x0C
1235
1236 //for STA
1237 #define ZD_IOCTL_TX_RATE                        0x0D
1238 #define ZD_IOCTL_EEPROM                         0x0E
1239
1240 //for debug purposes
1241 #define ZD_IOCTL_BCN                            0x10
1242 #define ZD_IOCTL_REG_READ16                     0x11
1243 #define ZD_IOCTL_REG_WRITE16                    0x12
1244
1245 //for CAM Test
1246 #define ZD_IOCTL_CAM_READ                       0x13
1247 #define ZD_IOCTL_CAM_WRITE                      0x14
1248 #define ZD_IOCTL_CAM_RESET                      0x15
1249 #define ZD_IOCTL_READ_PHY                       0x16
1250 #define ZD_IOCTL_WRITE_PHY                      0x17
1251 #define ZD_IOCTL_CONT_TX                        0x18
1252 #define ZD_IOCTL_SET_MIC_CNT_ENABLE 0x19
1253 #define ZD_IOCTL_GET_MIC_CNT_ENABLE 0x1A
1254 //prince add for CFCC begin
1255 #define ZD_IOCTL_SET_CHANNEL        0x1B
1256 //prince add for CFCC end
1257
1258 #define ZD_IOCTL_DEBUG_FLAG             0x21
1259 #define ZD_IOCTL_UW_PWR             0x29
1260
1261 #define ZDAPIOCTL       SIOCDEVPRIVATE
1262 #define ZDPRODUCTIOCTL          0x89FA
1263
1264
1265 /**************************************************************************
1266 **              Function Declarations
1267 ***************************************************************************
1268 */
1269 void zd1205_sleep_reset(struct zd1205_private *macp);
1270 void zd1205_sw_reset(struct zd1205_private *macp);
1271 void zd1205_watchdog_cb(struct net_device *);
1272 void zd1205_dump_data(char *info, u8 *data, u32 data_len);
1273 void zd1205_init_card_setting(struct zd1205_private *macp);
1274 void zd1205_load_card_setting(struct zd1205_private *macp, u8 bInit);
1275 void zd1205_save_card_setting(struct zd1205_private *macp);
1276 zd1205_SwTcb_t * zd1205_first_txq(struct zd1205_private *macp, zd1205_SwTcbQ_t *Q);
1277 u32 zd_readl(u32 offset);
1278 void zd_writel(u32 value, u32 offset);
1279 void zd1205_disable_int(void);
1280 void zd1205_enable_int(void);
1281 void zd1205_lock(struct zd1205_private *macp);
1282 void zd1205_unlock(struct zd1205_private *macp);
1283 void zd1205_device_reset(struct zd1205_private *macp);
1284 void zd1205_config_wep_keys(struct zd1205_private *macp);
1285 struct sk_buff* zd1205_prepare_tx_data(struct zd1205_private *macp, u16 bodyLen);
1286 void zd1205_tx_test(struct zd1205_private *macp, u16 size);
1287 void zd1205_qlast_txq(struct zd1205_private *macp, zd1205_SwTcbQ_t *Q, zd1205_SwTcb_t *signal);
1288 int zd1205_DestPowerSave(struct zd1205_private *macp, u8 *pDestAddr);
1289 int zd1205_found1(struct pci_dev *pcid, const struct pci_device_id *ent);
1290 void zd1205_remove1(struct pci_dev *pcid);
1291 BOOLEAN a_OSC_get_cal_int( u8 ch, u32 rate, u8 *intValue, u8 *calValue);
1292 void zd1205_tx_isr(struct zd1205_private *);
1293 u32 zd1205_rx_isr(struct zd1205_private *macp);
1294 void  zd1205_clear_structs(struct net_device *dev);
1295 unsigned char zd1205_init(struct zd1205_private *);
1296 int zd1205_open(struct net_device *);
1297 int zd1205_close(struct net_device *);
1298 int zd1205_change_mtu(struct net_device *, int);
1299 int zd1205_set_mac(struct net_device *, void *);
1300 void zd1205_set_multi(struct net_device *);
1301 void zd1205_IncreaseTxPower(struct zd1205_private *macp, u8 TxPwrType);
1302 void zd1205_DecreaseTxPower(struct zd1205_private *macp, u8 TxPwrType);
1303 void iLED_ON(struct zd1205_private *macp, u32 LEDn);
1304 void iLED_OFF(struct zd1205_private *macp, u32 LEDn);
1305 void iLED_SWITCH(struct zd1205_private *macp, u32 LEDn);
1306 void HKeepingCB(struct net_device *dev);
1307 void zd1205_mgt_mon_cb(struct net_device *dev);
1308 void zd1205_lp_poll_cb(struct net_device *dev);
1309 int zd1205_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1310 int zd1205_xmit_frame(struct sk_buff *skb, struct net_device *dev);
1311 struct net_device_stats *zd1205_get_stats(struct net_device *);
1312 void hostap_michael_mic_failure(struct zd1205_private *macp,
1313         struct hostap_ieee80211_hdr *hdr, int keyidx);
1314 #ifndef HOST_IF_USB
1315     void zd1205_start_ru(struct zd1205_private *);
1316 #else
1317     struct rx_list_elem *zd1205_start_ru(struct zd1205_private *);
1318 #endif
1319 void zd1205_process_wakeup(struct zd1205_private *macp);
1320 void zd1205_connect_mon(struct zd1205_private *macp);
1321
1322 void zd1205_watchdog(struct zd1205_private *macp);
1323 void zd1205_house_keeping(struct zd1205_private *macp);
1324 void zd1211_set_multicast(struct zd1205_private *macp);
1325 int zd1205_dis_connect(struct zd1205_private *macp);
1326 void ChangeMacMode(u8 MAC_Mode, u8 Channel);
1327 void zd1205_alloc_skbs(struct zd1205_private *macp);
1328 BssInfo_t *zd1212_bssid_to_BssInfo(U8 *bssid);
1329
1330 //prince add begin
1331 int zd1205_moxa_repeat( struct zd1205_private *macp);
1332 int zd1205_dis_update_setting( struct zd1205_private *macp);
1333 //prince add end
1334
1335 #if ZDCONF_WE_STAT_SUPPORT == 1
1336         struct iw_statistics * zd1205_iw_getstats(struct net_device *dev);
1337 #elif !defined(ZDCONF_WE_STAT_SUPPORT)
1338         #error "Undefine ZDCONF_WE_STAT_SUPPORT"
1339 #endif
1340 #endif  /* _ZD1205_H_ */
1341