drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /* statistics can be kept for for tuning/monitoring */
  25 struct ehci_stats {
  26         /* irq usage */
  27         unsigned long           normal;
  28         unsigned long           error;
  29         unsigned long           reclaim;
  30         unsigned long           lost_iaa;
  31
  32         /* termination of urbs from core */
  33         unsigned long           complete;
  34         unsigned long           unlink;
  35 };
  36
  37 /* ehci_hcd->lock guards shared data against other CPUs:
  38  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  39  *   hcd_dev:   ep[]
  40  *   ehci_qh:   qh_next, qtd_list
  41  *   ehci_qtd:  qtd_list
  42  *
  43  * Also, hold this lock when talking to HC registers or
  44  * when updating hw_* fields in shared qh/qtd/... structures.
  45  */
  46
  47 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  48
  49 struct ehci_hcd {                       /* one per controller */
  50         spinlock_t              lock;
  51
  52         /* async schedule support */
  53         struct ehci_qh          *async;
  54         struct ehci_qh          *reclaim;
  55         unsigned                reclaim_ready : 1;
  56         unsigned                scanning : 1;
  57
  58         /* periodic schedule support */
  59 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  60         unsigned                periodic_size;
  61         __le32                  *periodic;      /* hw periodic table */
  62         dma_addr_t              periodic_dma;
  63         unsigned                i_thresh;       /* uframes HC might cache */
  64
  65         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  66         int                     next_uframe;    /* scan periodic, start here */
  67         unsigned                periodic_sched; /* periodic activity count */
  68
  69         /* per root hub port */
  70         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  71
  72         /* glue to PCI and HCD framework */
  73         struct usb_hcd          hcd;
  74         struct ehci_caps __iomem *caps;
  75         struct ehci_regs __iomem *regs;
  76         __u32                   hcs_params;     /* cached register copy */
  77
  78         /* per-HC memory pools (could be per-bus, but ...) */
  79         struct dma_pool         *qh_pool;       /* qh per active urb */
  80         struct dma_pool         *qtd_pool;      /* one or more per qh */
  81         struct dma_pool         *itd_pool;      /* itd per iso urb */
  82         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
  83
  84         struct timer_list       watchdog;
  85         struct notifier_block   reboot_notifier;
  86         unsigned long           actions;
  87         unsigned                stamp;
  88         unsigned long           next_statechange;
  89         u32                     command;
  90
  91         unsigned                is_arc_rh_tt:1; /* ARC roothub with TT */
  92
  93         /* irq statistics */
  94 #ifdef EHCI_STATS
  95         struct ehci_stats       stats;
  96 #       define COUNT(x) do { (x)++; } while (0)
  97 #else
  98 #       define COUNT(x) do {} while (0)
  99 #endif
 100 };
 101
 102 /* unwrap an HCD pointer to get an EHCI_HCD pointer */
 103 #define hcd_to_ehci(hcd_ptr) container_of(hcd_ptr, struct ehci_hcd, hcd)
 104
 105
 106 enum ehci_timer_action {
 107         TIMER_IO_WATCHDOG,
 108         TIMER_IAA_WATCHDOG,
 109         TIMER_ASYNC_SHRINK,
 110         TIMER_ASYNC_OFF,
 111 };
 112
 113 static inline void
 114 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 115 {
 116         clear_bit (action, &ehci->actions);
 117 }
 118
 119 static inline void
 120 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 121 {
 122         if (!test_and_set_bit (action, &ehci->actions)) {
 123                 unsigned long t;
 124
 125                 switch (action) {
 126                 case TIMER_IAA_WATCHDOG:
 127                         t = EHCI_IAA_JIFFIES;
 128                         break;
 129                 case TIMER_IO_WATCHDOG:
 130                         t = EHCI_IO_JIFFIES;
 131                         break;
 132                 case TIMER_ASYNC_OFF:
 133                         t = EHCI_ASYNC_JIFFIES;
 134                         break;
 135                 // case TIMER_ASYNC_SHRINK:
 136                 default:
 137                         t = EHCI_SHRINK_JIFFIES;
 138                         break;
 139                 }
 140                 t += jiffies;
 141                 // all timings except IAA watchdog can be overridden.
 142                 // async queue SHRINK often precedes IAA.  while it's ready
 143                 // to go OFF neither can matter, and afterwards the IO
 144                 // watchdog stops unless there's still periodic traffic.
 145                 if (action != TIMER_IAA_WATCHDOG
 146                                 && t > ehci->watchdog.expires
 147                                 && timer_pending (&ehci->watchdog))
 148                         return;
 149                 mod_timer (&ehci->watchdog, t);
 150         }
 151 }
 152
 153 /*-------------------------------------------------------------------------*/
 154
 155 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 156
 157 /* Section 2.2 Host Controller Capability Registers */
 158 struct ehci_caps {
 159         /* these fields are specified as 8 and 16 bit registers,
 160          * but some hosts can't perform 8 or 16 bit PCI accesses.
 161          */
 162         u32     hc_capbase;
 163 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 164 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 165         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 166 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 167 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 168 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 169 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 170 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 171 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 172 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 173
 174         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 175 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 176 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 177 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 178 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 179 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 180 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 181         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 182 } __attribute__ ((packed));
 183
 184
 185 /* Section 2.3 Host Controller Operational Registers */
 186 struct ehci_regs {
 187
 188         /* USBCMD: offset 0x00 */
 189         u32             command;
 190 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 191 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 192 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 193 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 194 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 195 #define CMD_ASE         (1<<5)          /* async schedule enable */
 196 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 197 /* 3:2 is periodic frame list size */
 198 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 199 #define CMD_RUN         (1<<0)          /* start/stop HC */
 200
 201         /* USBSTS: offset 0x04 */
 202         u32             status;
 203 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 204 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 205 #define STS_RECL        (1<<13)         /* Reclamation */
 206 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 207 /* some bits reserved */
 208         /* these STS_* flags are also intr_enable bits (USBINTR) */
 209 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 210 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 211 #define STS_FLR         (1<<3)          /* frame list rolled over */
 212 #define STS_PCD         (1<<2)          /* port change detect */
 213 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 214 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 215
 216         /* USBINTR: offset 0x08 */
 217         u32             intr_enable;
 218
 219         /* FRINDEX: offset 0x0C */
 220         u32             frame_index;    /* current microframe number */
 221         /* CTRLDSSEGMENT: offset 0x10 */
 222         u32             segment;        /* address bits 63:32 if needed */
 223         /* PERIODICLISTBASE: offset 0x14 */
 224         u32             frame_list;     /* points to periodic list */
 225         /* ASYNCLISTADDR: offset 0x18 */
 226         u32             async_next;     /* address of next async queue head */
 227
 228 #ifdef CONFIG_ARCH_MOXACPU
 229         /* not used: offset 0x1C */
 230         u32             reserved;
 231
 232         /* PORTSC: offset 0x20 */
 233         u32             port_status [1];        /* just one port */
 234 /* 31:23 reserved */
 235 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 236 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 237 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 238 /* 19:16 for port testing */
 239 #define PORT_LED_OFF    (0<<14)
 240 #define PORT_LED_AMBER  (1<<14)
 241 #define PORT_LED_GREEN  (2<<14)
 242 #define PORT_LED_MASK   (3<<14)
 243 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 244 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 245 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 246 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 247 /* 9 reserved */
 248 #define PORT_RESET      (1<<8)          /* reset port */
 249 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 250 #define PORT_RESUME     (1<<6)          /* resume it */
 251 #define PORT_OCC        (1<<5)          /* over current change */
 252 #define PORT_OC         (1<<4)          /* over current active */
 253 #define PORT_PEC        (1<<3)          /* port enable change */
 254 #define PORT_PE         (1<<2)          /* port enable */
 255 #define PORT_CSC        (1<<1)          /* connect status change */
 256 #define PORT_CONNECT    (1<<0)          /* device connected */
 257
 258         /* EOF time & asynchronous schedule sleep timer register: offset 0x24 */
 259         u32             eof_time;
 260 #define U_SUSP_N        (1<<6)          /* transceiver suspend mode */
 261
 262 #define EOF2_TIME_MASK  (3<<4)
 263 #define EOF2_TIME_2     (0<<4)          /* high-speed E0F2 time 2 clocks */
 264 #define EOF2_TIME_4     (1<<4)          /* high-speed EOF2 time 4 clocks */
 265 #define EOF2_TIME_8     (2<<4)          /* high-speed EOF2 time 8 clocks */
 266 #define EOF2_TIME_16    (3<<4)          /* high-speed EOF2 time 16 clocks */
 267 #define EOF2_TIME_20    (0<<4)          /* full-speed EOF2 time 20 clocks */
 268 #define EOF2_TIME_40    (1<<4)          /* full-speed EOF2 time 40 clocks */
 269 #define EOF2_TIME_80    (2<<4)          /* full-speed EOF2 time 80 clocks */
 270 #define EOF2_TIME_160   (3<<4)          /* full-speed EOF2 time 160 clocks */
 271 #define EOF2_TIME_40L   (0<<4)          /* low-speed EOF2 time 40 clocks */
 272 #define EOF2_TIME_80L   (1<<4)          /* low-speed EOF2 time 80 clocks */
 273 #define EOF2_TIME_160L  (2<<4)          /* low-speed EOF2 time 160 clocks */
 274 #define EOF2_TIME_320L  (3<<4)          /* low-speed EOF2 time 320 clocks */
 275
 276         /* 0x28 - 0x2C : reserved */
 277         u32             reserved2[2];
 278
 279         /* bus monitor control/status: offset 0x30 */
 280         u32             bus_mon;
 281 #define HOST_SPEED_MASK (3<<9)
 282 #define HOST_SPEED_HS   (2<<9)          /* High speed */
 283 #define HOST_SPEED_FS   (0<<9)          /* full speed */
 284 #define HOST_SPEED_LS   (1<<9)          /* low speed */
 285 #define VBUS_VLD        (0<<8)          /* VBUS valid */
 286 #define VBUS_INVLD      (1<<8)          /* VBUS invalid */
 287 #define FORCE_HIGH_SPEED        (1<<6)
 288 #define FORCE_FULL_SPEED        (1<<7)
 289 #define VBUS_ON         (0<<4)          /* VBUS on */
 290 #define VBUS_OFF        (1<<4)          /* VBUS off */
 291 #define INT_ACT_LOW     (0<<3)          /* interrupt active low */
 292 #define INT_ACT_HIGH    (1<<3)          /* interrupt active high */
 293
 294         /* bus monitor interrupt status: offset 0x34 */
 295         u32             bus_mon_int;
 296
 297         /* bus monitor interrrupt enable: offset 0x38 */
 298         u32             bus_mon_int_enable;
 299
 300         /* 0x3C reserved */
 301         u32             reserved3;
 302
 303         /* test register: offset 0x40 */
 304         u32             test;
 305
 306         /* vendor specific IO control: offset 0x44 */
 307         u32             vendor_io;
 308
 309         /* vendor specific status: offset 0x48 */
 310         u32             vendor_status;
 311
 312         /* 0x4c - 0x5c reserved */
 313         u32             reserved4[5];
 314
 315         /* DMA controller parameter setting 1: offset 0x60 */
 316         u32             dma_cntl1;
 317
 318         /* DMA controller parameter setting 2: offset 0x64 */
 319         u32             dma_cntl2;
 320
 321         /* 0x68 - 0x6c reserved */
 322         u32             reserved5[2];
 323
 324         /* PHY control register */
 325         u32             phy_ctrl;
 326 #define PHY_RESET       (1<<15)
 327 #else   // CONFIG_ARCH_MOXACPU
 328         u32             reserved [9];
 329
 330         /* CONFIGFLAG: offset 0x40 */
 331         u32             configured_flag;
 332 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 333
 334         /* PORTSC: offset 0x44 */
 335         u32             port_status [0];        /* up to N_PORTS */
 336 /* 31:23 reserved */
 337 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 338 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 339 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 340 /* 19:16 for port testing */
 341 #define PORT_LED_OFF    (0<<14)
 342 #define PORT_LED_AMBER  (1<<14)
 343 #define PORT_LED_GREEN  (2<<14)
 344 #define PORT_LED_MASK   (3<<14)
 345 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 346 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 347 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 348 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 349 /* 9 reserved */
 350 #define PORT_RESET      (1<<8)          /* reset port */
 351 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 352 #define PORT_RESUME     (1<<6)          /* resume it */
 353 #define PORT_OCC        (1<<5)          /* over current change */
 354 #define PORT_OC         (1<<4)          /* over current active */
 355 #define PORT_PEC        (1<<3)          /* port enable change */
 356 #define PORT_PE         (1<<2)          /* port enable */
 357 #define PORT_CSC        (1<<1)          /* connect status change */
 358 #define PORT_CONNECT    (1<<0)          /* device connected */
 359 #endif  // CONFIG_ARCH_MOXACPU
 360 } __attribute__ ((packed));
 361
 362
 363 /*-------------------------------------------------------------------------*/
 364
 365 #define QTD_NEXT(dma)   cpu_to_le32((u32)dma)
 366
 367 /*
 368  * EHCI Specification 0.95 Section 3.5
 369  * QTD: describe data transfer components (buffer, direction, ...)
 370  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 371  *
 372  * These are associated only with "QH" (Queue Head) structures,
 373  * used with control, bulk, and interrupt transfers.
 374  */
 375 struct ehci_qtd {
 376         /* first part defined by EHCI spec */
 377         __le32                  hw_next;          /* see EHCI 3.5.1 */
 378         __le32                  hw_alt_next;      /* see EHCI 3.5.2 */
 379         __le32                  hw_token;         /* see EHCI 3.5.3 */
 380 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 381 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 382 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 383 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 384 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 385 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 386 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 387 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 388 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 389 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 390 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 391 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 392 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 393         __le32                  hw_buf [5];        /* see EHCI 3.5.4 */
 394         __le32                  hw_buf_hi [5];        /* Appendix B */
 395
 396         /* the rest is HCD-private */
 397         dma_addr_t              qtd_dma;                /* qtd address */
 398         struct list_head        qtd_list;               /* sw qtd list */
 399         struct urb              *urb;                   /* qtd's urb */
 400         size_t                  length;                 /* length of buffer */
 401 } __attribute__ ((aligned (32)));
 402
 403 /* mask NakCnt+T in qh->hw_alt_next */
 404 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
 405
 406 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 407
 408 /*-------------------------------------------------------------------------*/
 409
 410 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 411 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
 412
 413 /* values for that type tag */
 414 #define Q_TYPE_ITD      __constant_cpu_to_le32 (0 << 1)
 415 #define Q_TYPE_QH       __constant_cpu_to_le32 (1 << 1)
 416 #define Q_TYPE_SITD     __constant_cpu_to_le32 (2 << 1)
 417 #define Q_TYPE_FSTN     __constant_cpu_to_le32 (3 << 1)
 418
 419 /* next async queue entry, or pointer to interrupt/periodic QH */
 420 #define QH_NEXT(dma)    (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
 421
 422 /* for periodic/async schedules and qtd lists, mark end of list */
 423 #define EHCI_LIST_END   __constant_cpu_to_le32(1) /* "null pointer" to hw */
 424
 425 /*
 426  * Entries in periodic shadow table are pointers to one of four kinds
 427  * of data structure.  That's dictated by the hardware; a type tag is
 428  * encoded in the low bits of the hardware's periodic schedule.  Use
 429  * Q_NEXT_TYPE to get the tag.
 430  *
 431  * For entries in the async schedule, the type tag always says "qh".
 432  */
 433 union ehci_shadow {
 434         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 435         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 436         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 437         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 438         u32                     *hw_next;       /* (all types) */
 439         void                    *ptr;
 440 };
 441
 442 /*-------------------------------------------------------------------------*/
 443
 444 /*
 445  * EHCI Specification 0.95 Section 3.6
 446  * QH: describes control/bulk/interrupt endpoints
 447  * See Fig 3-7 "Queue Head Structure Layout".
 448  *
 449  * These appear in both the async and (for interrupt) periodic schedules.
 450  */
 451
 452 struct ehci_qh {
 453         /* first part defined by EHCI spec */
 454         __le32                  hw_next;         /* see EHCI 3.6.1 */
 455         __le32                  hw_info1;        /* see EHCI 3.6.2 */
 456 #define QH_HEAD         0x00008000
 457         __le32                  hw_info2;        /* see EHCI 3.6.2 */
 458         __le32                  hw_current;      /* qtd list - see EHCI 3.6.4 */
 459
 460         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 461         __le32                  hw_qtd_next;
 462         __le32                  hw_alt_next;
 463         __le32                  hw_token;
 464         __le32                  hw_buf [5];
 465         __le32                  hw_buf_hi [5];
 466
 467         /* the rest is HCD-private */
 468         dma_addr_t              qh_dma;         /* address of qh */
 469         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 470         struct list_head        qtd_list;       /* sw qtd list */
 471         struct ehci_qtd         *dummy;
 472         struct ehci_qh          *reclaim;       /* next to reclaim */
 473
 474         struct ehci_hcd         *ehci;
 475         struct kref             kref;
 476         unsigned                stamp;
 477
 478         u8                      qh_state;
 479 #define QH_STATE_LINKED         1               /* HC sees this */
 480 #define QH_STATE_UNLINK         2               /* HC may still see this */
 481 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 482 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 483 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 484
 485         /* periodic schedule info */
 486         u8                      usecs;          /* intr bandwidth */
 487         u8                      gap_uf;         /* uframes split/csplit gap */
 488         u8                      c_usecs;        /* ... split completion bw */
 489         unsigned short          period;         /* polling interval */
 490         unsigned short          start;          /* where polling starts */
 491 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 492         struct usb_device       *dev;           /* access to TT */
 493 } __attribute__ ((aligned (32)));
 494
 495 /*-------------------------------------------------------------------------*/
 496
 497 /* description of one iso transaction (up to 3 KB data if highspeed) */
 498 struct ehci_iso_packet {
 499         /* These will be copied to iTD when scheduling */
 500         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 501         __le32                  transaction;    /* itd->hw_transaction[i] |= */
 502         u8                      cross;          /* buf crosses pages */
 503         /* for full speed OUT splits */
 504         u16                     buf1;
 505 };
 506
 507 /* temporary schedule data for packets from iso urbs (both speeds)
 508  * each packet is one logical usb transaction to the device (not TT),
 509  * beginning at stream->next_uframe
 510  */
 511 struct ehci_iso_sched {
 512         struct list_head        td_list;
 513         unsigned                span;
 514         struct ehci_iso_packet  packet [0];
 515 };
 516
 517 /*
 518  * ehci_iso_stream - groups all (s)itds for this endpoint.
 519  * acts like a qh would, if EHCI had them for ISO.
 520  */
 521 struct ehci_iso_stream {
 522         /* first two fields match QH, but info1 == 0 */
 523         __le32                  hw_next;
 524         __le32                  hw_info1;
 525
 526         u32                     refcount;
 527         u8                      bEndpointAddress;
 528         u8                      highspeed;
 529         u16                     depth;          /* depth in uframes */
 530         struct list_head        td_list;        /* queued itds/sitds */
 531         struct list_head        free_list;      /* list of unused itds/sitds */
 532         struct usb_device       *udev;
 533
 534         /* output of (re)scheduling */
 535         unsigned long           start;          /* jiffies */
 536         unsigned long           rescheduled;
 537         int                     next_uframe;
 538         __le32                  splits;
 539
 540         /* the rest is derived from the endpoint descriptor,
 541          * trusting urb->interval == f(epdesc->bInterval) and
 542          * including the extra info for hw_bufp[0..2]
 543          */
 544         u8                      interval;
 545         u8                      usecs, c_usecs;
 546         u16                     maxp;
 547         u16                     raw_mask;
 548         unsigned                bandwidth;
 549
 550         /* This is used to initialize iTD's hw_bufp fields */
 551         __le32                  buf0;
 552         __le32                  buf1;
 553         __le32                  buf2;
 554
 555         /* this is used to initialize sITD's tt info */
 556         __le32                  address;
 557 };
 558
 559 /*-------------------------------------------------------------------------*/
 560
 561 /*
 562  * EHCI Specification 0.95 Section 3.3
 563  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 564  *
 565  * Schedule records for high speed iso xfers
 566  */
 567 struct ehci_itd {
 568         /* first part defined by EHCI spec */
 569         __le32                  hw_next;           /* see EHCI 3.3.1 */
 570         __le32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 571 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 572 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 573 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 574 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 575 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 576 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 577
 578 #define ITD_ACTIVE      __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
 579
 580         __le32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 581         __le32                  hw_bufp_hi [7]; /* Appendix B */
 582
 583         /* the rest is HCD-private */
 584         dma_addr_t              itd_dma;        /* for this itd */
 585         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 586
 587         struct urb              *urb;
 588         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 589         struct list_head        itd_list;       /* list of stream's itds */
 590
 591         /* any/all hw_transactions here may be used by that urb */
 592         unsigned                frame;          /* where scheduled */
 593         unsigned                pg;
 594         unsigned                index[8];       /* in urb->iso_frame_desc */
 595         u8                      usecs[8];
 596 } __attribute__ ((aligned (32)));
 597
 598 /*-------------------------------------------------------------------------*/
 599
 600 /*
 601  * EHCI Specification 0.95 Section 3.4
 602  * siTD, aka split-transaction isochronous Transfer Descriptor
 603  *       ... describe full speed iso xfers through TT in hubs
 604  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 605  */
 606 struct ehci_sitd {
 607         /* first part defined by EHCI spec */
 608         __le32                  hw_next;
 609 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 610         __le32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 611         __le32                  hw_uframe;              /* EHCI table 3-10 */
 612         __le32                  hw_results;             /* EHCI table 3-11 */
 613 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 614 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 615 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 616 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 617 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 618 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 619 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 620 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 621 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 622 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 623
 624 #define SITD_ACTIVE     __constant_cpu_to_le32(SITD_STS_ACTIVE)
 625
 626         __le32                  hw_buf [2];             /* EHCI table 3-12 */
 627         __le32                  hw_backpointer;         /* EHCI table 3-13 */
 628         __le32                  hw_buf_hi [2];          /* Appendix B */
 629
 630         /* the rest is HCD-private */
 631         dma_addr_t              sitd_dma;
 632         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 633
 634         struct urb              *urb;
 635         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 636         struct list_head        sitd_list;      /* list of stream's sitds */
 637         unsigned                frame;
 638         unsigned                index;
 639 } __attribute__ ((aligned (32)));
 640
 641 /*-------------------------------------------------------------------------*/
 642
 643 /*
 644  * EHCI Specification 0.96 Section 3.7
 645  * Periodic Frame Span Traversal Node (FSTN)
 646  *
 647  * Manages split interrupt transactions (using TT) that span frame boundaries
 648  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 649  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 650  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 651  */
 652 struct ehci_fstn {
 653         __le32                  hw_next;        /* any periodic q entry */
 654         __le32                  hw_prev;        /* qh or EHCI_LIST_END */
 655
 656         /* the rest is HCD-private */
 657         dma_addr_t              fstn_dma;
 658         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 659 } __attribute__ ((aligned (32)));
 660
 661 /*-------------------------------------------------------------------------*/
 662
 663 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 664
 665 /*
 666  * Some EHCI controllers have a Transaction Translator built into the
 667  * root hub. This is a non-standard feature.  Each controller will need
 668  * to add code to the following inline functions, and call them as
 669  * needed (mostly in root hub code).
 670  */
 671
 672 #define ehci_is_ARC(e)                  ((e)->is_arc_rh_tt)
 673
 674 /* Returns the speed of a device attached to a port on the root hub. */
 675 static inline unsigned int
 676 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 677 {
 678 #ifndef CONFIG_ARCH_MOXACPU     // add by Victor Yu. 01-03-2006
 679         if (ehci_is_ARC(ehci)) {
 680                 switch ((portsc>>26)&3) {
 681                 case 0:
 682                         return 0;
 683                 case 1:
 684                         return (1<<USB_PORT_FEAT_LOWSPEED);
 685                 case 2:
 686                 default:
 687                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 688                 }
 689         }
 690         return (1<<USB_PORT_FEAT_HIGHSPEED);
 691 #else
 692         switch ( readl(&ehci->regs->bus_mon) & HOST_SPEED_MASK ) {
 693         case HOST_SPEED_FS :
 694                 return 0;
 695         case HOST_SPEED_LS :
 696                 return (1<<USB_PORT_FEAT_LOWSPEED);
 697         case HOST_SPEED_HS :
 698         default :
 699                 return (1<<USB_PORT_FEAT_HIGHSPEED);
 700         }
 701         return (1<<USB_PORT_FEAT_HIGHSPEED);
 702 #endif
 703 }
 704
 705 #else
 706
 707 #define ehci_is_ARC(e)                  (0)
 708
 709 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 710 #endif
 711
 712 /*-------------------------------------------------------------------------*/
 713
 714 #ifndef DEBUG
 715 #define STUB_DEBUG_FILES
 716 #endif  /* DEBUG */
 717
 718 /*-------------------------------------------------------------------------*/
 719
 720 #endif /* __LINUX_EHCI_HCD_H */