2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
81 * We suspect that on some hardware no TX done interrupts are generated.
82 * This means recovery from netif_stop_queue only happens if the hw timer
83 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
84 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
85 * If your hardware reliably generates tx done interrupts, then you can remove
86 * DEV_NEED_TIMERIRQ from the driver_data flags.
87 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
88 * superfluous timer interrupts from the nic.
90 #define FORCEDETH_VERSION "0.29"
91 #define DRV_NAME "forcedeth"
93 #include <linux/module.h>
94 #include <linux/types.h>
95 #include <linux/pci.h>
96 #include <linux/interrupt.h>
97 #include <linux/netdevice.h>
98 #include <linux/etherdevice.h>
99 #include <linux/delay.h>
100 #include <linux/spinlock.h>
101 #include <linux/ethtool.h>
102 #include <linux/timer.h>
103 #include <linux/skbuff.h>
104 #include <linux/mii.h>
105 #include <linux/random.h>
106 #include <linux/init.h>
110 #include <asm/uaccess.h>
111 #include <asm/system.h>
114 #define dprintk printk
116 #define dprintk(x...) do { } while (0)
124 #define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
125 #define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
126 #define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
127 #define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
128 #define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
131 NvRegIrqStatus
= 0x000,
132 #define NVREG_IRQSTAT_MIIEVENT 0x040
133 #define NVREG_IRQSTAT_MASK 0x1ff
134 NvRegIrqMask
= 0x004,
135 #define NVREG_IRQ_RX_ERROR 0x0001
136 #define NVREG_IRQ_RX 0x0002
137 #define NVREG_IRQ_RX_NOBUF 0x0004
138 #define NVREG_IRQ_TX_ERR 0x0008
139 #define NVREG_IRQ_TX2 0x0010
140 #define NVREG_IRQ_TIMER 0x0020
141 #define NVREG_IRQ_LINK 0x0040
142 #define NVREG_IRQ_TX1 0x0100
143 #define NVREG_IRQMASK_WANTED_1 0x005f
144 #define NVREG_IRQMASK_WANTED_2 0x0147
145 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
147 NvRegUnknownSetupReg6
= 0x008,
148 #define NVREG_UNKSETUP6_VAL 3
151 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
152 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
154 NvRegPollingInterval
= 0x00c,
155 #define NVREG_POLL_DEFAULT 970
157 #define NVREG_MISC1_HD 0x02
158 #define NVREG_MISC1_FORCE 0x3b0f3c
160 NvRegTransmitterControl
= 0x084,
161 #define NVREG_XMITCTL_START 0x01
162 NvRegTransmitterStatus
= 0x088,
163 #define NVREG_XMITSTAT_BUSY 0x01
165 NvRegPacketFilterFlags
= 0x8c,
166 #define NVREG_PFF_ALWAYS 0x7F0008
167 #define NVREG_PFF_PROMISC 0x80
168 #define NVREG_PFF_MYADDR 0x20
170 NvRegOffloadConfig
= 0x90,
171 #define NVREG_OFFLOAD_HOMEPHY 0x601
172 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
173 NvRegReceiverControl
= 0x094,
174 #define NVREG_RCVCTL_START 0x01
175 NvRegReceiverStatus
= 0x98,
176 #define NVREG_RCVSTAT_BUSY 0x01
178 NvRegRandomSeed
= 0x9c,
179 #define NVREG_RNDSEED_MASK 0x00ff
180 #define NVREG_RNDSEED_FORCE 0x7f00
181 #define NVREG_RNDSEED_FORCE2 0x2d00
182 #define NVREG_RNDSEED_FORCE3 0x7400
184 NvRegUnknownSetupReg1
= 0xA0,
185 #define NVREG_UNKSETUP1_VAL 0x16070f
186 NvRegUnknownSetupReg2
= 0xA4,
187 #define NVREG_UNKSETUP2_VAL 0x16
188 NvRegMacAddrA
= 0xA8,
189 NvRegMacAddrB
= 0xAC,
190 NvRegMulticastAddrA
= 0xB0,
191 #define NVREG_MCASTADDRA_FORCE 0x01
192 NvRegMulticastAddrB
= 0xB4,
193 NvRegMulticastMaskA
= 0xB8,
194 NvRegMulticastMaskB
= 0xBC,
196 NvRegPhyInterface
= 0xC0,
197 #define PHY_RGMII 0x10000000
199 NvRegTxRingPhysAddr
= 0x100,
200 NvRegRxRingPhysAddr
= 0x104,
201 NvRegRingSizes
= 0x108,
202 #define NVREG_RINGSZ_TXSHIFT 0
203 #define NVREG_RINGSZ_RXSHIFT 16
204 NvRegUnknownTransmitterReg
= 0x10c,
205 NvRegLinkSpeed
= 0x110,
206 #define NVREG_LINKSPEED_FORCE 0x10000
207 #define NVREG_LINKSPEED_10 1000
208 #define NVREG_LINKSPEED_100 100
209 #define NVREG_LINKSPEED_1000 50
210 NvRegUnknownSetupReg5
= 0x130,
211 #define NVREG_UNKSETUP5_BIT31 (1<<31)
212 NvRegUnknownSetupReg3
= 0x13c,
213 #define NVREG_UNKSETUP3_VAL1 0x200010
214 NvRegTxRxControl
= 0x144,
215 #define NVREG_TXRXCTL_KICK 0x0001
216 #define NVREG_TXRXCTL_BIT1 0x0002
217 #define NVREG_TXRXCTL_BIT2 0x0004
218 #define NVREG_TXRXCTL_IDLE 0x0008
219 #define NVREG_TXRXCTL_RESET 0x0010
220 NvRegMIIStatus
= 0x180,
221 #define NVREG_MIISTAT_ERROR 0x0001
222 #define NVREG_MIISTAT_LINKCHANGE 0x0008
223 #define NVREG_MIISTAT_MASK 0x000f
224 #define NVREG_MIISTAT_MASK2 0x000f
225 NvRegUnknownSetupReg4
= 0x184,
226 #define NVREG_UNKSETUP4_VAL 8
228 NvRegAdapterControl
= 0x188,
229 #define NVREG_ADAPTCTL_START 0x02
230 #define NVREG_ADAPTCTL_LINKUP 0x04
231 #define NVREG_ADAPTCTL_PHYVALID 0x40000
232 #define NVREG_ADAPTCTL_RUNNING 0x100000
233 #define NVREG_ADAPTCTL_PHYSHIFT 24
234 NvRegMIISpeed
= 0x18c,
235 #define NVREG_MIISPEED_BIT8 (1<<8)
236 #define NVREG_MIIDELAY 5
237 NvRegMIIControl
= 0x190,
238 #define NVREG_MIICTL_INUSE 0x08000
239 #define NVREG_MIICTL_WRITE 0x00400
240 #define NVREG_MIICTL_ADDRSHIFT 5
241 NvRegMIIData
= 0x194,
242 NvRegWakeUpFlags
= 0x200,
243 #define NVREG_WAKEUPFLAGS_VAL 0x7770
244 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
245 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
246 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
247 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
248 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
249 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
250 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
251 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
252 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
253 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
255 NvRegPatternCRC
= 0x204,
256 NvRegPatternMask
= 0x208,
257 NvRegPowerCap
= 0x268,
258 #define NVREG_POWERCAP_D3SUPP (1<<30)
259 #define NVREG_POWERCAP_D2SUPP (1<<26)
260 #define NVREG_POWERCAP_D1SUPP (1<<25)
261 NvRegPowerState
= 0x26c,
262 #define NVREG_POWERSTATE_POWEREDUP 0x8000
263 #define NVREG_POWERSTATE_VALID 0x0100
264 #define NVREG_POWERSTATE_MASK 0x0003
265 #define NVREG_POWERSTATE_D0 0x0000
266 #define NVREG_POWERSTATE_D1 0x0001
267 #define NVREG_POWERSTATE_D2 0x0002
268 #define NVREG_POWERSTATE_D3 0x0003
271 /* Big endian: should work, but is untested */
277 #define FLAG_MASK_V1 0xffff0000
278 #define FLAG_MASK_V2 0xffffc000
279 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
280 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
282 #define NV_TX_LASTPACKET (1<<16)
283 #define NV_TX_RETRYERROR (1<<19)
284 #define NV_TX_LASTPACKET1 (1<<24)
285 #define NV_TX_DEFERRED (1<<26)
286 #define NV_TX_CARRIERLOST (1<<27)
287 #define NV_TX_LATECOLLISION (1<<28)
288 #define NV_TX_UNDERFLOW (1<<29)
289 #define NV_TX_ERROR (1<<30)
290 #define NV_TX_VALID (1<<31)
292 #define NV_TX2_LASTPACKET (1<<29)
293 #define NV_TX2_RETRYERROR (1<<18)
294 #define NV_TX2_LASTPACKET1 (1<<23)
295 #define NV_TX2_DEFERRED (1<<25)
296 #define NV_TX2_CARRIERLOST (1<<26)
297 #define NV_TX2_LATECOLLISION (1<<27)
298 #define NV_TX2_UNDERFLOW (1<<28)
299 /* error and valid are the same for both */
300 #define NV_TX2_ERROR (1<<30)
301 #define NV_TX2_VALID (1<<31)
303 #define NV_RX_DESCRIPTORVALID (1<<16)
304 #define NV_RX_MISSEDFRAME (1<<17)
305 #define NV_RX_SUBSTRACT1 (1<<18)
306 #define NV_RX_ERROR1 (1<<23)
307 #define NV_RX_ERROR2 (1<<24)
308 #define NV_RX_ERROR3 (1<<25)
309 #define NV_RX_ERROR4 (1<<26)
310 #define NV_RX_CRCERR (1<<27)
311 #define NV_RX_OVERFLOW (1<<28)
312 #define NV_RX_FRAMINGERR (1<<29)
313 #define NV_RX_ERROR (1<<30)
314 #define NV_RX_AVAIL (1<<31)
316 #define NV_RX2_DESCRIPTORVALID (1<<29)
317 #define NV_RX2_SUBSTRACT1 (1<<25)
318 #define NV_RX2_ERROR1 (1<<18)
319 #define NV_RX2_ERROR2 (1<<19)
320 #define NV_RX2_ERROR3 (1<<20)
321 #define NV_RX2_ERROR4 (1<<21)
322 #define NV_RX2_CRCERR (1<<22)
323 #define NV_RX2_OVERFLOW (1<<23)
324 #define NV_RX2_FRAMINGERR (1<<24)
325 /* error and avail are the same for both */
326 #define NV_RX2_ERROR (1<<30)
327 #define NV_RX2_AVAIL (1<<31)
329 /* Miscelaneous hardware related defines: */
330 #define NV_PCI_REGSZ 0x270
332 /* various timeout delays: all in usec */
333 #define NV_TXRX_RESET_DELAY 4
334 #define NV_TXSTOP_DELAY1 10
335 #define NV_TXSTOP_DELAY1MAX 500000
336 #define NV_TXSTOP_DELAY2 100
337 #define NV_RXSTOP_DELAY1 10
338 #define NV_RXSTOP_DELAY1MAX 500000
339 #define NV_RXSTOP_DELAY2 100
340 #define NV_SETUP5_DELAY 5
341 #define NV_SETUP5_DELAYMAX 50000
342 #define NV_POWERUP_DELAY 5
343 #define NV_POWERUP_DELAYMAX 5000
344 #define NV_MIIBUSY_DELAY 50
345 #define NV_MIIPHY_DELAY 10
346 #define NV_MIIPHY_DELAYMAX 10000
348 #define NV_WAKEUPPATTERNS 5
349 #define NV_WAKEUPMASKENTRIES 4
351 /* General driver defaults */
352 #define NV_WATCHDOG_TIMEO (5*HZ)
357 * If your nic mysteriously hangs then try to reduce the limits
358 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
359 * last valid ring entry. But this would be impossible to
360 * implement - probably a disassembly error.
362 #define TX_LIMIT_STOP 63
363 #define TX_LIMIT_START 62
365 /* rx/tx mac addr + type + vlan + align + slack*/
366 #define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
367 /* even more slack */
368 #define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
370 #define OOM_REFILL (1+HZ/20)
371 #define POLL_WAIT (1+HZ/100)
372 #define LINK_TIMEOUT (3*HZ)
374 #define DESC_VER_1 0x0
375 #define DESC_VER_2 0x02100
378 #define PHY_OUI_MARVELL 0x5043
379 #define PHY_OUI_CICADA 0x03f1
380 #define PHYID1_OUI_MASK 0x03ff
381 #define PHYID1_OUI_SHFT 6
382 #define PHYID2_OUI_MASK 0xfc00
383 #define PHYID2_OUI_SHFT 10
384 #define PHY_INIT1 0x0f000
385 #define PHY_INIT2 0x0e00
386 #define PHY_INIT3 0x01000
387 #define PHY_INIT4 0x0200
388 #define PHY_INIT5 0x0004
389 #define PHY_INIT6 0x02000
390 #define PHY_GIGABIT 0x0100
392 #define PHY_TIMEOUT 0x1
393 #define PHY_ERROR 0x2
397 #define PHY_HALF 0x100
399 /* FIXME: MII defines that should be added to <linux/mii.h> */
400 #define MII_1000BT_CR 0x09
401 #define MII_1000BT_SR 0x0a
402 #define ADVERTISE_1000FULL 0x0200
403 #define ADVERTISE_1000HALF 0x0100
404 #define LPA_1000FULL 0x0800
405 #define LPA_1000HALF 0x0400
410 * All hardware access under dev->priv->lock, except the performance
412 * - rx is (pseudo-) lockless: it relies on the single-threading provided
413 * by the arch code for interrupts.
414 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
415 * needs dev->priv->lock :-(
416 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
419 /* in dev: base, irq */
424 * Locking: spin_lock(&np->lock); */
425 struct net_device_stats stats
;
431 unsigned int phy_oui
;
434 /* General data: RO fields */
435 dma_addr_t ring_addr
;
436 struct pci_dev
*pci_dev
;
441 /* rx specific fields.
442 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
444 struct ring_desc
*rx_ring
;
445 unsigned int cur_rx
, refill_rx
;
446 struct sk_buff
*rx_skbuff
[RX_RING
];
447 dma_addr_t rx_dma
[RX_RING
];
448 unsigned int rx_buf_sz
;
449 struct timer_list oom_kick
;
450 struct timer_list nic_poll
;
452 /* media detection workaround.
453 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
456 unsigned long link_timeout
;
458 * tx specific fields.
460 struct ring_desc
*tx_ring
;
461 unsigned int next_tx
, nic_tx
;
462 struct sk_buff
*tx_skbuff
[TX_RING
];
463 dma_addr_t tx_dma
[TX_RING
];
468 * Maximum number of loops until we assume that a bit in the irq mask
469 * is stuck. Overridable with module param.
471 static int max_interrupt_work
= 5;
473 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
475 return (struct fe_priv
*) dev
->priv
;
478 static inline u8
*get_hwbase(struct net_device
*dev
)
480 return (u8
*) dev
->base_addr
;
483 static inline void pci_push(u8
* base
)
485 /* force out pending posted writes */
489 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
491 return le32_to_cpu(prd
->FlagLen
)
492 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
495 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
496 int delay
, int delaymax
, const char *msg
)
498 u8
*base
= get_hwbase(dev
);
509 } while ((readl(base
+ offset
) & mask
) != target
);
513 #define MII_READ (-1)
514 /* mii_rw: read/write a register on the PHY.
516 * Caller must guarantee serialization
518 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
520 u8
*base
= get_hwbase(dev
);
524 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
526 reg
= readl(base
+ NvRegMIIControl
);
527 if (reg
& NVREG_MIICTL_INUSE
) {
528 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
529 udelay(NV_MIIBUSY_DELAY
);
532 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
533 if (value
!= MII_READ
) {
534 writel(value
, base
+ NvRegMIIData
);
535 reg
|= NVREG_MIICTL_WRITE
;
537 writel(reg
, base
+ NvRegMIIControl
);
539 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
540 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
541 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
542 dev
->name
, miireg
, addr
);
544 } else if (value
!= MII_READ
) {
545 /* it was a write operation - fewer failures are detectable */
546 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
547 dev
->name
, value
, miireg
, addr
);
549 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
550 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
551 dev
->name
, miireg
, addr
);
554 retval
= readl(base
+ NvRegMIIData
);
555 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
556 dev
->name
, miireg
, addr
, retval
);
562 static int phy_reset(struct net_device
*dev
)
564 struct fe_priv
*np
= get_nvpriv(dev
);
566 unsigned int tries
= 0;
568 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
569 miicontrol
|= BMCR_RESET
;
570 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
577 /* must wait till reset is deasserted */
578 while (miicontrol
& BMCR_RESET
) {
580 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
581 /* FIXME: 100 tries seem excessive */
588 static int phy_init(struct net_device
*dev
)
590 struct fe_priv
*np
= get_nvpriv(dev
);
591 u8
*base
= get_hwbase(dev
);
592 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
594 /* set advertise register */
595 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
596 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|0x800|0x400);
597 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
598 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
602 /* get phy interface type */
603 phyinterface
= readl(base
+ NvRegPhyInterface
);
605 /* see if gigabit phy */
606 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
607 if (mii_status
& PHY_GIGABIT
) {
608 np
->gigabit
= PHY_GIGABIT
;
609 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
610 mii_control_1000
&= ~ADVERTISE_1000HALF
;
611 if (phyinterface
& PHY_RGMII
)
612 mii_control_1000
|= ADVERTISE_1000FULL
;
614 mii_control_1000
&= ~ADVERTISE_1000FULL
;
616 if (mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, mii_control_1000
)) {
617 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
625 if (phy_reset(dev
)) {
626 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
630 /* phy vendor specific configuration */
631 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
632 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
633 phy_reserved
&= ~(PHY_INIT1
| PHY_INIT2
);
634 phy_reserved
|= (PHY_INIT3
| PHY_INIT4
);
635 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
636 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
639 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
640 phy_reserved
|= PHY_INIT5
;
641 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
642 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
646 if (np
->phy_oui
== PHY_OUI_CICADA
) {
647 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
648 phy_reserved
|= PHY_INIT6
;
649 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
650 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
655 /* restart auto negotiation */
656 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
657 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
658 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
665 static void nv_start_rx(struct net_device
*dev
)
667 struct fe_priv
*np
= get_nvpriv(dev
);
668 u8
*base
= get_hwbase(dev
);
670 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
671 /* Already running? Stop it. */
672 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
673 writel(0, base
+ NvRegReceiverControl
);
676 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
678 writel(NVREG_RCVCTL_START
, base
+ NvRegReceiverControl
);
679 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
680 dev
->name
, np
->duplex
, np
->linkspeed
);
684 static void nv_stop_rx(struct net_device
*dev
)
686 u8
*base
= get_hwbase(dev
);
688 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
689 writel(0, base
+ NvRegReceiverControl
);
690 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
691 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
692 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
694 udelay(NV_RXSTOP_DELAY2
);
695 writel(0, base
+ NvRegLinkSpeed
);
698 static void nv_start_tx(struct net_device
*dev
)
700 u8
*base
= get_hwbase(dev
);
702 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
703 writel(NVREG_XMITCTL_START
, base
+ NvRegTransmitterControl
);
707 static void nv_stop_tx(struct net_device
*dev
)
709 u8
*base
= get_hwbase(dev
);
711 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
712 writel(0, base
+ NvRegTransmitterControl
);
713 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
714 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
715 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
717 udelay(NV_TXSTOP_DELAY2
);
718 writel(0, base
+ NvRegUnknownTransmitterReg
);
721 static void nv_txrx_reset(struct net_device
*dev
)
723 struct fe_priv
*np
= get_nvpriv(dev
);
724 u8
*base
= get_hwbase(dev
);
726 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
727 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->desc_ver
, base
+ NvRegTxRxControl
);
729 udelay(NV_TXRX_RESET_DELAY
);
730 writel(NVREG_TXRXCTL_BIT2
| np
->desc_ver
, base
+ NvRegTxRxControl
);
735 * nv_get_stats: dev->get_stats function
736 * Get latest stats value from the nic.
737 * Called with read_lock(&dev_base_lock) held for read -
738 * only synchronized against unregister_netdevice.
740 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
742 struct fe_priv
*np
= get_nvpriv(dev
);
744 /* It seems that the nic always generates interrupts and doesn't
745 * accumulate errors internally. Thus the current values in np->stats
746 * are already up to date.
751 static int nv_ethtool_ioctl(struct net_device
*dev
, void __user
*useraddr
)
753 struct fe_priv
*np
= get_nvpriv(dev
);
754 u8
*base
= get_hwbase(dev
);
757 if (copy_from_user(ðcmd
, useraddr
, sizeof (ethcmd
)))
761 case ETHTOOL_GDRVINFO
:
763 struct ethtool_drvinfo info
= { ETHTOOL_GDRVINFO
};
764 strcpy(info
.driver
, "forcedeth");
765 strcpy(info
.version
, FORCEDETH_VERSION
);
766 strcpy(info
.bus_info
, pci_name(np
->pci_dev
));
767 if (copy_to_user(useraddr
, &info
, sizeof (info
)))
773 struct ethtool_value edata
= { ETHTOOL_GLINK
};
775 edata
.data
= !!netif_carrier_ok(dev
);
777 if (copy_to_user(useraddr
, &edata
, sizeof(edata
)))
783 struct ethtool_wolinfo wolinfo
;
784 memset(&wolinfo
, 0, sizeof(wolinfo
));
785 wolinfo
.supported
= WAKE_MAGIC
;
787 spin_lock_irq(&np
->lock
);
789 wolinfo
.wolopts
= WAKE_MAGIC
;
790 spin_unlock_irq(&np
->lock
);
792 if (copy_to_user(useraddr
, &wolinfo
, sizeof(wolinfo
)))
798 struct ethtool_wolinfo wolinfo
;
799 if (copy_from_user(&wolinfo
, useraddr
, sizeof(wolinfo
)))
802 spin_lock_irq(&np
->lock
);
803 if (wolinfo
.wolopts
== 0) {
804 writel(0, base
+ NvRegWakeUpFlags
);
807 if (wolinfo
.wolopts
& WAKE_MAGIC
) {
808 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
811 spin_unlock_irq(&np
->lock
);
822 * nv_ioctl: dev->do_ioctl function
823 * Called with rtnl_lock held.
825 static int nv_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
829 return nv_ethtool_ioctl(dev
, rq
->ifr_data
);
837 * nv_alloc_rx: fill rx ring entries.
838 * Return 1 if the allocations for the skbs failed and the
839 * rx engine is without Available descriptors
841 static int nv_alloc_rx(struct net_device
*dev
)
843 struct fe_priv
*np
= get_nvpriv(dev
);
844 unsigned int refill_rx
= np
->refill_rx
;
847 while (np
->cur_rx
!= refill_rx
) {
850 nr
= refill_rx
% RX_RING
;
851 if (np
->rx_skbuff
[nr
] == NULL
) {
853 skb
= dev_alloc_skb(RX_ALLOC_BUFSIZE
);
858 np
->rx_skbuff
[nr
] = skb
;
860 skb
= np
->rx_skbuff
[nr
];
862 np
->rx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
, skb
->len
,
864 np
->rx_ring
[nr
].PacketBuffer
= cpu_to_le32(np
->rx_dma
[nr
]);
866 np
->rx_ring
[nr
].FlagLen
= cpu_to_le32(RX_NIC_BUFSIZE
| NV_RX_AVAIL
);
867 dprintk(KERN_DEBUG
"%s: nv_alloc_rx: Packet %d marked as Available\n",
868 dev
->name
, refill_rx
);
871 np
->refill_rx
= refill_rx
;
872 if (np
->cur_rx
- refill_rx
== RX_RING
)
877 static void nv_do_rx_refill(unsigned long data
)
879 struct net_device
*dev
= (struct net_device
*) data
;
880 struct fe_priv
*np
= get_nvpriv(dev
);
882 disable_irq(dev
->irq
);
883 if (nv_alloc_rx(dev
)) {
884 spin_lock(&np
->lock
);
885 if (!np
->in_shutdown
)
886 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
887 spin_unlock(&np
->lock
);
889 enable_irq(dev
->irq
);
892 static int nv_init_ring(struct net_device
*dev
)
894 struct fe_priv
*np
= get_nvpriv(dev
);
897 np
->next_tx
= np
->nic_tx
= 0;
898 for (i
= 0; i
< TX_RING
; i
++)
899 np
->tx_ring
[i
].FlagLen
= 0;
901 np
->cur_rx
= RX_RING
;
903 for (i
= 0; i
< RX_RING
; i
++)
904 np
->rx_ring
[i
].FlagLen
= 0;
905 return nv_alloc_rx(dev
);
908 static void nv_drain_tx(struct net_device
*dev
)
910 struct fe_priv
*np
= get_nvpriv(dev
);
912 for (i
= 0; i
< TX_RING
; i
++) {
913 np
->tx_ring
[i
].FlagLen
= 0;
914 if (np
->tx_skbuff
[i
]) {
915 pci_unmap_single(np
->pci_dev
, np
->tx_dma
[i
],
916 np
->tx_skbuff
[i
]->len
,
918 dev_kfree_skb(np
->tx_skbuff
[i
]);
919 np
->tx_skbuff
[i
] = NULL
;
920 np
->stats
.tx_dropped
++;
925 static void nv_drain_rx(struct net_device
*dev
)
927 struct fe_priv
*np
= get_nvpriv(dev
);
929 for (i
= 0; i
< RX_RING
; i
++) {
930 np
->rx_ring
[i
].FlagLen
= 0;
932 if (np
->rx_skbuff
[i
]) {
933 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
934 np
->rx_skbuff
[i
]->len
,
936 dev_kfree_skb(np
->rx_skbuff
[i
]);
937 np
->rx_skbuff
[i
] = NULL
;
942 static void drain_ring(struct net_device
*dev
)
949 * nv_start_xmit: dev->hard_start_xmit function
950 * Called with dev->xmit_lock held.
952 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
954 struct fe_priv
*np
= get_nvpriv(dev
);
955 int nr
= np
->next_tx
% TX_RING
;
957 np
->tx_skbuff
[nr
] = skb
;
958 np
->tx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
,skb
->len
,
961 np
->tx_ring
[nr
].PacketBuffer
= cpu_to_le32(np
->tx_dma
[nr
]);
963 spin_lock_irq(&np
->lock
);
965 np
->tx_ring
[nr
].FlagLen
= cpu_to_le32( (skb
->len
-1) | np
->tx_flags
);
966 dprintk(KERN_DEBUG
"%s: nv_start_xmit: packet packet %d queued for transmission.\n",
967 dev
->name
, np
->next_tx
);
970 for (j
=0; j
<64; j
++) {
972 dprintk("\n%03x:", j
);
973 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
980 dev
->trans_start
= jiffies
;
981 if (np
->next_tx
- np
->nic_tx
>= TX_LIMIT_STOP
)
982 netif_stop_queue(dev
);
983 spin_unlock_irq(&np
->lock
);
984 writel(NVREG_TXRXCTL_KICK
|np
->desc_ver
, get_hwbase(dev
) + NvRegTxRxControl
);
985 pci_push(get_hwbase(dev
));
990 * nv_tx_done: check for completed packets, release the skbs.
992 * Caller must own np->lock.
994 static void nv_tx_done(struct net_device
*dev
)
996 struct fe_priv
*np
= get_nvpriv(dev
);
1000 while (np
->nic_tx
!= np
->next_tx
) {
1001 i
= np
->nic_tx
% TX_RING
;
1003 Flags
= le32_to_cpu(np
->tx_ring
[i
].FlagLen
);
1005 dprintk(KERN_DEBUG
"%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1006 dev
->name
, np
->nic_tx
, Flags
);
1007 if (Flags
& NV_TX_VALID
)
1009 if (np
->desc_ver
== DESC_VER_1
) {
1010 if (Flags
& (NV_TX_RETRYERROR
|NV_TX_CARRIERLOST
|NV_TX_LATECOLLISION
|
1011 NV_TX_UNDERFLOW
|NV_TX_ERROR
)) {
1012 if (Flags
& NV_TX_UNDERFLOW
)
1013 np
->stats
.tx_fifo_errors
++;
1014 if (Flags
& NV_TX_CARRIERLOST
)
1015 np
->stats
.tx_carrier_errors
++;
1016 np
->stats
.tx_errors
++;
1018 np
->stats
.tx_packets
++;
1019 np
->stats
.tx_bytes
+= np
->tx_skbuff
[i
]->len
;
1022 if (Flags
& (NV_TX2_RETRYERROR
|NV_TX2_CARRIERLOST
|NV_TX2_LATECOLLISION
|
1023 NV_TX2_UNDERFLOW
|NV_TX2_ERROR
)) {
1024 if (Flags
& NV_TX2_UNDERFLOW
)
1025 np
->stats
.tx_fifo_errors
++;
1026 if (Flags
& NV_TX2_CARRIERLOST
)
1027 np
->stats
.tx_carrier_errors
++;
1028 np
->stats
.tx_errors
++;
1030 np
->stats
.tx_packets
++;
1031 np
->stats
.tx_bytes
+= np
->tx_skbuff
[i
]->len
;
1034 pci_unmap_single(np
->pci_dev
, np
->tx_dma
[i
],
1035 np
->tx_skbuff
[i
]->len
,
1037 dev_kfree_skb_irq(np
->tx_skbuff
[i
]);
1038 np
->tx_skbuff
[i
] = NULL
;
1041 if (np
->next_tx
- np
->nic_tx
< TX_LIMIT_START
)
1042 netif_wake_queue(dev
);
1046 * nv_tx_timeout: dev->tx_timeout function
1047 * Called with dev->xmit_lock held.
1049 static void nv_tx_timeout(struct net_device
*dev
)
1051 struct fe_priv
*np
= get_nvpriv(dev
);
1052 u8
*base
= get_hwbase(dev
);
1054 dprintk(KERN_DEBUG
"%s: Got tx_timeout. irq: %08x\n", dev
->name
,
1055 readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
);
1057 spin_lock_irq(&np
->lock
);
1059 /* 1) stop tx engine */
1062 /* 2) check that the packets were not sent already: */
1065 /* 3) if there are dead entries: clear everything */
1066 if (np
->next_tx
!= np
->nic_tx
) {
1067 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
1069 np
->next_tx
= np
->nic_tx
= 0;
1070 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1071 netif_wake_queue(dev
);
1074 /* 4) restart tx engine */
1076 spin_unlock_irq(&np
->lock
);
1079 static void nv_rx_process(struct net_device
*dev
)
1081 struct fe_priv
*np
= get_nvpriv(dev
);
1085 struct sk_buff
*skb
;
1088 if (np
->cur_rx
- np
->refill_rx
>= RX_RING
)
1089 break; /* we scanned the whole ring - do not continue */
1091 i
= np
->cur_rx
% RX_RING
;
1092 Flags
= le32_to_cpu(np
->rx_ring
[i
].FlagLen
);
1093 len
= nv_descr_getlength(&np
->rx_ring
[i
], np
->desc_ver
);
1095 dprintk(KERN_DEBUG
"%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1096 dev
->name
, np
->cur_rx
, Flags
);
1098 if (Flags
& NV_RX_AVAIL
)
1099 break; /* still owned by hardware, */
1102 * the packet is for us - immediately tear down the pci mapping.
1103 * TODO: check if a prefetch of the first cacheline improves
1106 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1107 np
->rx_skbuff
[i
]->len
,
1108 PCI_DMA_FROMDEVICE
);
1112 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",Flags
);
1113 for (j
=0; j
<64; j
++) {
1115 dprintk("\n%03x:", j
);
1116 dprintk(" %02x", ((unsigned char*)np
->rx_skbuff
[i
]->data
)[j
]);
1120 /* look at what we actually got: */
1121 if (np
->desc_ver
== DESC_VER_1
) {
1122 if (!(Flags
& NV_RX_DESCRIPTORVALID
))
1125 if (Flags
& NV_RX_MISSEDFRAME
) {
1126 np
->stats
.rx_missed_errors
++;
1127 np
->stats
.rx_errors
++;
1130 if (Flags
& (NV_RX_ERROR1
|NV_RX_ERROR2
|NV_RX_ERROR3
|NV_RX_ERROR4
)) {
1131 np
->stats
.rx_errors
++;
1134 if (Flags
& NV_RX_CRCERR
) {
1135 np
->stats
.rx_crc_errors
++;
1136 np
->stats
.rx_errors
++;
1139 if (Flags
& NV_RX_OVERFLOW
) {
1140 np
->stats
.rx_over_errors
++;
1141 np
->stats
.rx_errors
++;
1144 if (Flags
& NV_RX_ERROR
) {
1145 /* framing errors are soft errors, the rest is fatal. */
1146 if (Flags
& NV_RX_FRAMINGERR
) {
1147 if (Flags
& NV_RX_SUBSTRACT1
) {
1151 np
->stats
.rx_errors
++;
1156 if (!(Flags
& NV_RX2_DESCRIPTORVALID
))
1159 if (Flags
& (NV_RX2_ERROR1
|NV_RX2_ERROR2
|NV_RX2_ERROR3
|NV_RX2_ERROR4
)) {
1160 np
->stats
.rx_errors
++;
1163 if (Flags
& NV_RX2_CRCERR
) {
1164 np
->stats
.rx_crc_errors
++;
1165 np
->stats
.rx_errors
++;
1168 if (Flags
& NV_RX2_OVERFLOW
) {
1169 np
->stats
.rx_over_errors
++;
1170 np
->stats
.rx_errors
++;
1173 if (Flags
& NV_RX2_ERROR
) {
1174 /* framing errors are soft errors, the rest is fatal. */
1175 if (Flags
& NV_RX2_FRAMINGERR
) {
1176 if (Flags
& NV_RX2_SUBSTRACT1
) {
1180 np
->stats
.rx_errors
++;
1185 /* got a valid packet - forward it to the network core */
1186 skb
= np
->rx_skbuff
[i
];
1187 np
->rx_skbuff
[i
] = NULL
;
1190 skb
->protocol
= eth_type_trans(skb
, dev
);
1191 dprintk(KERN_DEBUG
"%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1192 dev
->name
, np
->cur_rx
, len
, skb
->protocol
);
1194 dev
->last_rx
= jiffies
;
1195 np
->stats
.rx_packets
++;
1196 np
->stats
.rx_bytes
+= len
;
1203 * nv_change_mtu: dev->change_mtu function
1204 * Called with dev_base_lock held for read.
1206 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
1208 if (new_mtu
> ETH_DATA_LEN
)
1215 * nv_set_multicast: dev->set_multicast function
1216 * Called with dev->xmit_lock held.
1218 static void nv_set_multicast(struct net_device
*dev
)
1220 struct fe_priv
*np
= get_nvpriv(dev
);
1221 u8
*base
= get_hwbase(dev
);
1226 memset(addr
, 0, sizeof(addr
));
1227 memset(mask
, 0, sizeof(mask
));
1229 if (dev
->flags
& IFF_PROMISC
) {
1230 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n", dev
->name
);
1231 pff
= NVREG_PFF_PROMISC
;
1233 pff
= NVREG_PFF_MYADDR
;
1235 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
1239 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
1240 if (dev
->flags
& IFF_ALLMULTI
) {
1241 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
1243 struct dev_mc_list
*walk
;
1245 walk
= dev
->mc_list
;
1246 while (walk
!= NULL
) {
1248 a
= le32_to_cpu(*(u32
*) walk
->dmi_addr
);
1249 b
= le16_to_cpu(*(u16
*) (&walk
->dmi_addr
[4]));
1257 addr
[0] = alwaysOn
[0];
1258 addr
[1] = alwaysOn
[1];
1259 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
1260 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
1263 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
1264 pff
|= NVREG_PFF_ALWAYS
;
1265 spin_lock_irq(&np
->lock
);
1267 writel(addr
[0], base
+ NvRegMulticastAddrA
);
1268 writel(addr
[1], base
+ NvRegMulticastAddrB
);
1269 writel(mask
[0], base
+ NvRegMulticastMaskA
);
1270 writel(mask
[1], base
+ NvRegMulticastMaskB
);
1271 writel(pff
, base
+ NvRegPacketFilterFlags
);
1272 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
1275 spin_unlock_irq(&np
->lock
);
1278 static int nv_update_linkspeed(struct net_device
*dev
)
1280 struct fe_priv
*np
= get_nvpriv(dev
);
1281 u8
*base
= get_hwbase(dev
);
1283 int newls
= np
->linkspeed
;
1284 int newdup
= np
->duplex
;
1287 u32 control_1000
, status_1000
, phyreg
;
1289 /* BMSR_LSTATUS is latched, read it twice:
1290 * we want the current value.
1292 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1293 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1295 if (!(mii_status
& BMSR_LSTATUS
)) {
1296 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
1298 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1304 /* check auto negotiation is complete */
1305 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
1306 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1307 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1310 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
1315 if (np
->gigabit
== PHY_GIGABIT
) {
1316 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1317 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_SR
, MII_READ
);
1319 if ((control_1000
& ADVERTISE_1000FULL
) &&
1320 (status_1000
& LPA_1000FULL
)) {
1321 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
1323 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
1329 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1330 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
1331 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1332 dev
->name
, adv
, lpa
);
1334 /* FIXME: handle parallel detection properly */
1336 if (lpa
& LPA_100FULL
) {
1337 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1339 } else if (lpa
& LPA_100HALF
) {
1340 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1342 } else if (lpa
& LPA_10FULL
) {
1343 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1345 } else if (lpa
& LPA_10HALF
) {
1346 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1349 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, lpa
);
1350 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1355 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
1358 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
1359 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
1361 np
->duplex
= newdup
;
1362 np
->linkspeed
= newls
;
1364 if (np
->gigabit
== PHY_GIGABIT
) {
1365 phyreg
= readl(base
+ NvRegRandomSeed
);
1366 phyreg
&= ~(0x3FF00);
1367 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
1368 phyreg
|= NVREG_RNDSEED_FORCE3
;
1369 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
1370 phyreg
|= NVREG_RNDSEED_FORCE2
;
1371 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
1372 phyreg
|= NVREG_RNDSEED_FORCE
;
1373 writel(phyreg
, base
+ NvRegRandomSeed
);
1376 phyreg
= readl(base
+ NvRegPhyInterface
);
1377 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
1378 if (np
->duplex
== 0)
1380 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
1382 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
1384 writel(phyreg
, base
+ NvRegPhyInterface
);
1386 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
1389 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1395 static void nv_linkchange(struct net_device
*dev
)
1397 if (nv_update_linkspeed(dev
)) {
1398 if (netif_carrier_ok(dev
)) {
1401 netif_carrier_on(dev
);
1402 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
1406 if (netif_carrier_ok(dev
)) {
1407 netif_carrier_off(dev
);
1408 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
1414 static void nv_link_irq(struct net_device
*dev
)
1416 u8
*base
= get_hwbase(dev
);
1419 miistat
= readl(base
+ NvRegMIIStatus
);
1420 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
1421 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
1423 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
1425 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
1428 static irqreturn_t
nv_nic_irq(int foo
, void *data
, struct pt_regs
*regs
)
1430 struct net_device
*dev
= (struct net_device
*) data
;
1431 struct fe_priv
*np
= get_nvpriv(dev
);
1432 u8
*base
= get_hwbase(dev
);
1436 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
1439 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1440 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
1442 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
1443 if (!(events
& np
->irqmask
))
1446 if (events
& (NVREG_IRQ_TX1
|NVREG_IRQ_TX2
|NVREG_IRQ_TX_ERR
)) {
1447 spin_lock(&np
->lock
);
1449 spin_unlock(&np
->lock
);
1452 if (events
& (NVREG_IRQ_RX_ERROR
|NVREG_IRQ_RX
|NVREG_IRQ_RX_NOBUF
)) {
1454 if (nv_alloc_rx(dev
)) {
1455 spin_lock(&np
->lock
);
1456 if (!np
->in_shutdown
)
1457 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1458 spin_unlock(&np
->lock
);
1462 if (events
& NVREG_IRQ_LINK
) {
1463 spin_lock(&np
->lock
);
1465 spin_unlock(&np
->lock
);
1467 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
1468 spin_lock(&np
->lock
);
1470 spin_unlock(&np
->lock
);
1471 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
1473 if (events
& (NVREG_IRQ_TX_ERR
)) {
1474 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
1477 if (events
& (NVREG_IRQ_UNKNOWN
)) {
1478 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
1481 if (i
> max_interrupt_work
) {
1482 spin_lock(&np
->lock
);
1483 /* disable interrupts on the nic */
1484 writel(0, base
+ NvRegIrqMask
);
1487 if (!np
->in_shutdown
)
1488 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
1489 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
1490 spin_unlock(&np
->lock
);
1495 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
1497 return IRQ_RETVAL(i
);
1500 static void nv_do_nic_poll(unsigned long data
)
1502 struct net_device
*dev
= (struct net_device
*) data
;
1503 struct fe_priv
*np
= get_nvpriv(dev
);
1504 u8
*base
= get_hwbase(dev
);
1506 disable_irq(dev
->irq
);
1507 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1509 * reenable interrupts on the nic, we have to do this before calling
1510 * nv_nic_irq because that may decide to do otherwise
1512 writel(np
->irqmask
, base
+ NvRegIrqMask
);
1514 nv_nic_irq((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
1515 enable_irq(dev
->irq
);
1518 static int nv_open(struct net_device
*dev
)
1520 struct fe_priv
*np
= get_nvpriv(dev
);
1521 u8
*base
= get_hwbase(dev
);
1524 dprintk(KERN_DEBUG
"nv_open: begin\n");
1526 /* 1) erase previous misconfiguration */
1527 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1528 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
1529 writel(0, base
+ NvRegMulticastAddrB
);
1530 writel(0, base
+ NvRegMulticastMaskA
);
1531 writel(0, base
+ NvRegMulticastMaskB
);
1532 writel(0, base
+ NvRegPacketFilterFlags
);
1534 writel(0, base
+ NvRegTransmitterControl
);
1535 writel(0, base
+ NvRegReceiverControl
);
1537 writel(0, base
+ NvRegAdapterControl
);
1539 /* 2) initialize descriptor rings */
1540 oom
= nv_init_ring(dev
);
1542 writel(0, base
+ NvRegLinkSpeed
);
1543 writel(0, base
+ NvRegUnknownTransmitterReg
);
1545 writel(0, base
+ NvRegUnknownSetupReg6
);
1547 np
->in_shutdown
= 0;
1549 /* 3) set mac address */
1553 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
1554 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
1555 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
1557 writel(mac
[0], base
+ NvRegMacAddrA
);
1558 writel(mac
[1], base
+ NvRegMacAddrB
);
1561 /* 4) give hw rings */
1562 writel((u32
) np
->ring_addr
, base
+ NvRegRxRingPhysAddr
);
1563 writel((u32
) (np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
1564 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
1565 base
+ NvRegRingSizes
);
1567 /* 5) continue setup */
1568 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1571 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1572 writel(NVREG_UNKSETUP3_VAL1
, base
+ NvRegUnknownSetupReg3
);
1573 writel(np
->desc_ver
, base
+ NvRegTxRxControl
);
1575 writel(NVREG_TXRXCTL_BIT1
|np
->desc_ver
, base
+ NvRegTxRxControl
);
1576 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
1577 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
1578 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
1580 writel(0, base
+ NvRegUnknownSetupReg4
);
1581 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
1582 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
1584 /* 6) continue setup */
1585 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
1586 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
1587 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
1588 writel(NVREG_OFFLOAD_NORMAL
, base
+ NvRegOffloadConfig
);
1590 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
1591 get_random_bytes(&i
, sizeof(i
));
1592 writel(NVREG_RNDSEED_FORCE
| (i
&NVREG_RNDSEED_MASK
), base
+ NvRegRandomSeed
);
1593 writel(NVREG_UNKSETUP1_VAL
, base
+ NvRegUnknownSetupReg1
);
1594 writel(NVREG_UNKSETUP2_VAL
, base
+ NvRegUnknownSetupReg2
);
1595 writel(NVREG_POLL_DEFAULT
, base
+ NvRegPollingInterval
);
1596 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
1597 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
1598 base
+ NvRegAdapterControl
);
1599 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
1600 writel(NVREG_UNKSETUP4_VAL
, base
+ NvRegUnknownSetupReg4
);
1601 writel(NVREG_WAKEUPFLAGS_VAL
, base
+ NvRegWakeUpFlags
);
1603 i
= readl(base
+ NvRegPowerState
);
1604 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
1605 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
1609 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
1611 writel(0, base
+ NvRegIrqMask
);
1613 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
1614 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
1617 ret
= request_irq(dev
->irq
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
);
1621 /* ask for interrupts */
1622 writel(np
->irqmask
, base
+ NvRegIrqMask
);
1624 spin_lock_irq(&np
->lock
);
1625 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
1626 writel(0, base
+ NvRegMulticastAddrB
);
1627 writel(0, base
+ NvRegMulticastMaskA
);
1628 writel(0, base
+ NvRegMulticastMaskB
);
1629 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
1630 /* One manual link speed update: Interrupts are enabled, future link
1631 * speed changes cause interrupts and are handled by nv_link_irq().
1635 miistat
= readl(base
+ NvRegMIIStatus
);
1636 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
1637 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
1639 ret
= nv_update_linkspeed(dev
);
1642 netif_start_queue(dev
);
1644 netif_carrier_on(dev
);
1646 printk("%s: no link during initialization.\n", dev
->name
);
1647 netif_carrier_off(dev
);
1650 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1651 spin_unlock_irq(&np
->lock
);
1659 static int nv_close(struct net_device
*dev
)
1661 struct fe_priv
*np
= get_nvpriv(dev
);
1664 spin_lock_irq(&np
->lock
);
1665 np
->in_shutdown
= 1;
1666 spin_unlock_irq(&np
->lock
);
1667 synchronize_irq(dev
->irq
);
1669 del_timer_sync(&np
->oom_kick
);
1670 del_timer_sync(&np
->nic_poll
);
1672 netif_stop_queue(dev
);
1673 spin_lock_irq(&np
->lock
);
1676 base
= get_hwbase(dev
);
1678 /* disable interrupts on the nic or we will lock up */
1679 writel(0, base
+ NvRegIrqMask
);
1681 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
1683 spin_unlock_irq(&np
->lock
);
1685 free_irq(dev
->irq
, dev
);
1692 /* FIXME: power down nic */
1697 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
1699 struct net_device
*dev
;
1705 dev
= alloc_etherdev(sizeof(struct fe_priv
));
1710 np
= get_nvpriv(dev
);
1711 np
->pci_dev
= pci_dev
;
1712 spin_lock_init(&np
->lock
);
1713 SET_MODULE_OWNER(dev
);
1714 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
1716 init_timer(&np
->oom_kick
);
1717 np
->oom_kick
.data
= (unsigned long) dev
;
1718 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
1719 init_timer(&np
->nic_poll
);
1720 np
->nic_poll
.data
= (unsigned long) dev
;
1721 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
1723 err
= pci_enable_device(pci_dev
);
1725 printk(KERN_INFO
"forcedeth: pci_enable_dev failed (%d) for device %s\n",
1726 err
, pci_name(pci_dev
));
1730 pci_set_master(pci_dev
);
1732 err
= pci_request_regions(pci_dev
, DRV_NAME
);
1738 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1739 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
1740 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
1741 pci_resource_len(pci_dev
, i
),
1742 pci_resource_flags(pci_dev
, i
));
1743 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
1744 pci_resource_len(pci_dev
, i
) >= NV_PCI_REGSZ
) {
1745 addr
= pci_resource_start(pci_dev
, i
);
1749 if (i
== DEVICE_COUNT_RESOURCE
) {
1750 printk(KERN_INFO
"forcedeth: Couldn't find register window for device %s.\n",
1755 /* handle different descriptor versions */
1756 if (pci_dev
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_1
||
1757 pci_dev
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_2
||
1758 pci_dev
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_3
)
1759 np
->desc_ver
= DESC_VER_1
;
1761 np
->desc_ver
= DESC_VER_2
;
1764 dev
->base_addr
= (unsigned long) ioremap(addr
, NV_PCI_REGSZ
);
1765 if (!dev
->base_addr
)
1767 dev
->irq
= pci_dev
->irq
;
1768 np
->rx_ring
= pci_alloc_consistent(pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
1772 np
->tx_ring
= &np
->rx_ring
[RX_RING
];
1774 dev
->open
= nv_open
;
1775 dev
->stop
= nv_close
;
1776 dev
->hard_start_xmit
= nv_start_xmit
;
1777 dev
->get_stats
= nv_get_stats
;
1778 dev
->change_mtu
= nv_change_mtu
;
1779 dev
->set_multicast_list
= nv_set_multicast
;
1780 dev
->do_ioctl
= nv_ioctl
;
1781 dev
->tx_timeout
= nv_tx_timeout
;
1782 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
1784 pci_set_drvdata(pci_dev
, dev
);
1786 /* read the mac address */
1787 base
= get_hwbase(dev
);
1788 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
1789 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
1791 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
1792 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
1793 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
1794 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
1795 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
1796 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
1798 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1800 * Bad mac address. At least one bios sets the mac address
1801 * to 01:23:45:67:89:ab
1803 printk(KERN_ERR
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1805 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
1806 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
1807 printk(KERN_ERR
"Please complain to your hardware vendor. Switching to a random MAC.\n");
1808 dev
->dev_addr
[0] = 0x00;
1809 dev
->dev_addr
[1] = 0x00;
1810 dev
->dev_addr
[2] = 0x6c;
1811 get_random_bytes(&dev
->dev_addr
[3], 3);
1814 dprintk(KERN_DEBUG
"%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev
),
1815 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
1816 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
1819 writel(0, base
+ NvRegWakeUpFlags
);
1822 if (np
->desc_ver
== DESC_VER_1
) {
1823 np
->tx_flags
= NV_TX_LASTPACKET
|NV_TX_VALID
;
1824 if (id
->driver_data
& DEV_NEED_LASTPACKET1
)
1825 np
->tx_flags
|= NV_TX_LASTPACKET1
;
1827 np
->tx_flags
= NV_TX2_LASTPACKET
|NV_TX2_VALID
;
1828 if (id
->driver_data
& DEV_NEED_LASTPACKET1
)
1829 np
->tx_flags
|= NV_TX2_LASTPACKET1
;
1831 if (id
->driver_data
& DEV_IRQMASK_1
)
1832 np
->irqmask
= NVREG_IRQMASK_WANTED_1
;
1833 if (id
->driver_data
& DEV_IRQMASK_2
)
1834 np
->irqmask
= NVREG_IRQMASK_WANTED_2
;
1835 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
1836 np
->irqmask
|= NVREG_IRQ_TIMER
;
1837 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
1838 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
1839 np
->need_linktimer
= 1;
1840 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
1842 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
1843 np
->need_linktimer
= 0;
1846 /* find a suitable phy */
1847 for (i
= 1; i
< 32; i
++) {
1850 spin_lock_irq(&np
->lock
);
1851 id1
= mii_rw(dev
, i
, MII_PHYSID1
, MII_READ
);
1852 spin_unlock_irq(&np
->lock
);
1853 if (id1
< 0 || id1
== 0xffff)
1855 spin_lock_irq(&np
->lock
);
1856 id2
= mii_rw(dev
, i
, MII_PHYSID2
, MII_READ
);
1857 spin_unlock_irq(&np
->lock
);
1858 if (id2
< 0 || id2
== 0xffff)
1861 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
1862 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
1863 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
1864 pci_name(pci_dev
), id1
, id2
, i
);
1866 np
->phy_oui
= id1
| id2
;
1870 /* PHY in isolate mode? No phy attached and user wants to
1871 * test loopback? Very odd, but can be correct.
1873 printk(KERN_INFO
"%s: open: Could not find a valid PHY.\n",
1882 err
= register_netdev(dev
);
1884 printk(KERN_INFO
"forcedeth: unable to register netdev: %d\n", err
);
1887 printk(KERN_INFO
"%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
1888 dev
->name
, pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
,
1894 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
1895 np
->rx_ring
, np
->ring_addr
);
1896 pci_set_drvdata(pci_dev
, NULL
);
1898 iounmap(get_hwbase(dev
));
1900 pci_release_regions(pci_dev
);
1902 pci_disable_device(pci_dev
);
1909 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
1911 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
1912 struct fe_priv
*np
= get_nvpriv(dev
);
1913 u8
*base
= get_hwbase(dev
);
1915 unregister_netdev(dev
);
1917 /* special op: write back the misordered MAC address - otherwise
1918 * the next nv_probe would see a wrong address.
1920 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
1921 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
1923 /* free all structures */
1924 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
), np
->rx_ring
, np
->ring_addr
);
1925 iounmap(get_hwbase(dev
));
1926 pci_release_regions(pci_dev
);
1927 pci_disable_device(pci_dev
);
1929 pci_set_drvdata(pci_dev
, NULL
);
1932 static struct pci_device_id pci_tbl
[] = {
1933 { /* nForce Ethernet Controller */
1934 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1935 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_1
,
1936 .subvendor
= PCI_ANY_ID
,
1937 .subdevice
= PCI_ANY_ID
,
1938 .driver_data
= DEV_IRQMASK_1
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
1940 { /* nForce2 Ethernet Controller */
1941 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1942 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_2
,
1943 .subvendor
= PCI_ANY_ID
,
1944 .subdevice
= PCI_ANY_ID
,
1945 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
1947 { /* nForce3 Ethernet Controller */
1948 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1949 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_3
,
1950 .subvendor
= PCI_ANY_ID
,
1951 .subdevice
= PCI_ANY_ID
,
1952 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
1954 { /* nForce3 Ethernet Controller */
1955 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1956 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_4
,
1957 .subvendor
= PCI_ANY_ID
,
1958 .subdevice
= PCI_ANY_ID
,
1959 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
1961 { /* nForce3 Ethernet Controller */
1962 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1963 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_5
,
1964 .subvendor
= PCI_ANY_ID
,
1965 .subdevice
= PCI_ANY_ID
,
1966 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
1968 { /* nForce3 Ethernet Controller */
1969 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1970 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_6
,
1971 .subvendor
= PCI_ANY_ID
,
1972 .subdevice
= PCI_ANY_ID
,
1973 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
1975 { /* nForce3 Ethernet Controller */
1976 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1977 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_7
,
1978 .subvendor
= PCI_ANY_ID
,
1979 .subdevice
= PCI_ANY_ID
,
1980 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
1982 { /* CK804 Ethernet Controller */
1983 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1984 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_8
,
1985 .subvendor
= PCI_ANY_ID
,
1986 .subdevice
= PCI_ANY_ID
,
1987 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
1989 { /* CK804 Ethernet Controller */
1990 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1991 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_9
,
1992 .subvendor
= PCI_ANY_ID
,
1993 .subdevice
= PCI_ANY_ID
,
1994 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
1996 { /* MCP04 Ethernet Controller */
1997 .vendor
= PCI_VENDOR_ID_NVIDIA
,
1998 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_10
,
1999 .subvendor
= PCI_ANY_ID
,
2000 .subdevice
= PCI_ANY_ID
,
2001 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
2003 { /* MCP04 Ethernet Controller */
2004 .vendor
= PCI_VENDOR_ID_NVIDIA
,
2005 .device
= PCI_DEVICE_ID_NVIDIA_NVENET_11
,
2006 .subvendor
= PCI_ANY_ID
,
2007 .subdevice
= PCI_ANY_ID
,
2008 .driver_data
= DEV_NEED_LASTPACKET1
|DEV_IRQMASK_2
|DEV_NEED_TIMERIRQ
,
2013 static struct pci_driver driver
= {
2014 .name
= "forcedeth",
2015 .id_table
= pci_tbl
,
2017 .remove
= __devexit_p(nv_remove
),
2021 static int __init
init_nic(void)
2023 printk(KERN_INFO
"forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION
);
2024 return pci_module_init(&driver
);
2027 static void __exit
exit_nic(void)
2029 pci_unregister_driver(&driver
);
2032 module_param(max_interrupt_work
, int, 0);
2033 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
2035 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2036 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2037 MODULE_LICENSE("GPL");
2039 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
2041 module_init(init_nic
);
2042 module_exit(exit_nic
);